1 /* 2 * (C) Copyright 2015 Google, Inc 3 * (C) 2017 Theobroma Systems Design und Consulting GmbH 4 * 5 * SPDX-License-Identifier: GPL-2.0 6 */ 7 8 #include <common.h> 9 #include <clk-uclass.h> 10 #include <dm.h> 11 #include <dt-structs.h> 12 #include <errno.h> 13 #include <mapmem.h> 14 #include <syscon.h> 15 #include <bitfield.h> 16 #include <asm/io.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/cru_rk3399.h> 19 #include <asm/arch/hardware.h> 20 #include <dm/lists.h> 21 #include <dt-bindings/clock/rk3399-cru.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #if CONFIG_IS_ENABLED(OF_PLATDATA) 26 struct rk3399_clk_plat { 27 struct dtd_rockchip_rk3399_cru dtd; 28 }; 29 30 struct rk3399_pmuclk_plat { 31 struct dtd_rockchip_rk3399_pmucru dtd; 32 }; 33 #endif 34 35 struct pll_div { 36 u32 refdiv; 37 u32 fbdiv; 38 u32 postdiv1; 39 u32 postdiv2; 40 u32 frac; 41 u32 freq; 42 }; 43 44 #define RATE_TO_DIV(input_rate, output_rate) \ 45 ((input_rate) / (output_rate) - 1); 46 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 47 48 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ 49 .refdiv = _refdiv,\ 50 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ 51 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2, .freq = hz}; 52 53 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); 54 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2); 55 #if !defined(CONFIG_SPL_BUILD) 56 static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1); 57 #endif 58 static const struct pll_div apll_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1); 59 static const struct pll_div apll_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1); 60 61 static const struct pll_div *apll_cfgs[] = { 62 [APLL_1600_MHZ] = &apll_1600_cfg, 63 [APLL_600_MHZ] = &apll_600_cfg, 64 }; 65 66 enum { 67 /* PLL_CON0 */ 68 PLL_FBDIV_MASK = 0xfff, 69 PLL_FBDIV_SHIFT = 0, 70 71 /* PLL_CON1 */ 72 PLL_POSTDIV2_SHIFT = 12, 73 PLL_POSTDIV2_MASK = 0x7 << PLL_POSTDIV2_SHIFT, 74 PLL_POSTDIV1_SHIFT = 8, 75 PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT, 76 PLL_REFDIV_MASK = 0x3f, 77 PLL_REFDIV_SHIFT = 0, 78 79 /* PLL_CON2 */ 80 PLL_LOCK_STATUS_SHIFT = 31, 81 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, 82 PLL_FRACDIV_MASK = 0xffffff, 83 PLL_FRACDIV_SHIFT = 0, 84 85 /* PLL_CON3 */ 86 PLL_MODE_SHIFT = 8, 87 PLL_MODE_MASK = 3 << PLL_MODE_SHIFT, 88 PLL_MODE_SLOW = 0, 89 PLL_MODE_NORM, 90 PLL_MODE_DEEP, 91 PLL_DSMPD_SHIFT = 3, 92 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, 93 PLL_INTEGER_MODE = 1, 94 95 /* PMUCRU_CLKSEL_CON0 */ 96 PMU_PCLK_DIV_CON_MASK = 0x1f, 97 PMU_PCLK_DIV_CON_SHIFT = 0, 98 99 /* PMUCRU_CLKSEL_CON1 */ 100 SPI3_PLL_SEL_SHIFT = 7, 101 SPI3_PLL_SEL_MASK = 1 << SPI3_PLL_SEL_SHIFT, 102 SPI3_PLL_SEL_24M = 0, 103 SPI3_PLL_SEL_PPLL = 1, 104 SPI3_DIV_CON_SHIFT = 0x0, 105 SPI3_DIV_CON_MASK = 0x7f, 106 107 /* PMUCRU_CLKSEL_CON2 */ 108 I2C_DIV_CON_MASK = 0x7f, 109 CLK_I2C8_DIV_CON_SHIFT = 8, 110 CLK_I2C0_DIV_CON_SHIFT = 0, 111 112 /* PMUCRU_CLKSEL_CON3 */ 113 CLK_I2C4_DIV_CON_SHIFT = 0, 114 115 /* CLKSEL_CON0 / CLKSEL_CON2 */ 116 ACLKM_CORE_DIV_CON_MASK = 0x1f, 117 ACLKM_CORE_DIV_CON_SHIFT = 8, 118 CLK_CORE_PLL_SEL_MASK = 3, 119 CLK_CORE_PLL_SEL_SHIFT = 6, 120 CLK_CORE_PLL_SEL_ALPLL = 0x0, 121 CLK_CORE_PLL_SEL_ABPLL = 0x1, 122 CLK_CORE_PLL_SEL_DPLL = 0x10, 123 CLK_CORE_PLL_SEL_GPLL = 0x11, 124 CLK_CORE_DIV_MASK = 0x1f, 125 CLK_CORE_DIV_SHIFT = 0, 126 127 /* CLKSEL_CON1 / CLKSEL_CON3 */ 128 PCLK_DBG_DIV_MASK = 0x1f, 129 PCLK_DBG_DIV_SHIFT = 0x8, 130 ATCLK_CORE_DIV_MASK = 0x1f, 131 ATCLK_CORE_DIV_SHIFT = 0, 132 133 /* CLKSEL_CON14 */ 134 PCLK_PERIHP_DIV_CON_SHIFT = 12, 135 PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT, 136 HCLK_PERIHP_DIV_CON_SHIFT = 8, 137 HCLK_PERIHP_DIV_CON_MASK = 3 << HCLK_PERIHP_DIV_CON_SHIFT, 138 ACLK_PERIHP_PLL_SEL_SHIFT = 7, 139 ACLK_PERIHP_PLL_SEL_MASK = 1 << ACLK_PERIHP_PLL_SEL_SHIFT, 140 ACLK_PERIHP_PLL_SEL_CPLL = 0, 141 ACLK_PERIHP_PLL_SEL_GPLL = 1, 142 ACLK_PERIHP_DIV_CON_SHIFT = 0, 143 ACLK_PERIHP_DIV_CON_MASK = 0x1f, 144 145 /* CLKSEL_CON21 */ 146 ACLK_EMMC_PLL_SEL_SHIFT = 7, 147 ACLK_EMMC_PLL_SEL_MASK = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT, 148 ACLK_EMMC_PLL_SEL_GPLL = 0x1, 149 ACLK_EMMC_DIV_CON_SHIFT = 0, 150 ACLK_EMMC_DIV_CON_MASK = 0x1f, 151 152 /* CLKSEL_CON22 */ 153 CLK_EMMC_PLL_SHIFT = 8, 154 CLK_EMMC_PLL_MASK = 0x7 << CLK_EMMC_PLL_SHIFT, 155 CLK_EMMC_PLL_SEL_GPLL = 0x1, 156 CLK_EMMC_PLL_SEL_24M = 0x5, 157 CLK_EMMC_DIV_CON_SHIFT = 0, 158 CLK_EMMC_DIV_CON_MASK = 0x7f << CLK_EMMC_DIV_CON_SHIFT, 159 160 /* CLKSEL_CON23 */ 161 PCLK_PERILP0_DIV_CON_SHIFT = 12, 162 PCLK_PERILP0_DIV_CON_MASK = 0x7 << PCLK_PERILP0_DIV_CON_SHIFT, 163 HCLK_PERILP0_DIV_CON_SHIFT = 8, 164 HCLK_PERILP0_DIV_CON_MASK = 3 << HCLK_PERILP0_DIV_CON_SHIFT, 165 ACLK_PERILP0_PLL_SEL_SHIFT = 7, 166 ACLK_PERILP0_PLL_SEL_MASK = 1 << ACLK_PERILP0_PLL_SEL_SHIFT, 167 ACLK_PERILP0_PLL_SEL_CPLL = 0, 168 ACLK_PERILP0_PLL_SEL_GPLL = 1, 169 ACLK_PERILP0_DIV_CON_SHIFT = 0, 170 ACLK_PERILP0_DIV_CON_MASK = 0x1f, 171 172 /* CLKSEL_CON25 */ 173 PCLK_PERILP1_DIV_CON_SHIFT = 8, 174 PCLK_PERILP1_DIV_CON_MASK = 0x7 << PCLK_PERILP1_DIV_CON_SHIFT, 175 HCLK_PERILP1_PLL_SEL_SHIFT = 7, 176 HCLK_PERILP1_PLL_SEL_MASK = 1 << HCLK_PERILP1_PLL_SEL_SHIFT, 177 HCLK_PERILP1_PLL_SEL_CPLL = 0, 178 HCLK_PERILP1_PLL_SEL_GPLL = 1, 179 HCLK_PERILP1_DIV_CON_SHIFT = 0, 180 HCLK_PERILP1_DIV_CON_MASK = 0x1f, 181 182 /* CLKSEL_CON26 */ 183 CLK_SARADC_DIV_CON_SHIFT = 8, 184 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8), 185 CLK_SARADC_DIV_CON_WIDTH = 8, 186 187 /* CLKSEL_CON27 */ 188 CLK_TSADC_SEL_X24M = 0x0, 189 CLK_TSADC_SEL_SHIFT = 15, 190 CLK_TSADC_SEL_MASK = 1 << CLK_TSADC_SEL_SHIFT, 191 CLK_TSADC_DIV_CON_SHIFT = 0, 192 CLK_TSADC_DIV_CON_MASK = 0x3ff, 193 194 /* CLKSEL_CON47 & CLKSEL_CON48 */ 195 ACLK_VOP_PLL_SEL_SHIFT = 6, 196 ACLK_VOP_PLL_SEL_MASK = 0x3 << ACLK_VOP_PLL_SEL_SHIFT, 197 ACLK_VOP_PLL_SEL_CPLL = 0x1, 198 ACLK_VOP_DIV_CON_SHIFT = 0, 199 ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT, 200 201 /* CLKSEL_CON49 & CLKSEL_CON50 */ 202 DCLK_VOP_DCLK_SEL_SHIFT = 11, 203 DCLK_VOP_DCLK_SEL_MASK = 1 << DCLK_VOP_DCLK_SEL_SHIFT, 204 DCLK_VOP_DCLK_SEL_DIVOUT = 0, 205 DCLK_VOP_PLL_SEL_SHIFT = 8, 206 DCLK_VOP_PLL_SEL_MASK = 3 << DCLK_VOP_PLL_SEL_SHIFT, 207 DCLK_VOP_PLL_SEL_VPLL = 0, 208 DCLK_VOP_DIV_CON_MASK = 0xff, 209 DCLK_VOP_DIV_CON_SHIFT = 0, 210 211 /* CLKSEL_CON58 */ 212 CLK_SPI_PLL_SEL_WIDTH = 1, 213 CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1), 214 CLK_SPI_PLL_SEL_CPLL = 0, 215 CLK_SPI_PLL_SEL_GPLL = 1, 216 CLK_SPI_PLL_DIV_CON_WIDTH = 7, 217 CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1), 218 219 CLK_SPI5_PLL_DIV_CON_SHIFT = 8, 220 CLK_SPI5_PLL_SEL_SHIFT = 15, 221 222 /* CLKSEL_CON59 */ 223 CLK_SPI1_PLL_SEL_SHIFT = 15, 224 CLK_SPI1_PLL_DIV_CON_SHIFT = 8, 225 CLK_SPI0_PLL_SEL_SHIFT = 7, 226 CLK_SPI0_PLL_DIV_CON_SHIFT = 0, 227 228 /* CLKSEL_CON60 */ 229 CLK_SPI4_PLL_SEL_SHIFT = 15, 230 CLK_SPI4_PLL_DIV_CON_SHIFT = 8, 231 CLK_SPI2_PLL_SEL_SHIFT = 7, 232 CLK_SPI2_PLL_DIV_CON_SHIFT = 0, 233 234 /* CLKSEL_CON61 */ 235 CLK_I2C_PLL_SEL_MASK = 1, 236 CLK_I2C_PLL_SEL_CPLL = 0, 237 CLK_I2C_PLL_SEL_GPLL = 1, 238 CLK_I2C5_PLL_SEL_SHIFT = 15, 239 CLK_I2C5_DIV_CON_SHIFT = 8, 240 CLK_I2C1_PLL_SEL_SHIFT = 7, 241 CLK_I2C1_DIV_CON_SHIFT = 0, 242 243 /* CLKSEL_CON62 */ 244 CLK_I2C6_PLL_SEL_SHIFT = 15, 245 CLK_I2C6_DIV_CON_SHIFT = 8, 246 CLK_I2C2_PLL_SEL_SHIFT = 7, 247 CLK_I2C2_DIV_CON_SHIFT = 0, 248 249 /* CLKSEL_CON63 */ 250 CLK_I2C7_PLL_SEL_SHIFT = 15, 251 CLK_I2C7_DIV_CON_SHIFT = 8, 252 CLK_I2C3_PLL_SEL_SHIFT = 7, 253 CLK_I2C3_DIV_CON_SHIFT = 0, 254 255 /* CRU_SOFTRST_CON4 */ 256 RESETN_DDR0_REQ_SHIFT = 8, 257 RESETN_DDR0_REQ_MASK = 1 << RESETN_DDR0_REQ_SHIFT, 258 RESETN_DDRPHY0_REQ_SHIFT = 9, 259 RESETN_DDRPHY0_REQ_MASK = 1 << RESETN_DDRPHY0_REQ_SHIFT, 260 RESETN_DDR1_REQ_SHIFT = 12, 261 RESETN_DDR1_REQ_MASK = 1 << RESETN_DDR1_REQ_SHIFT, 262 RESETN_DDRPHY1_REQ_SHIFT = 13, 263 RESETN_DDRPHY1_REQ_MASK = 1 << RESETN_DDRPHY1_REQ_SHIFT, 264 }; 265 266 #define VCO_MAX_KHZ (3200 * (MHz / KHz)) 267 #define VCO_MIN_KHZ (800 * (MHz / KHz)) 268 #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz)) 269 #define OUTPUT_MIN_KHZ (16 * (MHz / KHz)) 270 271 /* 272 * the div restructions of pll in integer mode, these are defined in 273 * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0 274 */ 275 #define PLL_DIV_MIN 16 276 #define PLL_DIV_MAX 3200 277 278 /* 279 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63): 280 * Formulas also embedded within the Fractional PLL Verilog model: 281 * If DSMPD = 1 (DSM is disabled, "integer mode") 282 * FOUTVCO = FREF / REFDIV * FBDIV 283 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 284 * Where: 285 * FOUTVCO = Fractional PLL non-divided output frequency 286 * FOUTPOSTDIV = Fractional PLL divided output frequency 287 * (output of second post divider) 288 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input) 289 * REFDIV = Fractional PLL input reference clock divider 290 * FBDIV = Integer value programmed into feedback divide 291 * 292 */ 293 static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div) 294 { 295 /* All 8 PLLs have same VCO and output frequency range restrictions. */ 296 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; 297 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; 298 299 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, " 300 "postdiv2=%d, vco=%u khz, output=%u khz\n", 301 pll_con, div->fbdiv, div->refdiv, div->postdiv1, 302 div->postdiv2, vco_khz, output_khz); 303 assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ && 304 output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ && 305 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); 306 307 /* 308 * When power on or changing PLL setting, 309 * we must force PLL into slow mode to ensure output stable clock. 310 */ 311 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, 312 PLL_MODE_SLOW << PLL_MODE_SHIFT); 313 314 /* use integer mode */ 315 rk_clrsetreg(&pll_con[3], PLL_DSMPD_MASK, 316 PLL_INTEGER_MODE << PLL_DSMPD_SHIFT); 317 318 rk_clrsetreg(&pll_con[0], PLL_FBDIV_MASK, 319 div->fbdiv << PLL_FBDIV_SHIFT); 320 rk_clrsetreg(&pll_con[1], 321 PLL_POSTDIV2_MASK | PLL_POSTDIV1_MASK | 322 PLL_REFDIV_MASK | PLL_REFDIV_SHIFT, 323 (div->postdiv2 << PLL_POSTDIV2_SHIFT) | 324 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | 325 (div->refdiv << PLL_REFDIV_SHIFT)); 326 327 /* waiting for pll lock */ 328 while (!(readl(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT))) 329 udelay(1); 330 331 /* pll enter normal mode */ 332 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, 333 PLL_MODE_NORM << PLL_MODE_SHIFT); 334 } 335 336 static int pll_para_config(u32 freq_hz, struct pll_div *div) 337 { 338 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; 339 u32 postdiv1, postdiv2 = 1; 340 u32 fref_khz; 341 u32 diff_khz, best_diff_khz; 342 const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16; 343 const u32 max_postdiv1 = 7, max_postdiv2 = 7; 344 u32 vco_khz; 345 u32 freq_khz = freq_hz / KHz; 346 347 if (!freq_hz) { 348 printf("%s: the frequency can't be 0 Hz\n", __func__); 349 return -1; 350 } 351 352 postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz); 353 if (postdiv1 > max_postdiv1) { 354 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); 355 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); 356 } 357 358 vco_khz = freq_khz * postdiv1 * postdiv2; 359 360 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || 361 postdiv2 > max_postdiv2) { 362 printf("%s: Cannot find out a supported VCO" 363 " for Frequency (%uHz).\n", __func__, freq_hz); 364 return -1; 365 } 366 367 div->postdiv1 = postdiv1; 368 div->postdiv2 = postdiv2; 369 370 best_diff_khz = vco_khz; 371 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { 372 fref_khz = ref_khz / refdiv; 373 374 fbdiv = vco_khz / fref_khz; 375 if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv)) 376 continue; 377 diff_khz = vco_khz - fbdiv * fref_khz; 378 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) { 379 fbdiv++; 380 diff_khz = fref_khz - diff_khz; 381 } 382 383 if (diff_khz >= best_diff_khz) 384 continue; 385 386 best_diff_khz = diff_khz; 387 div->refdiv = refdiv; 388 div->fbdiv = fbdiv; 389 } 390 391 if (best_diff_khz > 4 * (MHz/KHz)) { 392 printf("%s: Failed to match output frequency %u, " 393 "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz, 394 best_diff_khz * KHz); 395 return -1; 396 } 397 return 0; 398 } 399 400 void rk3399_configure_cpu(struct rk3399_cru *cru, 401 enum apll_frequencies freq, 402 enum cpu_cluster cluster) 403 { 404 u32 aclkm_div; 405 u32 pclk_dbg_div; 406 u32 atclk_div, apll_hz; 407 int con_base, parent; 408 u32 *pll_con; 409 410 switch (cluster) { 411 case CPU_CLUSTER_LITTLE: 412 con_base = 0; 413 parent = CLK_CORE_PLL_SEL_ALPLL; 414 pll_con = &cru->apll_l_con[0]; 415 break; 416 case CPU_CLUSTER_BIG: 417 default: 418 con_base = 2; 419 parent = CLK_CORE_PLL_SEL_ABPLL; 420 pll_con = &cru->apll_b_con[0]; 421 break; 422 } 423 424 apll_hz = apll_cfgs[freq]->freq; 425 rkclk_set_pll(pll_con, apll_cfgs[freq]); 426 427 aclkm_div = apll_hz / ACLKM_CORE_HZ - 1; 428 assert((aclkm_div + 1) * ACLKM_CORE_HZ == apll_hz && 429 aclkm_div < 0x1f); 430 431 pclk_dbg_div = apll_hz / PCLK_DBG_HZ - 1; 432 assert((pclk_dbg_div + 1) * PCLK_DBG_HZ == apll_hz && 433 pclk_dbg_div < 0x1f); 434 435 atclk_div = apll_hz / ATCLK_CORE_HZ - 1; 436 assert((atclk_div + 1) * ATCLK_CORE_HZ == apll_hz && 437 atclk_div < 0x1f); 438 439 rk_clrsetreg(&cru->clksel_con[con_base], 440 ACLKM_CORE_DIV_CON_MASK | CLK_CORE_PLL_SEL_MASK | 441 CLK_CORE_DIV_MASK, 442 aclkm_div << ACLKM_CORE_DIV_CON_SHIFT | 443 parent << CLK_CORE_PLL_SEL_SHIFT | 444 0 << CLK_CORE_DIV_SHIFT); 445 446 rk_clrsetreg(&cru->clksel_con[con_base + 1], 447 PCLK_DBG_DIV_MASK | ATCLK_CORE_DIV_MASK, 448 pclk_dbg_div << PCLK_DBG_DIV_SHIFT | 449 atclk_div << ATCLK_CORE_DIV_SHIFT); 450 } 451 #define I2C_CLK_REG_MASK(bus) \ 452 (I2C_DIV_CON_MASK << \ 453 CLK_I2C ##bus## _DIV_CON_SHIFT | \ 454 CLK_I2C_PLL_SEL_MASK << \ 455 CLK_I2C ##bus## _PLL_SEL_SHIFT) 456 457 #define I2C_CLK_REG_VALUE(bus, clk_div) \ 458 ((clk_div - 1) << \ 459 CLK_I2C ##bus## _DIV_CON_SHIFT | \ 460 CLK_I2C_PLL_SEL_GPLL << \ 461 CLK_I2C ##bus## _PLL_SEL_SHIFT) 462 463 #define I2C_CLK_DIV_VALUE(con, bus) \ 464 (con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \ 465 I2C_DIV_CON_MASK; 466 467 #define I2C_PMUCLK_REG_MASK(bus) \ 468 (I2C_DIV_CON_MASK << \ 469 CLK_I2C ##bus## _DIV_CON_SHIFT) 470 471 #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \ 472 ((clk_div - 1) << \ 473 CLK_I2C ##bus## _DIV_CON_SHIFT) 474 475 static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id) 476 { 477 u32 div, con; 478 479 switch (clk_id) { 480 case SCLK_I2C1: 481 con = readl(&cru->clksel_con[61]); 482 div = I2C_CLK_DIV_VALUE(con, 1); 483 break; 484 case SCLK_I2C2: 485 con = readl(&cru->clksel_con[62]); 486 div = I2C_CLK_DIV_VALUE(con, 2); 487 break; 488 case SCLK_I2C3: 489 con = readl(&cru->clksel_con[63]); 490 div = I2C_CLK_DIV_VALUE(con, 3); 491 break; 492 case SCLK_I2C5: 493 con = readl(&cru->clksel_con[61]); 494 div = I2C_CLK_DIV_VALUE(con, 5); 495 break; 496 case SCLK_I2C6: 497 con = readl(&cru->clksel_con[62]); 498 div = I2C_CLK_DIV_VALUE(con, 6); 499 break; 500 case SCLK_I2C7: 501 con = readl(&cru->clksel_con[63]); 502 div = I2C_CLK_DIV_VALUE(con, 7); 503 break; 504 default: 505 printf("do not support this i2c bus\n"); 506 return -EINVAL; 507 } 508 509 return DIV_TO_RATE(GPLL_HZ, div); 510 } 511 512 static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) 513 { 514 int src_clk_div; 515 516 /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/ 517 src_clk_div = GPLL_HZ / hz; 518 assert(src_clk_div - 1 <= 127); 519 520 switch (clk_id) { 521 case SCLK_I2C1: 522 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(1), 523 I2C_CLK_REG_VALUE(1, src_clk_div)); 524 break; 525 case SCLK_I2C2: 526 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(2), 527 I2C_CLK_REG_VALUE(2, src_clk_div)); 528 break; 529 case SCLK_I2C3: 530 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(3), 531 I2C_CLK_REG_VALUE(3, src_clk_div)); 532 break; 533 case SCLK_I2C5: 534 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(5), 535 I2C_CLK_REG_VALUE(5, src_clk_div)); 536 break; 537 case SCLK_I2C6: 538 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(6), 539 I2C_CLK_REG_VALUE(6, src_clk_div)); 540 break; 541 case SCLK_I2C7: 542 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(7), 543 I2C_CLK_REG_VALUE(7, src_clk_div)); 544 break; 545 default: 546 printf("do not support this i2c bus\n"); 547 return -EINVAL; 548 } 549 550 return rk3399_i2c_get_clk(cru, clk_id); 551 } 552 553 /* 554 * RK3399 SPI clocks have a common divider-width (7 bits) and a single bit 555 * to select either CPLL or GPLL as the clock-parent. The location within 556 * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable. 557 */ 558 559 struct spi_clkreg { 560 uint8_t reg; /* CLKSEL_CON[reg] register in CRU */ 561 uint8_t div_shift; 562 uint8_t sel_shift; 563 }; 564 565 /* 566 * The entries are numbered relative to their offset from SCLK_SPI0. 567 * 568 * Note that SCLK_SPI3 (which is configured via PMUCRU and requires different 569 * logic is not supported). 570 */ 571 static const struct spi_clkreg spi_clkregs[] = { 572 [0] = { .reg = 59, 573 .div_shift = CLK_SPI0_PLL_DIV_CON_SHIFT, 574 .sel_shift = CLK_SPI0_PLL_SEL_SHIFT, }, 575 [1] = { .reg = 59, 576 .div_shift = CLK_SPI1_PLL_DIV_CON_SHIFT, 577 .sel_shift = CLK_SPI1_PLL_SEL_SHIFT, }, 578 [2] = { .reg = 60, 579 .div_shift = CLK_SPI2_PLL_DIV_CON_SHIFT, 580 .sel_shift = CLK_SPI2_PLL_SEL_SHIFT, }, 581 [3] = { .reg = 60, 582 .div_shift = CLK_SPI4_PLL_DIV_CON_SHIFT, 583 .sel_shift = CLK_SPI4_PLL_SEL_SHIFT, }, 584 [4] = { .reg = 58, 585 .div_shift = CLK_SPI5_PLL_DIV_CON_SHIFT, 586 .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, }, 587 }; 588 589 static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id) 590 { 591 const struct spi_clkreg *spiclk = NULL; 592 u32 div, val; 593 594 switch (clk_id) { 595 case SCLK_SPI0 ... SCLK_SPI5: 596 spiclk = &spi_clkregs[clk_id - SCLK_SPI0]; 597 break; 598 599 default: 600 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id); 601 return -EINVAL; 602 } 603 604 val = readl(&cru->clksel_con[spiclk->reg]); 605 div = bitfield_extract(val, spiclk->div_shift, 606 CLK_SPI_PLL_DIV_CON_WIDTH); 607 608 return DIV_TO_RATE(GPLL_HZ, div); 609 } 610 611 static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) 612 { 613 const struct spi_clkreg *spiclk = NULL; 614 int src_clk_div; 615 616 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; 617 assert(src_clk_div < 128); 618 619 switch (clk_id) { 620 case SCLK_SPI1 ... SCLK_SPI5: 621 spiclk = &spi_clkregs[clk_id - SCLK_SPI0]; 622 break; 623 624 default: 625 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id); 626 return -EINVAL; 627 } 628 629 rk_clrsetreg(&cru->clksel_con[spiclk->reg], 630 ((CLK_SPI_PLL_DIV_CON_MASK << spiclk->div_shift) | 631 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)), 632 ((src_clk_div << spiclk->div_shift) | 633 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift))); 634 635 return rk3399_spi_get_clk(cru, clk_id); 636 } 637 638 static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz) 639 { 640 struct pll_div vpll_config = {0}; 641 int aclk_vop = 198*MHz; 642 void *aclkreg_addr, *dclkreg_addr; 643 u32 div; 644 645 switch (clk_id) { 646 case DCLK_VOP0: 647 aclkreg_addr = &cru->clksel_con[47]; 648 dclkreg_addr = &cru->clksel_con[49]; 649 break; 650 case DCLK_VOP1: 651 aclkreg_addr = &cru->clksel_con[48]; 652 dclkreg_addr = &cru->clksel_con[50]; 653 break; 654 default: 655 return -EINVAL; 656 } 657 /* vop aclk source clk: cpll */ 658 div = CPLL_HZ / aclk_vop; 659 assert(div - 1 <= 31); 660 661 rk_clrsetreg(aclkreg_addr, 662 ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK, 663 ACLK_VOP_PLL_SEL_CPLL << ACLK_VOP_PLL_SEL_SHIFT | 664 (div - 1) << ACLK_VOP_DIV_CON_SHIFT); 665 666 /* vop dclk source from vpll, and equals to vpll(means div == 1) */ 667 if (pll_para_config(hz, &vpll_config)) 668 return -1; 669 670 rkclk_set_pll(&cru->vpll_con[0], &vpll_config); 671 672 rk_clrsetreg(dclkreg_addr, 673 DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_PLL_SEL_MASK| 674 DCLK_VOP_DIV_CON_MASK, 675 DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT | 676 DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT | 677 (1 - 1) << DCLK_VOP_DIV_CON_SHIFT); 678 679 return hz; 680 } 681 682 static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id) 683 { 684 u32 div, con; 685 686 switch (clk_id) { 687 case HCLK_SDMMC: 688 case SCLK_SDMMC: 689 con = readl(&cru->clksel_con[16]); 690 /* dwmmc controller have internal div 2 */ 691 div = 2; 692 break; 693 case SCLK_EMMC: 694 con = readl(&cru->clksel_con[21]); 695 div = 1; 696 break; 697 default: 698 return -EINVAL; 699 } 700 701 div *= (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT; 702 if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT 703 == CLK_EMMC_PLL_SEL_24M) 704 return DIV_TO_RATE(OSC_HZ, div); 705 else 706 return DIV_TO_RATE(GPLL_HZ, div); 707 } 708 709 static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru, 710 ulong clk_id, ulong set_rate) 711 { 712 int src_clk_div; 713 int aclk_emmc = 198*MHz; 714 715 switch (clk_id) { 716 case HCLK_SDMMC: 717 case SCLK_SDMMC: 718 /* Select clk_sdmmc source from GPLL by default */ 719 /* mmc clock defaulg div 2 internal, provide double in cru */ 720 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate); 721 722 if (src_clk_div > 128) { 723 /* use 24MHz source for 400KHz clock */ 724 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); 725 assert(src_clk_div - 1 < 128); 726 rk_clrsetreg(&cru->clksel_con[16], 727 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 728 CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT | 729 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 730 } else { 731 rk_clrsetreg(&cru->clksel_con[16], 732 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 733 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | 734 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 735 } 736 break; 737 case SCLK_EMMC: 738 /* Select aclk_emmc source from GPLL */ 739 src_clk_div = DIV_ROUND_UP(GPLL_HZ , aclk_emmc); 740 assert(src_clk_div - 1 < 32); 741 742 rk_clrsetreg(&cru->clksel_con[21], 743 ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK, 744 ACLK_EMMC_PLL_SEL_GPLL << ACLK_EMMC_PLL_SEL_SHIFT | 745 (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT); 746 747 /* Select clk_emmc source from GPLL too */ 748 src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate); 749 assert(src_clk_div - 1 < 128); 750 751 rk_clrsetreg(&cru->clksel_con[22], 752 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 753 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | 754 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 755 break; 756 default: 757 return -EINVAL; 758 } 759 return rk3399_mmc_get_clk(cru, clk_id); 760 } 761 762 static ulong rk3399_gmac_set_clk(struct rk3399_cru *cru, ulong rate) 763 { 764 ulong ret; 765 766 /* 767 * The RGMII CLK can be derived either from an external "clkin" 768 * or can be generated from internally by a divider from SCLK_MAC. 769 */ 770 if (readl(&cru->clksel_con[19]) & BIT(4)) { 771 /* An external clock will always generate the right rate... */ 772 ret = rate; 773 } else { 774 /* 775 * No platform uses an internal clock to date. 776 * Implement this once it becomes necessary and print an error 777 * if someone tries to use it (while it remains unimplemented). 778 */ 779 pr_err("%s: internal clock is UNIMPLEMENTED\n", __func__); 780 ret = 0; 781 } 782 783 return ret; 784 } 785 786 #define PMUSGRF_DDR_RGN_CON16 0xff330040 787 static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru, 788 ulong set_rate) 789 { 790 struct pll_div dpll_cfg; 791 792 /* IC ECO bug, need to set this register */ 793 writel(0xc000c000, PMUSGRF_DDR_RGN_CON16); 794 795 /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */ 796 switch (set_rate) { 797 case 200*MHz: 798 dpll_cfg = (struct pll_div) 799 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1}; 800 break; 801 case 300*MHz: 802 dpll_cfg = (struct pll_div) 803 {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1}; 804 break; 805 case 666*MHz: 806 dpll_cfg = (struct pll_div) 807 {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1}; 808 break; 809 case 800*MHz: 810 dpll_cfg = (struct pll_div) 811 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}; 812 break; 813 case 933*MHz: 814 dpll_cfg = (struct pll_div) 815 {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1}; 816 break; 817 default: 818 pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate); 819 } 820 rkclk_set_pll(&cru->dpll_con[0], &dpll_cfg); 821 822 return set_rate; 823 } 824 825 static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru) 826 { 827 u32 div, val; 828 829 val = readl(&cru->clksel_con[26]); 830 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT, 831 CLK_SARADC_DIV_CON_WIDTH); 832 833 return DIV_TO_RATE(OSC_HZ, div); 834 } 835 836 static ulong rk3399_saradc_set_clk(struct rk3399_cru *cru, uint hz) 837 { 838 int src_clk_div; 839 840 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; 841 assert(src_clk_div <= 255); 842 843 rk_clrsetreg(&cru->clksel_con[26], 844 CLK_SARADC_DIV_CON_MASK, 845 src_clk_div << CLK_SARADC_DIV_CON_SHIFT); 846 847 return rk3399_saradc_get_clk(cru); 848 } 849 850 static ulong rk3399_clk_get_rate(struct clk *clk) 851 { 852 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 853 ulong rate = 0; 854 855 switch (clk->id) { 856 case 0 ... 63: 857 return 0; 858 case HCLK_SDMMC: 859 case SCLK_SDMMC: 860 case SCLK_EMMC: 861 rate = rk3399_mmc_get_clk(priv->cru, clk->id); 862 break; 863 case SCLK_I2C1: 864 case SCLK_I2C2: 865 case SCLK_I2C3: 866 case SCLK_I2C5: 867 case SCLK_I2C6: 868 case SCLK_I2C7: 869 rate = rk3399_i2c_get_clk(priv->cru, clk->id); 870 break; 871 case SCLK_SPI0...SCLK_SPI5: 872 rate = rk3399_spi_get_clk(priv->cru, clk->id); 873 break; 874 case SCLK_UART0: 875 case SCLK_UART1: 876 case SCLK_UART2: 877 case SCLK_UART3: 878 return 24000000; 879 break; 880 case PCLK_HDMI_CTRL: 881 break; 882 case DCLK_VOP0: 883 case DCLK_VOP1: 884 break; 885 case PCLK_EFUSE1024NS: 886 break; 887 case SCLK_SARADC: 888 rate = rk3399_saradc_get_clk(priv->cru); 889 break; 890 default: 891 return -ENOENT; 892 } 893 894 return rate; 895 } 896 897 static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) 898 { 899 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 900 ulong ret = 0; 901 902 switch (clk->id) { 903 case 0 ... 63: 904 return 0; 905 906 case ACLK_PERIHP: 907 case HCLK_PERIHP: 908 case PCLK_PERIHP: 909 return 0; 910 911 case ACLK_PERILP0: 912 case HCLK_PERILP0: 913 case PCLK_PERILP0: 914 return 0; 915 916 case ACLK_CCI: 917 return 0; 918 919 case HCLK_PERILP1: 920 case PCLK_PERILP1: 921 return 0; 922 923 case HCLK_SDMMC: 924 case SCLK_SDMMC: 925 case SCLK_EMMC: 926 ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate); 927 break; 928 case SCLK_MAC: 929 ret = rk3399_gmac_set_clk(priv->cru, rate); 930 break; 931 case SCLK_I2C1: 932 case SCLK_I2C2: 933 case SCLK_I2C3: 934 case SCLK_I2C5: 935 case SCLK_I2C6: 936 case SCLK_I2C7: 937 ret = rk3399_i2c_set_clk(priv->cru, clk->id, rate); 938 break; 939 case SCLK_SPI0...SCLK_SPI5: 940 ret = rk3399_spi_set_clk(priv->cru, clk->id, rate); 941 break; 942 case PCLK_HDMI_CTRL: 943 case PCLK_VIO_GRF: 944 /* the PCLK gates for video are enabled by default */ 945 break; 946 case DCLK_VOP0: 947 case DCLK_VOP1: 948 ret = rk3399_vop_set_clk(priv->cru, clk->id, rate); 949 break; 950 case SCLK_DDRCLK: 951 ret = rk3399_ddr_set_clk(priv->cru, rate); 952 break; 953 case PCLK_EFUSE1024NS: 954 break; 955 case SCLK_SARADC: 956 ret = rk3399_saradc_set_clk(priv->cru, rate); 957 break; 958 default: 959 return -ENOENT; 960 } 961 962 return ret; 963 } 964 965 static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk, struct clk *parent) 966 { 967 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 968 const char *clock_output_name; 969 int ret; 970 971 /* 972 * If the requested parent is in the same clock-controller and 973 * the id is SCLK_MAC ("clk_gmac"), switch to the internal clock. 974 */ 975 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC)) { 976 debug("%s: switching RGMII to SCLK_MAC\n", __func__); 977 rk_clrreg(&priv->cru->clksel_con[19], BIT(4)); 978 return 0; 979 } 980 981 /* 982 * Otherwise, we need to check the clock-output-names of the 983 * requested parent to see if the requested id is "clkin_gmac". 984 */ 985 ret = dev_read_string_index(parent->dev, "clock-output-names", 986 parent->id, &clock_output_name); 987 if (ret < 0) 988 return -ENODATA; 989 990 /* If this is "clkin_gmac", switch to the external clock input */ 991 if (!strcmp(clock_output_name, "clkin_gmac")) { 992 debug("%s: switching RGMII to CLKIN\n", __func__); 993 rk_setreg(&priv->cru->clksel_con[19], BIT(4)); 994 return 0; 995 } 996 997 return -EINVAL; 998 } 999 1000 static int __maybe_unused rk3399_clk_set_parent(struct clk *clk, struct clk *parent) 1001 { 1002 switch (clk->id) { 1003 case SCLK_RMII_SRC: 1004 return rk3399_gmac_set_parent(clk, parent); 1005 } 1006 1007 debug("%s: unsupported clk %ld\n", __func__, clk->id); 1008 return -ENOENT; 1009 } 1010 1011 static int rk3399_clk_enable(struct clk *clk) 1012 { 1013 switch (clk->id) { 1014 case HCLK_HOST0: 1015 case HCLK_HOST0_ARB: 1016 case HCLK_HOST1: 1017 case HCLK_HOST1_ARB: 1018 return 0; 1019 } 1020 1021 debug("%s: unsupported clk %ld\n", __func__, clk->id); 1022 return -ENOENT; 1023 } 1024 1025 static struct clk_ops rk3399_clk_ops = { 1026 .get_rate = rk3399_clk_get_rate, 1027 .set_rate = rk3399_clk_set_rate, 1028 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 1029 .set_parent = rk3399_clk_set_parent, 1030 #endif 1031 .enable = rk3399_clk_enable, 1032 }; 1033 1034 static void rkclk_init(struct rk3399_cru *cru) 1035 { 1036 u32 aclk_div; 1037 u32 hclk_div; 1038 u32 pclk_div; 1039 1040 rk3399_configure_cpu(cru, APLL_600_MHZ, CPU_CLUSTER_LITTLE); 1041 1042 /* 1043 * some cru registers changed by bootrom, we'd better reset them to 1044 * reset/default values described in TRM to avoid confusion in kernel. 1045 * Please consider these three lines as a fix of bootrom bug. 1046 */ 1047 rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101); 1048 rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f); 1049 rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003); 1050 1051 /* configure gpll cpll */ 1052 rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg); 1053 rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg); 1054 1055 /* configure perihp aclk, hclk, pclk */ 1056 aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1; 1057 assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); 1058 1059 hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1; 1060 assert((hclk_div + 1) * PERIHP_HCLK_HZ == 1061 PERIHP_ACLK_HZ && (hclk_div <= 0x3)); 1062 1063 pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1; 1064 assert((pclk_div + 1) * PERIHP_PCLK_HZ == 1065 PERIHP_ACLK_HZ && (pclk_div <= 0x7)); 1066 1067 rk_clrsetreg(&cru->clksel_con[14], 1068 PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK | 1069 ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK, 1070 pclk_div << PCLK_PERIHP_DIV_CON_SHIFT | 1071 hclk_div << HCLK_PERIHP_DIV_CON_SHIFT | 1072 ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT | 1073 aclk_div << ACLK_PERIHP_DIV_CON_SHIFT); 1074 1075 /* configure perilp0 aclk, hclk, pclk */ 1076 aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1; 1077 assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); 1078 1079 hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1; 1080 assert((hclk_div + 1) * PERILP0_HCLK_HZ == 1081 PERILP0_ACLK_HZ && (hclk_div <= 0x3)); 1082 1083 pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1; 1084 assert((pclk_div + 1) * PERILP0_PCLK_HZ == 1085 PERILP0_ACLK_HZ && (pclk_div <= 0x7)); 1086 1087 rk_clrsetreg(&cru->clksel_con[23], 1088 PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK | 1089 ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK, 1090 pclk_div << PCLK_PERILP0_DIV_CON_SHIFT | 1091 hclk_div << HCLK_PERILP0_DIV_CON_SHIFT | 1092 ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT | 1093 aclk_div << ACLK_PERILP0_DIV_CON_SHIFT); 1094 1095 /* perilp1 hclk select gpll as source */ 1096 hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1; 1097 assert((hclk_div + 1) * PERILP1_HCLK_HZ == 1098 GPLL_HZ && (hclk_div <= 0x1f)); 1099 1100 pclk_div = PERILP1_HCLK_HZ / PERILP1_PCLK_HZ - 1; 1101 assert((pclk_div + 1) * PERILP1_PCLK_HZ == 1102 PERILP1_HCLK_HZ && (pclk_div <= 0x7)); 1103 1104 rk_clrsetreg(&cru->clksel_con[25], 1105 PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK | 1106 HCLK_PERILP1_PLL_SEL_MASK, 1107 pclk_div << PCLK_PERILP1_DIV_CON_SHIFT | 1108 hclk_div << HCLK_PERILP1_DIV_CON_SHIFT | 1109 HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT); 1110 } 1111 1112 static int rk3399_clk_probe(struct udevice *dev) 1113 { 1114 struct rk3399_clk_priv *priv = dev_get_priv(dev); 1115 1116 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1117 struct rk3399_clk_plat *plat = dev_get_platdata(dev); 1118 1119 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); 1120 #endif 1121 rkclk_init(priv->cru); 1122 return 0; 1123 } 1124 1125 static int rk3399_clk_ofdata_to_platdata(struct udevice *dev) 1126 { 1127 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 1128 struct rk3399_clk_priv *priv = dev_get_priv(dev); 1129 1130 priv->cru = dev_read_addr_ptr(dev); 1131 #endif 1132 return 0; 1133 } 1134 1135 static int rk3399_clk_bind(struct udevice *dev) 1136 { 1137 int ret; 1138 struct udevice *sys_child, *sf_child; 1139 struct sysreset_reg *priv; 1140 struct softreset_reg *sf_priv; 1141 1142 /* The reset driver does not have a device node, so bind it here */ 1143 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", 1144 &sys_child); 1145 if (ret) { 1146 debug("Warning: No sysreset driver: ret=%d\n", ret); 1147 } else { 1148 priv = malloc(sizeof(struct sysreset_reg)); 1149 priv->glb_srst_fst_value = offsetof(struct rk3399_cru, 1150 glb_srst_fst_value); 1151 priv->glb_srst_snd_value = offsetof(struct rk3399_cru, 1152 glb_srst_snd_value); 1153 sys_child->priv = priv; 1154 } 1155 1156 ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset", 1157 dev_ofnode(dev), &sf_child); 1158 if (ret) { 1159 debug("Warning: No rockchip reset driver: ret=%d\n", ret); 1160 } else { 1161 sf_priv = malloc(sizeof(struct softreset_reg)); 1162 sf_priv->sf_reset_offset = offsetof(struct rk3399_cru, 1163 softrst_con[0]); 1164 sf_priv->sf_reset_num = 21; 1165 sf_child->priv = sf_priv; 1166 } 1167 1168 return 0; 1169 } 1170 1171 static const struct udevice_id rk3399_clk_ids[] = { 1172 { .compatible = "rockchip,rk3399-cru" }, 1173 { } 1174 }; 1175 1176 U_BOOT_DRIVER(clk_rk3399) = { 1177 .name = "rockchip_rk3399_cru", 1178 .id = UCLASS_CLK, 1179 .of_match = rk3399_clk_ids, 1180 .priv_auto_alloc_size = sizeof(struct rk3399_clk_priv), 1181 .ofdata_to_platdata = rk3399_clk_ofdata_to_platdata, 1182 .ops = &rk3399_clk_ops, 1183 .bind = rk3399_clk_bind, 1184 .probe = rk3399_clk_probe, 1185 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1186 .platdata_auto_alloc_size = sizeof(struct rk3399_clk_plat), 1187 #endif 1188 }; 1189 1190 static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id) 1191 { 1192 u32 div, con; 1193 1194 switch (clk_id) { 1195 case SCLK_I2C0_PMU: 1196 con = readl(&pmucru->pmucru_clksel[2]); 1197 div = I2C_CLK_DIV_VALUE(con, 0); 1198 break; 1199 case SCLK_I2C4_PMU: 1200 con = readl(&pmucru->pmucru_clksel[3]); 1201 div = I2C_CLK_DIV_VALUE(con, 4); 1202 break; 1203 case SCLK_I2C8_PMU: 1204 con = readl(&pmucru->pmucru_clksel[2]); 1205 div = I2C_CLK_DIV_VALUE(con, 8); 1206 break; 1207 default: 1208 printf("do not support this i2c bus\n"); 1209 return -EINVAL; 1210 } 1211 1212 return DIV_TO_RATE(PPLL_HZ, div); 1213 } 1214 1215 static ulong rk3399_i2c_set_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id, 1216 uint hz) 1217 { 1218 int src_clk_div; 1219 1220 src_clk_div = PPLL_HZ / hz; 1221 assert(src_clk_div - 1 < 127); 1222 1223 switch (clk_id) { 1224 case SCLK_I2C0_PMU: 1225 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(0), 1226 I2C_PMUCLK_REG_VALUE(0, src_clk_div)); 1227 break; 1228 case SCLK_I2C4_PMU: 1229 rk_clrsetreg(&pmucru->pmucru_clksel[3], I2C_PMUCLK_REG_MASK(4), 1230 I2C_PMUCLK_REG_VALUE(4, src_clk_div)); 1231 break; 1232 case SCLK_I2C8_PMU: 1233 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(8), 1234 I2C_PMUCLK_REG_VALUE(8, src_clk_div)); 1235 break; 1236 default: 1237 printf("do not support this i2c bus\n"); 1238 return -EINVAL; 1239 } 1240 1241 return DIV_TO_RATE(PPLL_HZ, src_clk_div); 1242 } 1243 1244 static ulong rk3399_pwm_get_clk(struct rk3399_pmucru *pmucru) 1245 { 1246 u32 div, con; 1247 1248 /* PWM closk rate is same as pclk_pmu */ 1249 con = readl(&pmucru->pmucru_clksel[0]); 1250 div = con & PMU_PCLK_DIV_CON_MASK; 1251 1252 return DIV_TO_RATE(PPLL_HZ, div); 1253 } 1254 1255 static ulong rk3399_pmuclk_get_rate(struct clk *clk) 1256 { 1257 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev); 1258 ulong rate = 0; 1259 1260 switch (clk->id) { 1261 case PCLK_RKPWM_PMU: 1262 rate = rk3399_pwm_get_clk(priv->pmucru); 1263 break; 1264 case SCLK_I2C0_PMU: 1265 case SCLK_I2C4_PMU: 1266 case SCLK_I2C8_PMU: 1267 rate = rk3399_i2c_get_pmuclk(priv->pmucru, clk->id); 1268 break; 1269 case SCLK_UART4_PMU: 1270 rate = 24000000; 1271 break; 1272 default: 1273 return -ENOENT; 1274 } 1275 1276 return rate; 1277 } 1278 1279 static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate) 1280 { 1281 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev); 1282 ulong ret = 0; 1283 1284 switch (clk->id) { 1285 case SCLK_I2C0_PMU: 1286 case SCLK_I2C4_PMU: 1287 case SCLK_I2C8_PMU: 1288 ret = rk3399_i2c_set_pmuclk(priv->pmucru, clk->id, rate); 1289 break; 1290 default: 1291 return -ENOENT; 1292 } 1293 1294 return ret; 1295 } 1296 1297 static struct clk_ops rk3399_pmuclk_ops = { 1298 .get_rate = rk3399_pmuclk_get_rate, 1299 .set_rate = rk3399_pmuclk_set_rate, 1300 }; 1301 1302 #ifndef CONFIG_SPL_BUILD 1303 static void pmuclk_init(struct rk3399_pmucru *pmucru) 1304 { 1305 u32 pclk_div; 1306 1307 /* configure pmu pll(ppll) */ 1308 rkclk_set_pll(&pmucru->ppll_con[0], &ppll_init_cfg); 1309 1310 /* configure pmu pclk */ 1311 pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1; 1312 assert((pclk_div + 1) * PMU_PCLK_HZ == PPLL_HZ && pclk_div <= 0x1f); 1313 rk_clrsetreg(&pmucru->pmucru_clksel[0], 1314 PMU_PCLK_DIV_CON_MASK, 1315 pclk_div << PMU_PCLK_DIV_CON_SHIFT); 1316 } 1317 #endif 1318 1319 static int rk3399_pmuclk_probe(struct udevice *dev) 1320 { 1321 #if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_SPL_BUILD) 1322 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); 1323 #endif 1324 1325 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1326 struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev); 1327 1328 priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); 1329 #endif 1330 1331 #ifndef CONFIG_SPL_BUILD 1332 pmuclk_init(priv->pmucru); 1333 #endif 1334 return 0; 1335 } 1336 1337 static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev) 1338 { 1339 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 1340 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); 1341 1342 priv->pmucru = dev_read_addr_ptr(dev); 1343 #endif 1344 return 0; 1345 } 1346 1347 static int rk3399_pmuclk_bind(struct udevice *dev) 1348 { 1349 int ret = 0; 1350 struct udevice *sf_child; 1351 struct softreset_reg *sf_priv; 1352 1353 ret = device_bind_driver_to_node(dev, "rockchip_reset", 1354 "reset", dev_ofnode(dev), 1355 &sf_child); 1356 if (ret) { 1357 debug("Warning: No rockchip reset driver: ret=%d\n", ret); 1358 } else { 1359 sf_priv = malloc(sizeof(struct softreset_reg)); 1360 sf_priv->sf_reset_offset = offsetof(struct rk3399_pmucru, 1361 pmucru_softrst_con[0]); 1362 sf_priv->sf_reset_num = 2; 1363 sf_child->priv = sf_priv; 1364 } 1365 1366 return 0; 1367 } 1368 1369 static const struct udevice_id rk3399_pmuclk_ids[] = { 1370 { .compatible = "rockchip,rk3399-pmucru" }, 1371 { } 1372 }; 1373 1374 U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = { 1375 .name = "rockchip_rk3399_pmucru", 1376 .id = UCLASS_CLK, 1377 .of_match = rk3399_pmuclk_ids, 1378 .priv_auto_alloc_size = sizeof(struct rk3399_pmuclk_priv), 1379 .ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata, 1380 .ops = &rk3399_pmuclk_ops, 1381 .probe = rk3399_pmuclk_probe, 1382 .bind = rk3399_pmuclk_bind, 1383 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1384 .platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat), 1385 #endif 1386 }; 1387