1 /* 2 * (C) Copyright 2015 Google, Inc 3 * (C) 2017 Theobroma Systems Design und Consulting GmbH 4 * 5 * SPDX-License-Identifier: GPL-2.0 6 */ 7 8 #include <common.h> 9 #include <clk-uclass.h> 10 #include <dm.h> 11 #include <dt-structs.h> 12 #include <errno.h> 13 #include <mapmem.h> 14 #include <syscon.h> 15 #include <bitfield.h> 16 #include <asm/io.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/cru_rk3399.h> 19 #include <asm/arch/hardware.h> 20 #include <dm/lists.h> 21 #include <dt-bindings/clock/rk3399-cru.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #if CONFIG_IS_ENABLED(OF_PLATDATA) 26 struct rk3399_clk_plat { 27 struct dtd_rockchip_rk3399_cru dtd; 28 }; 29 30 struct rk3399_pmuclk_plat { 31 struct dtd_rockchip_rk3399_pmucru dtd; 32 }; 33 #endif 34 35 struct pll_div { 36 u32 refdiv; 37 u32 fbdiv; 38 u32 postdiv1; 39 u32 postdiv2; 40 u32 frac; 41 u32 freq; 42 }; 43 44 #define RATE_TO_DIV(input_rate, output_rate) \ 45 ((input_rate) / (output_rate) - 1); 46 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 47 48 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ 49 .refdiv = _refdiv,\ 50 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ 51 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2, .freq = hz}; 52 53 #if !defined(CONFIG_SPL_BUILD) 54 static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1); 55 #endif 56 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 3, 1); 57 static const struct pll_div npll_init_cfg = PLL_DIVISORS(NPLL_HZ, 1, 3, 1); 58 static const struct pll_div apll_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1); 59 static const struct pll_div apll_816_cfg = PLL_DIVISORS(816 * MHz, 1, 2, 1); 60 static const struct pll_div apll_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1); 61 62 static const struct pll_div *apll_cfgs[] = { 63 [APLL_1600_MHZ] = &apll_1600_cfg, 64 [APLL_816_MHZ] = &apll_816_cfg, 65 [APLL_600_MHZ] = &apll_600_cfg, 66 }; 67 68 #ifndef CONFIG_SPL_BUILD 69 #define RK3399_CLK_DUMP(_id, _name, _iscru) \ 70 { \ 71 .id = _id, \ 72 .name = _name, \ 73 .is_cru = _iscru, \ 74 } 75 76 static const struct rk3399_clk_info clks_dump[] = { 77 RK3399_CLK_DUMP(PLL_APLLL, "aplll", true), 78 RK3399_CLK_DUMP(PLL_APLLB, "apllb", true), 79 RK3399_CLK_DUMP(PLL_DPLL, "dpll", true), 80 RK3399_CLK_DUMP(PLL_CPLL, "cpll", true), 81 RK3399_CLK_DUMP(PLL_GPLL, "gpll", true), 82 RK3399_CLK_DUMP(PLL_NPLL, "npll", true), 83 RK3399_CLK_DUMP(PLL_VPLL, "vpll", true), 84 RK3399_CLK_DUMP(ACLK_PERIHP, "aclk_perihp", true), 85 RK3399_CLK_DUMP(HCLK_PERIHP, "hclk_perihp", true), 86 RK3399_CLK_DUMP(PCLK_PERIHP, "pclk_perihp", true), 87 RK3399_CLK_DUMP(ACLK_PERILP0, "aclk_perilp0", true), 88 RK3399_CLK_DUMP(HCLK_PERILP0, "hclk_perilp0", true), 89 RK3399_CLK_DUMP(PCLK_PERILP0, "pclk_perilp0", true), 90 RK3399_CLK_DUMP(HCLK_PERILP1, "hclk_perilp1", true), 91 RK3399_CLK_DUMP(PCLK_PERILP1, "pclk_perilp1", true), 92 }; 93 #endif 94 95 enum { 96 /* PLL_CON0 */ 97 PLL_FBDIV_MASK = 0xfff, 98 PLL_FBDIV_SHIFT = 0, 99 100 /* PLL_CON1 */ 101 PLL_POSTDIV2_SHIFT = 12, 102 PLL_POSTDIV2_MASK = 0x7 << PLL_POSTDIV2_SHIFT, 103 PLL_POSTDIV1_SHIFT = 8, 104 PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT, 105 PLL_REFDIV_MASK = 0x3f, 106 PLL_REFDIV_SHIFT = 0, 107 108 /* PLL_CON2 */ 109 PLL_LOCK_STATUS_SHIFT = 31, 110 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, 111 PLL_FRACDIV_MASK = 0xffffff, 112 PLL_FRACDIV_SHIFT = 0, 113 114 /* PLL_CON3 */ 115 PLL_MODE_SHIFT = 8, 116 PLL_MODE_MASK = 3 << PLL_MODE_SHIFT, 117 PLL_MODE_SLOW = 0, 118 PLL_MODE_NORM, 119 PLL_MODE_DEEP, 120 PLL_DSMPD_SHIFT = 3, 121 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, 122 PLL_INTEGER_MODE = 1, 123 124 /* PMUCRU_CLKSEL_CON0 */ 125 PMU_PCLK_DIV_CON_MASK = 0x1f, 126 PMU_PCLK_DIV_CON_SHIFT = 0, 127 128 /* PMUCRU_CLKSEL_CON1 */ 129 SPI3_PLL_SEL_SHIFT = 7, 130 SPI3_PLL_SEL_MASK = 1 << SPI3_PLL_SEL_SHIFT, 131 SPI3_PLL_SEL_24M = 0, 132 SPI3_PLL_SEL_PPLL = 1, 133 SPI3_DIV_CON_SHIFT = 0x0, 134 SPI3_DIV_CON_MASK = 0x7f, 135 136 /* PMUCRU_CLKSEL_CON2 */ 137 I2C_DIV_CON_MASK = 0x7f, 138 CLK_I2C8_DIV_CON_SHIFT = 8, 139 CLK_I2C0_DIV_CON_SHIFT = 0, 140 141 /* PMUCRU_CLKSEL_CON3 */ 142 CLK_I2C4_DIV_CON_SHIFT = 0, 143 144 /* CLKSEL_CON0 / CLKSEL_CON2 */ 145 ACLKM_CORE_DIV_CON_MASK = 0x1f, 146 ACLKM_CORE_DIV_CON_SHIFT = 8, 147 CLK_CORE_PLL_SEL_MASK = 3, 148 CLK_CORE_PLL_SEL_SHIFT = 6, 149 CLK_CORE_PLL_SEL_ALPLL = 0x0, 150 CLK_CORE_PLL_SEL_ABPLL = 0x1, 151 CLK_CORE_PLL_SEL_DPLL = 0x10, 152 CLK_CORE_PLL_SEL_GPLL = 0x11, 153 CLK_CORE_DIV_MASK = 0x1f, 154 CLK_CORE_DIV_SHIFT = 0, 155 156 /* CLKSEL_CON1 / CLKSEL_CON3 */ 157 PCLK_DBG_DIV_MASK = 0x1f, 158 PCLK_DBG_DIV_SHIFT = 0x8, 159 ATCLK_CORE_DIV_MASK = 0x1f, 160 ATCLK_CORE_DIV_SHIFT = 0, 161 162 /* CLKSEL_CON14 */ 163 PCLK_PERIHP_DIV_CON_SHIFT = 12, 164 PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT, 165 HCLK_PERIHP_DIV_CON_SHIFT = 8, 166 HCLK_PERIHP_DIV_CON_MASK = 3 << HCLK_PERIHP_DIV_CON_SHIFT, 167 ACLK_PERIHP_PLL_SEL_SHIFT = 7, 168 ACLK_PERIHP_PLL_SEL_MASK = 1 << ACLK_PERIHP_PLL_SEL_SHIFT, 169 ACLK_PERIHP_PLL_SEL_CPLL = 0, 170 ACLK_PERIHP_PLL_SEL_GPLL = 1, 171 ACLK_PERIHP_DIV_CON_SHIFT = 0, 172 ACLK_PERIHP_DIV_CON_MASK = 0x1f, 173 174 /* CLKSEL_CON21 */ 175 ACLK_EMMC_PLL_SEL_SHIFT = 7, 176 ACLK_EMMC_PLL_SEL_MASK = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT, 177 ACLK_EMMC_PLL_SEL_GPLL = 0x1, 178 ACLK_EMMC_DIV_CON_SHIFT = 0, 179 ACLK_EMMC_DIV_CON_MASK = 0x1f, 180 181 /* CLKSEL_CON22 */ 182 CLK_EMMC_PLL_SHIFT = 8, 183 CLK_EMMC_PLL_MASK = 0x7 << CLK_EMMC_PLL_SHIFT, 184 CLK_EMMC_PLL_SEL_GPLL = 0x1, 185 CLK_EMMC_PLL_SEL_24M = 0x5, 186 CLK_EMMC_DIV_CON_SHIFT = 0, 187 CLK_EMMC_DIV_CON_MASK = 0x7f << CLK_EMMC_DIV_CON_SHIFT, 188 189 /* CLKSEL_CON23 */ 190 PCLK_PERILP0_DIV_CON_SHIFT = 12, 191 PCLK_PERILP0_DIV_CON_MASK = 0x7 << PCLK_PERILP0_DIV_CON_SHIFT, 192 HCLK_PERILP0_DIV_CON_SHIFT = 8, 193 HCLK_PERILP0_DIV_CON_MASK = 3 << HCLK_PERILP0_DIV_CON_SHIFT, 194 ACLK_PERILP0_PLL_SEL_SHIFT = 7, 195 ACLK_PERILP0_PLL_SEL_MASK = 1 << ACLK_PERILP0_PLL_SEL_SHIFT, 196 ACLK_PERILP0_PLL_SEL_CPLL = 0, 197 ACLK_PERILP0_PLL_SEL_GPLL = 1, 198 ACLK_PERILP0_DIV_CON_SHIFT = 0, 199 ACLK_PERILP0_DIV_CON_MASK = 0x1f, 200 201 /* CRU_CLK_SEL24_CON */ 202 CRYPTO0_PLL_SEL_SHIFT = 6, 203 CRYPTO0_PLL_SEL_MASK = 3 << CRYPTO0_PLL_SEL_SHIFT, 204 CRYPTO_PLL_SEL_CPLL = 0, 205 CRYPTO_PLL_SEL_GPLL, 206 CRYPTO_PLL_SEL_PPLL = 0, 207 CRYPTO0_DIV_SHIFT = 0, 208 CRYPTO0_DIV_MASK = 0x1f << CRYPTO0_DIV_SHIFT, 209 210 /* CLKSEL_CON25 */ 211 PCLK_PERILP1_DIV_CON_SHIFT = 8, 212 PCLK_PERILP1_DIV_CON_MASK = 0x7 << PCLK_PERILP1_DIV_CON_SHIFT, 213 HCLK_PERILP1_PLL_SEL_SHIFT = 7, 214 HCLK_PERILP1_PLL_SEL_MASK = 1 << HCLK_PERILP1_PLL_SEL_SHIFT, 215 HCLK_PERILP1_PLL_SEL_CPLL = 0, 216 HCLK_PERILP1_PLL_SEL_GPLL = 1, 217 HCLK_PERILP1_DIV_CON_SHIFT = 0, 218 HCLK_PERILP1_DIV_CON_MASK = 0x1f, 219 220 /* CLKSEL_CON26 */ 221 CLK_SARADC_DIV_CON_SHIFT = 8, 222 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8), 223 CLK_SARADC_DIV_CON_WIDTH = 8, 224 CRYPTO1_PLL_SEL_SHIFT = 6, 225 CRYPTO1_PLL_SEL_MASK = 3 << CRYPTO1_PLL_SEL_SHIFT, 226 CRYPTO1_DIV_SHIFT = 0, 227 CRYPTO1_DIV_MASK = 0x1f << CRYPTO1_DIV_SHIFT, 228 229 /* CLKSEL_CON27 */ 230 CLK_TSADC_SEL_X24M = 0x0, 231 CLK_TSADC_SEL_SHIFT = 15, 232 CLK_TSADC_SEL_MASK = 1 << CLK_TSADC_SEL_SHIFT, 233 CLK_TSADC_DIV_CON_SHIFT = 0, 234 CLK_TSADC_DIV_CON_MASK = 0x3ff, 235 236 /* CLKSEL_CON47 & CLKSEL_CON48 */ 237 ACLK_VOP_PLL_SEL_SHIFT = 6, 238 ACLK_VOP_PLL_SEL_MASK = 0x3 << ACLK_VOP_PLL_SEL_SHIFT, 239 ACLK_VOP_PLL_SEL_CPLL = 0x1, 240 ACLK_VOP_PLL_SEL_GPLL = 0x2, 241 ACLK_VOP_DIV_CON_SHIFT = 0, 242 ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT, 243 244 /* CLKSEL_CON49 & CLKSEL_CON50 */ 245 DCLK_VOP_DCLK_SEL_SHIFT = 11, 246 DCLK_VOP_DCLK_SEL_MASK = 1 << DCLK_VOP_DCLK_SEL_SHIFT, 247 DCLK_VOP_DCLK_SEL_DIVOUT = 0, 248 DCLK_VOP_PLL_SEL_SHIFT = 8, 249 DCLK_VOP_PLL_SEL_MASK = 3 << DCLK_VOP_PLL_SEL_SHIFT, 250 DCLK_VOP_PLL_SEL_VPLL = 0, 251 DCLK_VOP_PLL_SEL_CPLL = 1, 252 DCLK_VOP_DIV_CON_MASK = 0xff, 253 DCLK_VOP_DIV_CON_SHIFT = 0, 254 255 /* CLKSEL_CON57 */ 256 PCLK_ALIVE_DIV_CON_SHIFT = 0, 257 PCLK_ALIVE_DIV_CON_MASK = 0x1f << PCLK_ALIVE_DIV_CON_SHIFT, 258 259 /* CLKSEL_CON58 */ 260 CLK_SPI_PLL_SEL_WIDTH = 1, 261 CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1), 262 CLK_SPI_PLL_SEL_CPLL = 0, 263 CLK_SPI_PLL_SEL_GPLL = 1, 264 CLK_SPI_PLL_DIV_CON_WIDTH = 7, 265 CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1), 266 267 CLK_SPI5_PLL_DIV_CON_SHIFT = 8, 268 CLK_SPI5_PLL_SEL_SHIFT = 15, 269 270 /* CLKSEL_CON59 */ 271 CLK_SPI1_PLL_SEL_SHIFT = 15, 272 CLK_SPI1_PLL_DIV_CON_SHIFT = 8, 273 CLK_SPI0_PLL_SEL_SHIFT = 7, 274 CLK_SPI0_PLL_DIV_CON_SHIFT = 0, 275 276 /* CLKSEL_CON60 */ 277 CLK_SPI4_PLL_SEL_SHIFT = 15, 278 CLK_SPI4_PLL_DIV_CON_SHIFT = 8, 279 CLK_SPI2_PLL_SEL_SHIFT = 7, 280 CLK_SPI2_PLL_DIV_CON_SHIFT = 0, 281 282 /* CLKSEL_CON61 */ 283 CLK_I2C_PLL_SEL_MASK = 1, 284 CLK_I2C_PLL_SEL_CPLL = 0, 285 CLK_I2C_PLL_SEL_GPLL = 1, 286 CLK_I2C5_PLL_SEL_SHIFT = 15, 287 CLK_I2C5_DIV_CON_SHIFT = 8, 288 CLK_I2C1_PLL_SEL_SHIFT = 7, 289 CLK_I2C1_DIV_CON_SHIFT = 0, 290 291 /* CLKSEL_CON62 */ 292 CLK_I2C6_PLL_SEL_SHIFT = 15, 293 CLK_I2C6_DIV_CON_SHIFT = 8, 294 CLK_I2C2_PLL_SEL_SHIFT = 7, 295 CLK_I2C2_DIV_CON_SHIFT = 0, 296 297 /* CLKSEL_CON63 */ 298 CLK_I2C7_PLL_SEL_SHIFT = 15, 299 CLK_I2C7_DIV_CON_SHIFT = 8, 300 CLK_I2C3_PLL_SEL_SHIFT = 7, 301 CLK_I2C3_DIV_CON_SHIFT = 0, 302 303 /* CRU_SOFTRST_CON4 */ 304 RESETN_DDR0_REQ_SHIFT = 8, 305 RESETN_DDR0_REQ_MASK = 1 << RESETN_DDR0_REQ_SHIFT, 306 RESETN_DDRPHY0_REQ_SHIFT = 9, 307 RESETN_DDRPHY0_REQ_MASK = 1 << RESETN_DDRPHY0_REQ_SHIFT, 308 RESETN_DDR1_REQ_SHIFT = 12, 309 RESETN_DDR1_REQ_MASK = 1 << RESETN_DDR1_REQ_SHIFT, 310 RESETN_DDRPHY1_REQ_SHIFT = 13, 311 RESETN_DDRPHY1_REQ_MASK = 1 << RESETN_DDRPHY1_REQ_SHIFT, 312 }; 313 314 #define VCO_MAX_KHZ (3200 * (MHz / KHz)) 315 #define VCO_MIN_KHZ (800 * (MHz / KHz)) 316 #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz)) 317 #define OUTPUT_MIN_KHZ (16 * (MHz / KHz)) 318 319 /* 320 * the div restructions of pll in integer mode, these are defined in 321 * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0 322 */ 323 #define PLL_DIV_MIN 16 324 #define PLL_DIV_MAX 3200 325 326 /* 327 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63): 328 * Formulas also embedded within the Fractional PLL Verilog model: 329 * If DSMPD = 1 (DSM is disabled, "integer mode") 330 * FOUTVCO = FREF / REFDIV * FBDIV 331 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 332 * Where: 333 * FOUTVCO = Fractional PLL non-divided output frequency 334 * FOUTPOSTDIV = Fractional PLL divided output frequency 335 * (output of second post divider) 336 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input) 337 * REFDIV = Fractional PLL input reference clock divider 338 * FBDIV = Integer value programmed into feedback divide 339 * 340 */ 341 342 static uint32_t rkclk_pll_get_rate(u32 *pll_con) 343 { 344 u32 refdiv, fbdiv, postdiv1, postdiv2; 345 u32 con; 346 347 con = readl(&pll_con[3]); 348 switch ((con & PLL_MODE_MASK) >> PLL_MODE_SHIFT) { 349 case PLL_MODE_SLOW: 350 return OSC_HZ; 351 case PLL_MODE_NORM: 352 /* normal mode */ 353 con = readl(&pll_con[0]); 354 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; 355 con = readl(&pll_con[1]); 356 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; 357 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; 358 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; 359 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; 360 case PLL_MODE_DEEP: 361 default: 362 return 32768; 363 } 364 } 365 366 static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div) 367 { 368 /* All 8 PLLs have same VCO and output frequency range restrictions. */ 369 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; 370 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; 371 372 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, " 373 "postdiv2=%d, vco=%u khz, output=%u khz\n", 374 pll_con, div->fbdiv, div->refdiv, div->postdiv1, 375 div->postdiv2, vco_khz, output_khz); 376 assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ && 377 output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ && 378 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); 379 380 /* 381 * When power on or changing PLL setting, 382 * we must force PLL into slow mode to ensure output stable clock. 383 */ 384 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, 385 PLL_MODE_SLOW << PLL_MODE_SHIFT); 386 387 /* use integer mode */ 388 rk_clrsetreg(&pll_con[3], PLL_DSMPD_MASK, 389 PLL_INTEGER_MODE << PLL_DSMPD_SHIFT); 390 391 rk_clrsetreg(&pll_con[0], PLL_FBDIV_MASK, 392 div->fbdiv << PLL_FBDIV_SHIFT); 393 rk_clrsetreg(&pll_con[1], 394 PLL_POSTDIV2_MASK | PLL_POSTDIV1_MASK | 395 PLL_REFDIV_MASK | PLL_REFDIV_SHIFT, 396 (div->postdiv2 << PLL_POSTDIV2_SHIFT) | 397 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | 398 (div->refdiv << PLL_REFDIV_SHIFT)); 399 400 /* waiting for pll lock */ 401 while (!(readl(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT))) 402 udelay(1); 403 404 /* pll enter normal mode */ 405 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, 406 PLL_MODE_NORM << PLL_MODE_SHIFT); 407 } 408 409 static ulong rk3399_pll_get_rate(struct rk3399_clk_priv *priv, 410 enum rk3399_pll_id pll_id) 411 { 412 struct rk3399_cru *cru = priv->cru; 413 u32 *pll_con; 414 415 switch (pll_id) { 416 case PLL_APLLL: 417 pll_con = &cru->apll_l_con[0]; 418 break; 419 case PLL_APLLB: 420 pll_con = &cru->apll_b_con[0]; 421 break; 422 case PLL_DPLL: 423 pll_con = &cru->dpll_con[0]; 424 break; 425 case PLL_CPLL: 426 pll_con = &cru->cpll_con[0]; 427 break; 428 case PLL_GPLL: 429 pll_con = &cru->gpll_con[0]; 430 break; 431 case PLL_NPLL: 432 pll_con = &cru->npll_con[0]; 433 break; 434 case PLL_VPLL: 435 pll_con = &cru->vpll_con[0]; 436 break; 437 default: 438 pll_con = &cru->vpll_con[0]; 439 break; 440 } 441 442 return rkclk_pll_get_rate(pll_con); 443 } 444 445 static int pll_para_config(u32 freq_hz, struct pll_div *div) 446 { 447 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; 448 u32 postdiv1, postdiv2 = 1; 449 u32 fref_khz; 450 u32 diff_khz, best_diff_khz; 451 const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16; 452 const u32 max_postdiv1 = 7, max_postdiv2 = 7; 453 u32 vco_khz; 454 u32 freq_khz = freq_hz / KHz; 455 456 if (!freq_hz) { 457 printf("%s: the frequency can't be 0 Hz\n", __func__); 458 return -1; 459 } 460 461 postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz); 462 if (postdiv1 > max_postdiv1) { 463 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); 464 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); 465 } 466 467 vco_khz = freq_khz * postdiv1 * postdiv2; 468 469 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || 470 postdiv2 > max_postdiv2) { 471 printf("%s: Cannot find out a supported VCO" 472 " for Frequency (%uHz).\n", __func__, freq_hz); 473 return -1; 474 } 475 476 div->postdiv1 = postdiv1; 477 div->postdiv2 = postdiv2; 478 479 best_diff_khz = vco_khz; 480 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { 481 fref_khz = ref_khz / refdiv; 482 483 fbdiv = vco_khz / fref_khz; 484 if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv)) 485 continue; 486 diff_khz = vco_khz - fbdiv * fref_khz; 487 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) { 488 fbdiv++; 489 diff_khz = fref_khz - diff_khz; 490 } 491 492 if (diff_khz >= best_diff_khz) 493 continue; 494 495 best_diff_khz = diff_khz; 496 div->refdiv = refdiv; 497 div->fbdiv = fbdiv; 498 } 499 500 if (best_diff_khz > 4 * (MHz/KHz)) { 501 printf("%s: Failed to match output frequency %u, " 502 "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz, 503 best_diff_khz * KHz); 504 return -1; 505 } 506 return 0; 507 } 508 509 void rk3399_configure_cpu(struct rk3399_cru *cru, 510 enum apll_frequencies freq, 511 enum cpu_cluster cluster) 512 { 513 u32 aclkm_div; 514 u32 pclk_dbg_div; 515 u32 atclk_div, apll_hz; 516 int con_base, parent; 517 u32 *pll_con; 518 519 switch (cluster) { 520 case CPU_CLUSTER_LITTLE: 521 con_base = 0; 522 parent = CLK_CORE_PLL_SEL_ALPLL; 523 pll_con = &cru->apll_l_con[0]; 524 break; 525 case CPU_CLUSTER_BIG: 526 default: 527 con_base = 2; 528 parent = CLK_CORE_PLL_SEL_ABPLL; 529 pll_con = &cru->apll_b_con[0]; 530 break; 531 } 532 533 apll_hz = apll_cfgs[freq]->freq; 534 rkclk_set_pll(pll_con, apll_cfgs[freq]); 535 536 aclkm_div = apll_hz / ACLKM_CORE_HZ - 1; 537 assert((aclkm_div + 1) * ACLKM_CORE_HZ <= apll_hz && 538 aclkm_div < 0x1f); 539 540 pclk_dbg_div = apll_hz / PCLK_DBG_HZ - 1; 541 assert((pclk_dbg_div + 1) * PCLK_DBG_HZ <= apll_hz && 542 pclk_dbg_div < 0x1f); 543 544 atclk_div = apll_hz / ATCLK_CORE_HZ - 1; 545 assert((atclk_div + 1) * ATCLK_CORE_HZ <= apll_hz && 546 atclk_div < 0x1f); 547 548 rk_clrsetreg(&cru->clksel_con[con_base], 549 ACLKM_CORE_DIV_CON_MASK | CLK_CORE_PLL_SEL_MASK | 550 CLK_CORE_DIV_MASK, 551 aclkm_div << ACLKM_CORE_DIV_CON_SHIFT | 552 parent << CLK_CORE_PLL_SEL_SHIFT | 553 0 << CLK_CORE_DIV_SHIFT); 554 555 rk_clrsetreg(&cru->clksel_con[con_base + 1], 556 PCLK_DBG_DIV_MASK | ATCLK_CORE_DIV_MASK, 557 pclk_dbg_div << PCLK_DBG_DIV_SHIFT | 558 atclk_div << ATCLK_CORE_DIV_SHIFT); 559 } 560 #define I2C_CLK_REG_MASK(bus) \ 561 (I2C_DIV_CON_MASK << \ 562 CLK_I2C ##bus## _DIV_CON_SHIFT | \ 563 CLK_I2C_PLL_SEL_MASK << \ 564 CLK_I2C ##bus## _PLL_SEL_SHIFT) 565 566 #define I2C_CLK_REG_VALUE(bus, clk_div) \ 567 ((clk_div - 1) << \ 568 CLK_I2C ##bus## _DIV_CON_SHIFT | \ 569 CLK_I2C_PLL_SEL_GPLL << \ 570 CLK_I2C ##bus## _PLL_SEL_SHIFT) 571 572 #define I2C_CLK_DIV_VALUE(con, bus) \ 573 (con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \ 574 I2C_DIV_CON_MASK; 575 576 #define I2C_PMUCLK_REG_MASK(bus) \ 577 (I2C_DIV_CON_MASK << \ 578 CLK_I2C ##bus## _DIV_CON_SHIFT) 579 580 #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \ 581 ((clk_div - 1) << \ 582 CLK_I2C ##bus## _DIV_CON_SHIFT) 583 584 static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id) 585 { 586 u32 div, con; 587 588 switch (clk_id) { 589 case SCLK_I2C1: 590 con = readl(&cru->clksel_con[61]); 591 div = I2C_CLK_DIV_VALUE(con, 1); 592 break; 593 case SCLK_I2C2: 594 con = readl(&cru->clksel_con[62]); 595 div = I2C_CLK_DIV_VALUE(con, 2); 596 break; 597 case SCLK_I2C3: 598 con = readl(&cru->clksel_con[63]); 599 div = I2C_CLK_DIV_VALUE(con, 3); 600 break; 601 case SCLK_I2C5: 602 con = readl(&cru->clksel_con[61]); 603 div = I2C_CLK_DIV_VALUE(con, 5); 604 break; 605 case SCLK_I2C6: 606 con = readl(&cru->clksel_con[62]); 607 div = I2C_CLK_DIV_VALUE(con, 6); 608 break; 609 case SCLK_I2C7: 610 con = readl(&cru->clksel_con[63]); 611 div = I2C_CLK_DIV_VALUE(con, 7); 612 break; 613 default: 614 printf("do not support this i2c bus\n"); 615 return -EINVAL; 616 } 617 618 return DIV_TO_RATE(GPLL_HZ, div); 619 } 620 621 static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) 622 { 623 int src_clk_div; 624 625 /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/ 626 src_clk_div = GPLL_HZ / hz; 627 assert(src_clk_div - 1 <= 127); 628 629 switch (clk_id) { 630 case SCLK_I2C1: 631 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(1), 632 I2C_CLK_REG_VALUE(1, src_clk_div)); 633 break; 634 case SCLK_I2C2: 635 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(2), 636 I2C_CLK_REG_VALUE(2, src_clk_div)); 637 break; 638 case SCLK_I2C3: 639 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(3), 640 I2C_CLK_REG_VALUE(3, src_clk_div)); 641 break; 642 case SCLK_I2C5: 643 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(5), 644 I2C_CLK_REG_VALUE(5, src_clk_div)); 645 break; 646 case SCLK_I2C6: 647 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(6), 648 I2C_CLK_REG_VALUE(6, src_clk_div)); 649 break; 650 case SCLK_I2C7: 651 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(7), 652 I2C_CLK_REG_VALUE(7, src_clk_div)); 653 break; 654 default: 655 printf("do not support this i2c bus\n"); 656 return -EINVAL; 657 } 658 659 return rk3399_i2c_get_clk(cru, clk_id); 660 } 661 662 /* 663 * RK3399 SPI clocks have a common divider-width (7 bits) and a single bit 664 * to select either CPLL or GPLL as the clock-parent. The location within 665 * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable. 666 */ 667 668 struct spi_clkreg { 669 uint8_t reg; /* CLKSEL_CON[reg] register in CRU */ 670 uint8_t div_shift; 671 uint8_t sel_shift; 672 }; 673 674 /* 675 * The entries are numbered relative to their offset from SCLK_SPI0. 676 * 677 * Note that SCLK_SPI3 (which is configured via PMUCRU and requires different 678 * logic is not supported). 679 */ 680 static const struct spi_clkreg spi_clkregs[] = { 681 [0] = { .reg = 59, 682 .div_shift = CLK_SPI0_PLL_DIV_CON_SHIFT, 683 .sel_shift = CLK_SPI0_PLL_SEL_SHIFT, }, 684 [1] = { .reg = 59, 685 .div_shift = CLK_SPI1_PLL_DIV_CON_SHIFT, 686 .sel_shift = CLK_SPI1_PLL_SEL_SHIFT, }, 687 [2] = { .reg = 60, 688 .div_shift = CLK_SPI2_PLL_DIV_CON_SHIFT, 689 .sel_shift = CLK_SPI2_PLL_SEL_SHIFT, }, 690 [3] = { .reg = 60, 691 .div_shift = CLK_SPI4_PLL_DIV_CON_SHIFT, 692 .sel_shift = CLK_SPI4_PLL_SEL_SHIFT, }, 693 [4] = { .reg = 58, 694 .div_shift = CLK_SPI5_PLL_DIV_CON_SHIFT, 695 .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, }, 696 }; 697 698 static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id) 699 { 700 const struct spi_clkreg *spiclk = NULL; 701 u32 div, val; 702 703 switch (clk_id) { 704 case SCLK_SPI0 ... SCLK_SPI5: 705 spiclk = &spi_clkregs[clk_id - SCLK_SPI0]; 706 break; 707 708 default: 709 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id); 710 return -EINVAL; 711 } 712 713 val = readl(&cru->clksel_con[spiclk->reg]); 714 div = bitfield_extract(val, spiclk->div_shift, 715 CLK_SPI_PLL_DIV_CON_WIDTH); 716 717 return DIV_TO_RATE(GPLL_HZ, div); 718 } 719 720 static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) 721 { 722 const struct spi_clkreg *spiclk = NULL; 723 int src_clk_div; 724 725 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; 726 assert(src_clk_div < 128); 727 728 switch (clk_id) { 729 case SCLK_SPI1 ... SCLK_SPI5: 730 spiclk = &spi_clkregs[clk_id - SCLK_SPI0]; 731 break; 732 733 default: 734 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id); 735 return -EINVAL; 736 } 737 738 rk_clrsetreg(&cru->clksel_con[spiclk->reg], 739 ((CLK_SPI_PLL_DIV_CON_MASK << spiclk->div_shift) | 740 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)), 741 ((src_clk_div << spiclk->div_shift) | 742 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift))); 743 744 return rk3399_spi_get_clk(cru, clk_id); 745 } 746 747 #define RK3399_LIMIT_PLL_ACLK_VOP (400 * 1000000) 748 749 static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz) 750 { 751 struct pll_div vpll_config = {0}, cpll_config = {0}; 752 int aclk_vop = RK3399_LIMIT_PLL_ACLK_VOP; 753 void *aclkreg_addr, *dclkreg_addr; 754 u32 div = 1; 755 756 switch (clk_id) { 757 case DCLK_VOP0: 758 aclkreg_addr = &cru->clksel_con[47]; 759 dclkreg_addr = &cru->clksel_con[49]; 760 break; 761 case DCLK_VOP1: 762 aclkreg_addr = &cru->clksel_con[48]; 763 dclkreg_addr = &cru->clksel_con[50]; 764 break; 765 default: 766 return -EINVAL; 767 } 768 /* vop aclk source clk: cpll */ 769 div = GPLL_HZ / aclk_vop; 770 assert(div - 1 <= 31); 771 772 rk_clrsetreg(aclkreg_addr, 773 ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK, 774 ACLK_VOP_PLL_SEL_GPLL << ACLK_VOP_PLL_SEL_SHIFT | 775 (div - 1) << ACLK_VOP_DIV_CON_SHIFT); 776 rk_clrsetreg(&cru->clksel_con[42], 777 ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK, 778 ACLK_VOP_PLL_SEL_GPLL << ACLK_VOP_PLL_SEL_SHIFT | 779 (div - 1) << ACLK_VOP_DIV_CON_SHIFT); 780 781 if (readl(dclkreg_addr) & DCLK_VOP_PLL_SEL_MASK) { 782 if (pll_para_config(hz, &cpll_config)) 783 return -1; 784 rkclk_set_pll(&cru->cpll_con[0], &cpll_config); 785 } else { 786 if (pll_para_config(hz, &vpll_config)) 787 return -1; 788 rkclk_set_pll(&cru->vpll_con[0], &vpll_config); 789 } 790 791 rk_clrsetreg(dclkreg_addr, 792 DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_DIV_CON_MASK, 793 DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT | 794 (1 - 1) << DCLK_VOP_DIV_CON_SHIFT); 795 796 return hz; 797 } 798 799 static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id) 800 { 801 u32 div, con; 802 803 switch (clk_id) { 804 case HCLK_SDMMC: 805 case SCLK_SDMMC: 806 con = readl(&cru->clksel_con[16]); 807 /* dwmmc controller have internal div 2 */ 808 div = 2; 809 break; 810 case SCLK_EMMC: 811 con = readl(&cru->clksel_con[22]); 812 div = 1; 813 break; 814 default: 815 return -EINVAL; 816 } 817 818 div *= (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT; 819 if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT 820 == CLK_EMMC_PLL_SEL_24M) 821 return DIV_TO_RATE(OSC_HZ, div); 822 else 823 return DIV_TO_RATE(GPLL_HZ, div); 824 } 825 826 static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru, 827 ulong clk_id, ulong set_rate) 828 { 829 int src_clk_div; 830 int aclk_emmc = 198*MHz; 831 832 switch (clk_id) { 833 case HCLK_SDMMC: 834 case SCLK_SDMMC: 835 /* Select clk_sdmmc source from GPLL by default */ 836 /* mmc clock defaulg div 2 internal, provide double in cru */ 837 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate); 838 839 if (src_clk_div > 128) { 840 /* use 24MHz source for 400KHz clock */ 841 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); 842 assert(src_clk_div - 1 < 128); 843 rk_clrsetreg(&cru->clksel_con[16], 844 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 845 CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT | 846 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 847 } else { 848 rk_clrsetreg(&cru->clksel_con[16], 849 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 850 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | 851 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 852 } 853 break; 854 case SCLK_EMMC: 855 /* Select aclk_emmc source from GPLL */ 856 src_clk_div = DIV_ROUND_UP(GPLL_HZ , aclk_emmc); 857 assert(src_clk_div - 1 < 32); 858 859 rk_clrsetreg(&cru->clksel_con[21], 860 ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK, 861 ACLK_EMMC_PLL_SEL_GPLL << ACLK_EMMC_PLL_SEL_SHIFT | 862 (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT); 863 864 /* Select clk_emmc source from GPLL too */ 865 src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate); 866 if (src_clk_div > 128) { 867 /* use 24MHz source for 400KHz clock */ 868 src_clk_div = DIV_ROUND_UP(OSC_HZ, set_rate); 869 assert(src_clk_div - 1 < 128); 870 rk_clrsetreg(&cru->clksel_con[22], 871 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 872 CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT | 873 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 874 } else { 875 rk_clrsetreg(&cru->clksel_con[22], 876 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 877 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | 878 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 879 } 880 break; 881 default: 882 return -EINVAL; 883 } 884 return rk3399_mmc_get_clk(cru, clk_id); 885 } 886 887 static ulong rk3399_gmac_set_clk(struct rk3399_cru *cru, ulong rate) 888 { 889 ulong ret; 890 891 /* 892 * The RGMII CLK can be derived either from an external "clkin" 893 * or can be generated from internally by a divider from SCLK_MAC. 894 */ 895 if (readl(&cru->clksel_con[19]) & BIT(4)) { 896 /* An external clock will always generate the right rate... */ 897 ret = rate; 898 } else { 899 /* 900 * No platform uses an internal clock to date. 901 * Implement this once it becomes necessary and print an error 902 * if someone tries to use it (while it remains unimplemented). 903 */ 904 pr_err("%s: internal clock is UNIMPLEMENTED\n", __func__); 905 ret = 0; 906 } 907 908 return ret; 909 } 910 911 #define PMUSGRF_DDR_RGN_CON16 0xff330040 912 static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru, 913 ulong set_rate) 914 { 915 struct pll_div dpll_cfg; 916 917 /* IC ECO bug, need to set this register */ 918 writel(0xc000c000, PMUSGRF_DDR_RGN_CON16); 919 920 /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */ 921 switch (set_rate) { 922 case 50 * MHz: 923 dpll_cfg = (struct pll_div) 924 {.refdiv = 1, .fbdiv = 12, .postdiv1 = 3, .postdiv2 = 2}; 925 break; 926 case 200 * MHz: 927 dpll_cfg = (struct pll_div) 928 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1}; 929 break; 930 case 300 * MHz: 931 dpll_cfg = (struct pll_div) 932 {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1}; 933 break; 934 case 400 * MHz: 935 dpll_cfg = (struct pll_div) 936 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1}; 937 break; 938 case 666 * MHz: 939 dpll_cfg = (struct pll_div) 940 {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1}; 941 break; 942 case 800 * MHz: 943 dpll_cfg = (struct pll_div) 944 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}; 945 break; 946 case 933 * MHz: 947 dpll_cfg = (struct pll_div) 948 {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1}; 949 break; 950 default: 951 pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate); 952 } 953 rkclk_set_pll(&cru->dpll_con[0], &dpll_cfg); 954 955 return set_rate; 956 } 957 958 static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru) 959 { 960 u32 div, val; 961 962 val = readl(&cru->clksel_con[26]); 963 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT, 964 CLK_SARADC_DIV_CON_WIDTH); 965 966 return DIV_TO_RATE(OSC_HZ, div); 967 } 968 969 static ulong rk3399_saradc_set_clk(struct rk3399_cru *cru, uint hz) 970 { 971 int src_clk_div; 972 973 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; 974 assert(src_clk_div <= 255); 975 976 rk_clrsetreg(&cru->clksel_con[26], 977 CLK_SARADC_DIV_CON_MASK, 978 src_clk_div << CLK_SARADC_DIV_CON_SHIFT); 979 980 return rk3399_saradc_get_clk(cru); 981 } 982 983 static ulong rk3399_tsadc_get_clk(struct rk3399_cru *cru) 984 { 985 u32 div, val; 986 987 val = readl(&cru->clksel_con[27]); 988 div = bitfield_extract(val, CLK_TSADC_SEL_SHIFT, 989 10); 990 991 return DIV_TO_RATE(OSC_HZ, div); 992 } 993 994 static ulong rk3399_tsadc_set_clk(struct rk3399_cru *cru, uint hz) 995 { 996 int src_clk_div; 997 998 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; 999 assert(src_clk_div <= 255); 1000 1001 rk_clrsetreg(&cru->clksel_con[27], 1002 CLK_TSADC_DIV_CON_MASK | CLK_TSADC_SEL_MASK, 1003 (CLK_TSADC_SEL_X24M << CLK_TSADC_SEL_SHIFT) | 1004 (src_clk_div << CLK_TSADC_DIV_CON_SHIFT)); 1005 1006 return rk3399_tsadc_get_clk(cru); 1007 } 1008 1009 static ulong rk3399_crypto_get_clk(struct rk3399_clk_priv *priv, ulong clk_id) 1010 { 1011 struct rk3399_cru *cru = priv->cru; 1012 u32 div, con, parent; 1013 1014 switch (clk_id) { 1015 case SCLK_CRYPTO0: 1016 con = readl(&cru->clksel_con[24]); 1017 div = (con & CRYPTO0_DIV_MASK) >> CRYPTO0_DIV_SHIFT; 1018 parent = GPLL_HZ; 1019 break; 1020 case SCLK_CRYPTO1: 1021 con = readl(&cru->clksel_con[26]); 1022 div = (con & CRYPTO1_DIV_MASK) >> CRYPTO1_DIV_SHIFT; 1023 parent = GPLL_HZ; 1024 break; 1025 default: 1026 return -ENOENT; 1027 } 1028 1029 return DIV_TO_RATE(parent, div); 1030 } 1031 1032 static ulong rk3399_crypto_set_clk(struct rk3399_clk_priv *priv, ulong clk_id, 1033 ulong hz) 1034 { 1035 struct rk3399_cru *cru = priv->cru; 1036 int src_clk_div; 1037 1038 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz); 1039 assert(src_clk_div - 1 <= 31); 1040 1041 /* 1042 * select gpll as crypto clock source and 1043 * set up dependent divisors for crypto clocks. 1044 */ 1045 switch (clk_id) { 1046 case SCLK_CRYPTO0: 1047 rk_clrsetreg(&cru->clksel_con[24], 1048 CRYPTO0_PLL_SEL_MASK | CRYPTO0_DIV_MASK, 1049 CRYPTO_PLL_SEL_GPLL << CRYPTO0_PLL_SEL_SHIFT | 1050 (src_clk_div - 1) << CRYPTO0_DIV_SHIFT); 1051 break; 1052 case SCLK_CRYPTO1: 1053 rk_clrsetreg(&cru->clksel_con[26], 1054 CRYPTO1_PLL_SEL_MASK | CRYPTO1_DIV_MASK, 1055 CRYPTO_PLL_SEL_GPLL << CRYPTO1_PLL_SEL_SHIFT | 1056 (src_clk_div - 1) << CRYPTO1_DIV_SHIFT); 1057 break; 1058 default: 1059 printf("do not support this peri freq\n"); 1060 return -EINVAL; 1061 } 1062 1063 return rk3399_crypto_get_clk(priv, clk_id); 1064 } 1065 1066 #ifndef CONFIG_SPL_BUILD 1067 static ulong rk3399_peri_get_clk(struct rk3399_clk_priv *priv, ulong clk_id) 1068 { 1069 struct rk3399_cru *cru = priv->cru; 1070 u32 div, con, parent; 1071 1072 switch (clk_id) { 1073 case ACLK_PERIHP: 1074 con = readl(&cru->clksel_con[14]); 1075 div = (con & ACLK_PERIHP_DIV_CON_MASK) >> 1076 ACLK_PERIHP_DIV_CON_SHIFT; 1077 parent = GPLL_HZ; 1078 break; 1079 case PCLK_PERIHP: 1080 con = readl(&cru->clksel_con[14]); 1081 div = (con & PCLK_PERIHP_DIV_CON_MASK) >> 1082 PCLK_PERIHP_DIV_CON_SHIFT; 1083 parent = rk3399_peri_get_clk(priv, ACLK_PERIHP); 1084 break; 1085 case HCLK_PERIHP: 1086 con = readl(&cru->clksel_con[14]); 1087 div = (con & HCLK_PERIHP_DIV_CON_MASK) >> 1088 HCLK_PERIHP_DIV_CON_SHIFT; 1089 parent = rk3399_peri_get_clk(priv, ACLK_PERIHP); 1090 break; 1091 case ACLK_PERILP0: 1092 con = readl(&cru->clksel_con[23]); 1093 div = (con & ACLK_PERILP0_DIV_CON_MASK) >> 1094 ACLK_PERILP0_DIV_CON_SHIFT; 1095 parent = GPLL_HZ; 1096 break; 1097 case HCLK_PERILP0: 1098 con = readl(&cru->clksel_con[23]); 1099 div = (con & HCLK_PERILP0_DIV_CON_MASK) >> 1100 HCLK_PERILP0_DIV_CON_SHIFT; 1101 parent = rk3399_peri_get_clk(priv, ACLK_PERILP0); 1102 break; 1103 case PCLK_PERILP0: 1104 con = readl(&cru->clksel_con[23]); 1105 div = (con & PCLK_PERILP0_DIV_CON_MASK) >> 1106 PCLK_PERILP0_DIV_CON_SHIFT; 1107 parent = rk3399_peri_get_clk(priv, ACLK_PERILP0); 1108 break; 1109 case HCLK_PERILP1: 1110 con = readl(&cru->clksel_con[25]); 1111 div = (con & HCLK_PERILP1_DIV_CON_MASK) >> 1112 HCLK_PERILP1_DIV_CON_SHIFT; 1113 parent = GPLL_HZ; 1114 break; 1115 case PCLK_PERILP1: 1116 con = readl(&cru->clksel_con[25]); 1117 div = (con & PCLK_PERILP1_DIV_CON_MASK) >> 1118 PCLK_PERILP1_DIV_CON_SHIFT; 1119 parent = rk3399_peri_get_clk(priv, HCLK_PERILP1); 1120 break; 1121 default: 1122 return -ENOENT; 1123 } 1124 1125 return DIV_TO_RATE(parent, div); 1126 } 1127 1128 static ulong rk3399_alive_get_clk(struct rk3399_clk_priv *priv) 1129 { 1130 struct rk3399_cru *cru = priv->cru; 1131 u32 div, con, parent; 1132 1133 con = readl(&cru->clksel_con[57]); 1134 div = (con & PCLK_ALIVE_DIV_CON_MASK) >> 1135 PCLK_ALIVE_DIV_CON_SHIFT; 1136 parent = GPLL_HZ; 1137 return DIV_TO_RATE(parent, div); 1138 } 1139 #endif 1140 1141 static ulong rk3399_clk_get_rate(struct clk *clk) 1142 { 1143 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 1144 ulong rate = 0; 1145 1146 switch (clk->id) { 1147 case PLL_APLLL: 1148 case PLL_APLLB: 1149 case PLL_DPLL: 1150 case PLL_CPLL: 1151 case PLL_GPLL: 1152 case PLL_NPLL: 1153 case PLL_VPLL: 1154 rate = rk3399_pll_get_rate(priv, clk->id); 1155 break; 1156 case HCLK_SDMMC: 1157 case SCLK_SDMMC: 1158 case SCLK_EMMC: 1159 rate = rk3399_mmc_get_clk(priv->cru, clk->id); 1160 break; 1161 case SCLK_I2C1: 1162 case SCLK_I2C2: 1163 case SCLK_I2C3: 1164 case SCLK_I2C5: 1165 case SCLK_I2C6: 1166 case SCLK_I2C7: 1167 rate = rk3399_i2c_get_clk(priv->cru, clk->id); 1168 break; 1169 case SCLK_SPI0...SCLK_SPI5: 1170 rate = rk3399_spi_get_clk(priv->cru, clk->id); 1171 break; 1172 case SCLK_UART0: 1173 case SCLK_UART1: 1174 case SCLK_UART2: 1175 case SCLK_UART3: 1176 return 24000000; 1177 break; 1178 case PCLK_HDMI_CTRL: 1179 break; 1180 case DCLK_VOP0: 1181 case DCLK_VOP1: 1182 break; 1183 case PCLK_EFUSE1024NS: 1184 break; 1185 case SCLK_SARADC: 1186 rate = rk3399_saradc_get_clk(priv->cru); 1187 break; 1188 case SCLK_TSADC: 1189 rate = rk3399_tsadc_get_clk(priv->cru); 1190 break; 1191 case SCLK_CRYPTO0: 1192 case SCLK_CRYPTO1: 1193 rate = rk3399_crypto_get_clk(priv, clk->id); 1194 break; 1195 #ifndef CONFIG_SPL_BUILD 1196 case ACLK_PERIHP: 1197 case HCLK_PERIHP: 1198 case PCLK_PERIHP: 1199 case ACLK_PERILP0: 1200 case HCLK_PERILP0: 1201 case PCLK_PERILP0: 1202 case HCLK_PERILP1: 1203 case PCLK_PERILP1: 1204 rate = rk3399_peri_get_clk(priv, clk->id); 1205 break; 1206 case PCLK_ALIVE: 1207 case PCLK_WDT: 1208 rate = rk3399_alive_get_clk(priv); 1209 break; 1210 #endif 1211 default: 1212 return -ENOENT; 1213 } 1214 1215 return rate; 1216 } 1217 1218 static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) 1219 { 1220 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 1221 ulong ret = 0; 1222 1223 switch (clk->id) { 1224 case 0 ... 63: 1225 return 0; 1226 1227 case ACLK_PERIHP: 1228 case HCLK_PERIHP: 1229 case PCLK_PERIHP: 1230 return 0; 1231 1232 case ACLK_PERILP0: 1233 case HCLK_PERILP0: 1234 case PCLK_PERILP0: 1235 return 0; 1236 1237 case ACLK_CCI: 1238 return 0; 1239 1240 case HCLK_PERILP1: 1241 case PCLK_PERILP1: 1242 return 0; 1243 1244 case HCLK_SDMMC: 1245 case SCLK_SDMMC: 1246 case SCLK_EMMC: 1247 ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate); 1248 break; 1249 case SCLK_MAC: 1250 ret = rk3399_gmac_set_clk(priv->cru, rate); 1251 break; 1252 case SCLK_I2C1: 1253 case SCLK_I2C2: 1254 case SCLK_I2C3: 1255 case SCLK_I2C5: 1256 case SCLK_I2C6: 1257 case SCLK_I2C7: 1258 ret = rk3399_i2c_set_clk(priv->cru, clk->id, rate); 1259 break; 1260 case SCLK_SPI0...SCLK_SPI5: 1261 ret = rk3399_spi_set_clk(priv->cru, clk->id, rate); 1262 break; 1263 case PCLK_HDMI_CTRL: 1264 case PCLK_VIO_GRF: 1265 /* the PCLK gates for video are enabled by default */ 1266 break; 1267 case DCLK_VOP0: 1268 case DCLK_VOP1: 1269 ret = rk3399_vop_set_clk(priv->cru, clk->id, rate); 1270 break; 1271 case SCLK_DDRCLK: 1272 ret = rk3399_ddr_set_clk(priv->cru, rate); 1273 break; 1274 case PCLK_EFUSE1024NS: 1275 break; 1276 case SCLK_SARADC: 1277 ret = rk3399_saradc_set_clk(priv->cru, rate); 1278 break; 1279 case SCLK_TSADC: 1280 ret = rk3399_tsadc_set_clk(priv->cru, rate); 1281 break; 1282 case SCLK_CRYPTO0: 1283 case SCLK_CRYPTO1: 1284 ret = rk3399_crypto_set_clk(priv, clk->id, rate); 1285 break; 1286 default: 1287 return -ENOENT; 1288 } 1289 1290 return ret; 1291 } 1292 1293 static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk, struct clk *parent) 1294 { 1295 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 1296 const char *clock_output_name; 1297 int ret; 1298 1299 /* 1300 * If the requested parent is in the same clock-controller and 1301 * the id is SCLK_MAC ("clk_gmac"), switch to the internal clock. 1302 */ 1303 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC)) { 1304 debug("%s: switching RGMII to SCLK_MAC\n", __func__); 1305 rk_clrreg(&priv->cru->clksel_con[19], BIT(4)); 1306 return 0; 1307 } 1308 1309 /* 1310 * Otherwise, we need to check the clock-output-names of the 1311 * requested parent to see if the requested id is "clkin_gmac". 1312 */ 1313 ret = dev_read_string_index(parent->dev, "clock-output-names", 1314 parent->id, &clock_output_name); 1315 if (ret < 0) 1316 return -ENODATA; 1317 1318 /* If this is "clkin_gmac", switch to the external clock input */ 1319 if (!strcmp(clock_output_name, "clkin_gmac")) { 1320 debug("%s: switching RGMII to CLKIN\n", __func__); 1321 rk_setreg(&priv->cru->clksel_con[19], BIT(4)); 1322 return 0; 1323 } 1324 1325 return -EINVAL; 1326 } 1327 1328 static int __maybe_unused rk3399_dclk_vop_set_parent(struct clk *clk, 1329 struct clk *parent) 1330 { 1331 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 1332 void *dclkreg_addr; 1333 1334 switch (clk->id) { 1335 case DCLK_VOP0_DIV: 1336 dclkreg_addr = &priv->cru->clksel_con[49]; 1337 break; 1338 case DCLK_VOP1_DIV: 1339 dclkreg_addr = &priv->cru->clksel_con[50]; 1340 break; 1341 default: 1342 return -EINVAL; 1343 } 1344 if (parent->id == PLL_CPLL) { 1345 rk_clrsetreg(dclkreg_addr, DCLK_VOP_PLL_SEL_MASK, 1346 DCLK_VOP_PLL_SEL_CPLL << DCLK_VOP_PLL_SEL_SHIFT); 1347 } else { 1348 rk_clrsetreg(dclkreg_addr, DCLK_VOP_PLL_SEL_MASK, 1349 DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT); 1350 } 1351 1352 return 0; 1353 } 1354 1355 static int __maybe_unused rk3399_clk_set_parent(struct clk *clk, struct clk *parent) 1356 { 1357 switch (clk->id) { 1358 case SCLK_RMII_SRC: 1359 return rk3399_gmac_set_parent(clk, parent); 1360 case DCLK_VOP0_DIV: 1361 case DCLK_VOP1_DIV: 1362 return rk3399_dclk_vop_set_parent(clk, parent); 1363 } 1364 1365 debug("%s: unsupported clk %ld\n", __func__, clk->id); 1366 return -ENOENT; 1367 } 1368 1369 static int rk3399_clk_enable(struct clk *clk) 1370 { 1371 switch (clk->id) { 1372 case HCLK_HOST0: 1373 case HCLK_HOST0_ARB: 1374 case SCLK_USBPHY0_480M_SRC: 1375 case HCLK_HOST1: 1376 case HCLK_HOST1_ARB: 1377 case SCLK_USBPHY1_480M_SRC: 1378 case ACLK_USB3OTG1: 1379 case ACLK_USB3_GRF: 1380 case SCLK_USB3OTG1_REF: 1381 case SCLK_USB3OTG1_SUSPEND: 1382 return 0; 1383 } 1384 1385 debug("%s: unsupported clk %ld\n", __func__, clk->id); 1386 return -ENOENT; 1387 } 1388 1389 static struct clk_ops rk3399_clk_ops = { 1390 .get_rate = rk3399_clk_get_rate, 1391 .set_rate = rk3399_clk_set_rate, 1392 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 1393 .set_parent = rk3399_clk_set_parent, 1394 #endif 1395 .enable = rk3399_clk_enable, 1396 }; 1397 1398 static void rkclk_init(struct rk3399_cru *cru) 1399 { 1400 u32 aclk_div; 1401 u32 hclk_div; 1402 u32 pclk_div; 1403 1404 rk3399_configure_cpu(cru, APLL_816_MHZ, CPU_CLUSTER_LITTLE); 1405 rk3399_configure_cpu(cru, APLL_816_MHZ, CPU_CLUSTER_BIG); 1406 1407 /* 1408 * some cru registers changed by bootrom, we'd better reset them to 1409 * reset/default values described in TRM to avoid confusion in kernel. 1410 * Please consider these three lines as a fix of bootrom bug. 1411 */ 1412 if (rkclk_pll_get_rate(&cru->npll_con[0]) != NPLL_HZ) 1413 rkclk_set_pll(&cru->npll_con[0], &npll_init_cfg); 1414 1415 if (rkclk_pll_get_rate(&cru->gpll_con[0]) == GPLL_HZ) 1416 return; 1417 1418 rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101); 1419 rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f); 1420 rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003); 1421 1422 /* configure perihp aclk, hclk, pclk */ 1423 aclk_div = DIV_ROUND_UP(GPLL_HZ, PERIHP_ACLK_HZ) - 1; 1424 1425 hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1; 1426 assert((hclk_div + 1) * PERIHP_HCLK_HZ <= 1427 PERIHP_ACLK_HZ && (hclk_div <= 0x3)); 1428 1429 pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1; 1430 assert((pclk_div + 1) * PERIHP_PCLK_HZ <= 1431 PERIHP_ACLK_HZ && (pclk_div <= 0x7)); 1432 1433 rk_clrsetreg(&cru->clksel_con[14], 1434 PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK | 1435 ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK, 1436 pclk_div << PCLK_PERIHP_DIV_CON_SHIFT | 1437 hclk_div << HCLK_PERIHP_DIV_CON_SHIFT | 1438 ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT | 1439 aclk_div << ACLK_PERIHP_DIV_CON_SHIFT); 1440 1441 /* configure perilp0 aclk, hclk, pclk */ 1442 aclk_div = DIV_ROUND_UP(GPLL_HZ, PERILP0_ACLK_HZ) - 1; 1443 1444 hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1; 1445 assert((hclk_div + 1) * PERILP0_HCLK_HZ <= 1446 PERILP0_ACLK_HZ && (hclk_div <= 0x3)); 1447 1448 pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1; 1449 assert((pclk_div + 1) * PERILP0_PCLK_HZ <= 1450 PERILP0_ACLK_HZ && (pclk_div <= 0x7)); 1451 1452 rk_clrsetreg(&cru->clksel_con[23], 1453 PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK | 1454 ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK, 1455 pclk_div << PCLK_PERILP0_DIV_CON_SHIFT | 1456 hclk_div << HCLK_PERILP0_DIV_CON_SHIFT | 1457 ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT | 1458 aclk_div << ACLK_PERILP0_DIV_CON_SHIFT); 1459 1460 /* perilp1 hclk select gpll as source */ 1461 hclk_div = DIV_ROUND_UP(GPLL_HZ, PERILP1_HCLK_HZ) - 1; 1462 assert((hclk_div + 1) * PERILP1_HCLK_HZ <= 1463 GPLL_HZ && (hclk_div <= 0x1f)); 1464 1465 pclk_div = PERILP1_HCLK_HZ / PERILP1_PCLK_HZ - 1; 1466 assert((pclk_div + 1) * PERILP1_PCLK_HZ <= 1467 PERILP1_HCLK_HZ && (pclk_div <= 0x7)); 1468 1469 rk_clrsetreg(&cru->clksel_con[25], 1470 PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK | 1471 HCLK_PERILP1_PLL_SEL_MASK, 1472 pclk_div << PCLK_PERILP1_DIV_CON_SHIFT | 1473 hclk_div << HCLK_PERILP1_DIV_CON_SHIFT | 1474 HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT); 1475 1476 rk_clrsetreg(&cru->clksel_con[21], 1477 ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK, 1478 ACLK_EMMC_PLL_SEL_GPLL << ACLK_EMMC_PLL_SEL_SHIFT | 1479 (4 - 1) << ACLK_EMMC_DIV_CON_SHIFT); 1480 rk_clrsetreg(&cru->clksel_con[22], 0x3f << 0, 7 << 0); 1481 1482 /* 1483 * I2c MUx is in cpll by default, but cpll is for dclk_vop exclusive. 1484 * If dclk_vop set rate after i2c init, the CPLL changed, 1485 * but the i2c not perception, it will resulting the wrong 1486 * frequency of the i2c. 1487 * So set the i2c frequency according to the kernel configuration, 1488 * and Hang I2C on the GPLL. 1489 */ 1490 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(1), 1491 I2C_CLK_REG_VALUE(1, 4)); 1492 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(2), 1493 I2C_CLK_REG_VALUE(2, 4)); 1494 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(3), 1495 I2C_CLK_REG_VALUE(3, 4)); 1496 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(5), 1497 I2C_CLK_REG_VALUE(5, 4)); 1498 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(6), 1499 I2C_CLK_REG_VALUE(6, 4)); 1500 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(7), 1501 I2C_CLK_REG_VALUE(7, 4)); 1502 1503 rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg); 1504 } 1505 1506 static int rk3399_clk_probe(struct udevice *dev) 1507 { 1508 struct rk3399_clk_priv *priv = dev_get_priv(dev); 1509 1510 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1511 struct rk3399_clk_plat *plat = dev_get_platdata(dev); 1512 1513 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); 1514 #endif 1515 1516 priv->sync_kernel = false; 1517 if (!priv->armlclk_enter_hz) 1518 priv->armlclk_enter_hz = 1519 rkclk_pll_get_rate(&priv->cru->apll_l_con[0]); 1520 if (!priv->armbclk_enter_hz) 1521 priv->armbclk_enter_hz = 1522 rkclk_pll_get_rate(&priv->cru->apll_b_con[0]); 1523 rkclk_init(priv->cru); 1524 if (!priv->armlclk_init_hz) 1525 priv->armlclk_init_hz = 1526 rkclk_pll_get_rate(&priv->cru->apll_l_con[0]); 1527 if (!priv->armbclk_init_hz) 1528 priv->armbclk_init_hz = 1529 rkclk_pll_get_rate(&priv->cru->apll_b_con[0]); 1530 1531 return 0; 1532 } 1533 1534 static int rk3399_clk_ofdata_to_platdata(struct udevice *dev) 1535 { 1536 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 1537 struct rk3399_clk_priv *priv = dev_get_priv(dev); 1538 1539 priv->cru = dev_read_addr_ptr(dev); 1540 #endif 1541 return 0; 1542 } 1543 1544 static int rk3399_clk_bind(struct udevice *dev) 1545 { 1546 int ret; 1547 struct udevice *sys_child, *sf_child; 1548 struct sysreset_reg *priv; 1549 struct softreset_reg *sf_priv; 1550 1551 /* The reset driver does not have a device node, so bind it here */ 1552 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", 1553 &sys_child); 1554 if (ret) { 1555 debug("Warning: No sysreset driver: ret=%d\n", ret); 1556 } else { 1557 priv = malloc(sizeof(struct sysreset_reg)); 1558 priv->glb_srst_fst_value = offsetof(struct rk3399_cru, 1559 glb_srst_fst_value); 1560 priv->glb_srst_snd_value = offsetof(struct rk3399_cru, 1561 glb_srst_snd_value); 1562 sys_child->priv = priv; 1563 } 1564 1565 ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset", 1566 dev_ofnode(dev), &sf_child); 1567 if (ret) { 1568 debug("Warning: No rockchip reset driver: ret=%d\n", ret); 1569 } else { 1570 sf_priv = malloc(sizeof(struct softreset_reg)); 1571 sf_priv->sf_reset_offset = offsetof(struct rk3399_cru, 1572 softrst_con[0]); 1573 sf_priv->sf_reset_num = 21; 1574 sf_child->priv = sf_priv; 1575 } 1576 1577 return 0; 1578 } 1579 1580 static const struct udevice_id rk3399_clk_ids[] = { 1581 { .compatible = "rockchip,rk3399-cru" }, 1582 { } 1583 }; 1584 1585 U_BOOT_DRIVER(clk_rk3399) = { 1586 .name = "rockchip_rk3399_cru", 1587 .id = UCLASS_CLK, 1588 .of_match = rk3399_clk_ids, 1589 .priv_auto_alloc_size = sizeof(struct rk3399_clk_priv), 1590 .ofdata_to_platdata = rk3399_clk_ofdata_to_platdata, 1591 .ops = &rk3399_clk_ops, 1592 .bind = rk3399_clk_bind, 1593 .probe = rk3399_clk_probe, 1594 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1595 .platdata_auto_alloc_size = sizeof(struct rk3399_clk_plat), 1596 #endif 1597 }; 1598 1599 static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id) 1600 { 1601 u32 div, con; 1602 1603 switch (clk_id) { 1604 case SCLK_I2C0_PMU: 1605 con = readl(&pmucru->pmucru_clksel[2]); 1606 div = I2C_CLK_DIV_VALUE(con, 0); 1607 break; 1608 case SCLK_I2C4_PMU: 1609 con = readl(&pmucru->pmucru_clksel[3]); 1610 div = I2C_CLK_DIV_VALUE(con, 4); 1611 break; 1612 case SCLK_I2C8_PMU: 1613 con = readl(&pmucru->pmucru_clksel[2]); 1614 div = I2C_CLK_DIV_VALUE(con, 8); 1615 break; 1616 default: 1617 printf("do not support this i2c bus\n"); 1618 return -EINVAL; 1619 } 1620 1621 return DIV_TO_RATE(PPLL_HZ, div); 1622 } 1623 1624 static ulong rk3399_i2c_set_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id, 1625 uint hz) 1626 { 1627 int src_clk_div; 1628 1629 src_clk_div = PPLL_HZ / hz; 1630 assert(src_clk_div - 1 < 127); 1631 1632 switch (clk_id) { 1633 case SCLK_I2C0_PMU: 1634 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(0), 1635 I2C_PMUCLK_REG_VALUE(0, src_clk_div)); 1636 break; 1637 case SCLK_I2C4_PMU: 1638 rk_clrsetreg(&pmucru->pmucru_clksel[3], I2C_PMUCLK_REG_MASK(4), 1639 I2C_PMUCLK_REG_VALUE(4, src_clk_div)); 1640 break; 1641 case SCLK_I2C8_PMU: 1642 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(8), 1643 I2C_PMUCLK_REG_VALUE(8, src_clk_div)); 1644 break; 1645 default: 1646 printf("do not support this i2c bus\n"); 1647 return -EINVAL; 1648 } 1649 1650 return DIV_TO_RATE(PPLL_HZ, src_clk_div); 1651 } 1652 1653 static ulong rk3399_pwm_get_clk(struct rk3399_pmucru *pmucru) 1654 { 1655 u32 div, con; 1656 1657 /* PWM closk rate is same as pclk_pmu */ 1658 con = readl(&pmucru->pmucru_clksel[0]); 1659 div = con & PMU_PCLK_DIV_CON_MASK; 1660 1661 return DIV_TO_RATE(PPLL_HZ, div); 1662 } 1663 1664 static ulong rk3399_pmuclk_get_rate(struct clk *clk) 1665 { 1666 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev); 1667 ulong rate = 0; 1668 1669 switch (clk->id) { 1670 case PCLK_RKPWM_PMU: 1671 case PCLK_WDT_M0_PMU: 1672 rate = rk3399_pwm_get_clk(priv->pmucru); 1673 break; 1674 case SCLK_I2C0_PMU: 1675 case SCLK_I2C4_PMU: 1676 case SCLK_I2C8_PMU: 1677 rate = rk3399_i2c_get_pmuclk(priv->pmucru, clk->id); 1678 break; 1679 case SCLK_UART4_PMU: 1680 rate = 24000000; 1681 break; 1682 default: 1683 return -ENOENT; 1684 } 1685 1686 return rate; 1687 } 1688 1689 static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate) 1690 { 1691 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev); 1692 ulong ret = 0; 1693 1694 switch (clk->id) { 1695 case SCLK_I2C0_PMU: 1696 case SCLK_I2C4_PMU: 1697 case SCLK_I2C8_PMU: 1698 ret = rk3399_i2c_set_pmuclk(priv->pmucru, clk->id, rate); 1699 break; 1700 default: 1701 return -ENOENT; 1702 } 1703 1704 return ret; 1705 } 1706 1707 static struct clk_ops rk3399_pmuclk_ops = { 1708 .get_rate = rk3399_pmuclk_get_rate, 1709 .set_rate = rk3399_pmuclk_set_rate, 1710 }; 1711 1712 #ifndef CONFIG_SPL_BUILD 1713 static void pmuclk_init(struct rk3399_pmucru *pmucru) 1714 { 1715 u32 pclk_div; 1716 1717 /* configure pmu pll(ppll) */ 1718 rkclk_set_pll(&pmucru->ppll_con[0], &ppll_init_cfg); 1719 1720 /* configure pmu pclk */ 1721 pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1; 1722 rk_clrsetreg(&pmucru->pmucru_clksel[0], 1723 PMU_PCLK_DIV_CON_MASK, 1724 pclk_div << PMU_PCLK_DIV_CON_SHIFT); 1725 } 1726 #endif 1727 1728 static int rk3399_pmuclk_probe(struct udevice *dev) 1729 { 1730 #if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_SPL_BUILD) 1731 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); 1732 #endif 1733 1734 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1735 struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev); 1736 1737 priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); 1738 #endif 1739 1740 #ifndef CONFIG_SPL_BUILD 1741 pmuclk_init(priv->pmucru); 1742 #endif 1743 return 0; 1744 } 1745 1746 static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev) 1747 { 1748 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 1749 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); 1750 1751 priv->pmucru = dev_read_addr_ptr(dev); 1752 #endif 1753 return 0; 1754 } 1755 1756 static int rk3399_pmuclk_bind(struct udevice *dev) 1757 { 1758 int ret = 0; 1759 struct udevice *sf_child; 1760 struct softreset_reg *sf_priv; 1761 1762 ret = device_bind_driver_to_node(dev, "rockchip_reset", 1763 "reset", dev_ofnode(dev), 1764 &sf_child); 1765 if (ret) { 1766 debug("Warning: No rockchip reset driver: ret=%d\n", ret); 1767 } else { 1768 sf_priv = malloc(sizeof(struct softreset_reg)); 1769 sf_priv->sf_reset_offset = offsetof(struct rk3399_pmucru, 1770 pmucru_softrst_con[0]); 1771 sf_priv->sf_reset_num = 2; 1772 sf_child->priv = sf_priv; 1773 } 1774 1775 return 0; 1776 } 1777 1778 static const struct udevice_id rk3399_pmuclk_ids[] = { 1779 { .compatible = "rockchip,rk3399-pmucru" }, 1780 { } 1781 }; 1782 1783 U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = { 1784 .name = "rockchip_rk3399_pmucru", 1785 .id = UCLASS_CLK, 1786 .of_match = rk3399_pmuclk_ids, 1787 .priv_auto_alloc_size = sizeof(struct rk3399_pmuclk_priv), 1788 .ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata, 1789 .ops = &rk3399_pmuclk_ops, 1790 .probe = rk3399_pmuclk_probe, 1791 .bind = rk3399_pmuclk_bind, 1792 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1793 .platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat), 1794 #endif 1795 }; 1796 1797 #ifndef CONFIG_SPL_BUILD 1798 /** 1799 * soc_clk_dump() - Print clock frequencies 1800 * Returns zero on success 1801 * 1802 * Implementation for the clk dump command. 1803 */ 1804 int soc_clk_dump(void) 1805 { 1806 struct udevice *cru_dev, *pmucru_dev; 1807 struct rk3399_clk_priv *priv; 1808 const struct rk3399_clk_info *clk_dump; 1809 struct clk clk; 1810 unsigned long clk_count = ARRAY_SIZE(clks_dump); 1811 unsigned long rate; 1812 int i, ret; 1813 1814 ret = uclass_get_device_by_driver(UCLASS_CLK, 1815 DM_GET_DRIVER(clk_rk3399), 1816 &cru_dev); 1817 if (ret) { 1818 printf("%s failed to get cru device\n", __func__); 1819 return ret; 1820 } 1821 1822 ret = uclass_get_device_by_driver(UCLASS_CLK, 1823 DM_GET_DRIVER(rockchip_rk3399_pmuclk), 1824 &pmucru_dev); 1825 if (ret) { 1826 printf("%s failed to get pmucru device\n", __func__); 1827 return ret; 1828 } 1829 1830 priv = dev_get_priv(cru_dev); 1831 printf("CLK: (%s. arml: enter %lu KHz, init %lu KHz, kernel %lu%s)\n", 1832 priv->sync_kernel ? "sync kernel" : "uboot", 1833 priv->armlclk_enter_hz / 1000, 1834 priv->armlclk_init_hz / 1000, 1835 priv->set_armclk_rate ? priv->armlclk_hz / 1000 : 0, 1836 priv->set_armclk_rate ? " KHz" : "N/A"); 1837 printf("CLK: (%s. armb: enter %lu KHz, init %lu KHz, kernel %lu%s)\n", 1838 priv->sync_kernel ? "sync kernel" : "uboot", 1839 priv->armbclk_enter_hz / 1000, 1840 priv->armbclk_init_hz / 1000, 1841 priv->set_armclk_rate ? priv->armbclk_hz / 1000 : 0, 1842 priv->set_armclk_rate ? " KHz" : "N/A"); 1843 for (i = 0; i < clk_count; i++) { 1844 clk_dump = &clks_dump[i]; 1845 if (clk_dump->name) { 1846 clk.id = clk_dump->id; 1847 if (clk_dump->is_cru) 1848 ret = clk_request(cru_dev, &clk); 1849 else 1850 ret = clk_request(pmucru_dev, &clk); 1851 if (ret < 0) 1852 return ret; 1853 1854 rate = clk_get_rate(&clk); 1855 clk_free(&clk); 1856 if (i == 0) { 1857 if (rate < 0) 1858 printf(" %s %s\n", clk_dump->name, 1859 "unknown"); 1860 else 1861 printf(" %s %lu KHz\n", clk_dump->name, 1862 rate / 1000); 1863 } else { 1864 if (rate < 0) 1865 printf(" %s %s\n", clk_dump->name, 1866 "unknown"); 1867 else 1868 printf(" %s %lu KHz\n", clk_dump->name, 1869 rate / 1000); 1870 } 1871 } 1872 } 1873 1874 return 0; 1875 } 1876 #endif 1877