1 /* 2 * (C) Copyright 2015 Google, Inc 3 * (C) 2017 Theobroma Systems Design und Consulting GmbH 4 * 5 * SPDX-License-Identifier: GPL-2.0 6 */ 7 8 #include <common.h> 9 #include <clk-uclass.h> 10 #include <dm.h> 11 #include <dt-structs.h> 12 #include <errno.h> 13 #include <mapmem.h> 14 #include <syscon.h> 15 #include <bitfield.h> 16 #include <asm/io.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/cru_rk3399.h> 19 #include <asm/arch/hardware.h> 20 #include <dm/lists.h> 21 #include <dt-bindings/clock/rk3399-cru.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #if CONFIG_IS_ENABLED(OF_PLATDATA) 26 struct rk3399_clk_plat { 27 struct dtd_rockchip_rk3399_cru dtd; 28 }; 29 30 struct rk3399_pmuclk_plat { 31 struct dtd_rockchip_rk3399_pmucru dtd; 32 }; 33 #endif 34 35 struct pll_div { 36 u32 refdiv; 37 u32 fbdiv; 38 u32 postdiv1; 39 u32 postdiv2; 40 u32 frac; 41 u32 freq; 42 }; 43 44 #define RATE_TO_DIV(input_rate, output_rate) \ 45 ((input_rate) / (output_rate) - 1); 46 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 47 48 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ 49 .refdiv = _refdiv,\ 50 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ 51 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2, .freq = hz}; 52 53 #if !defined(CONFIG_SPL_BUILD) 54 static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1); 55 #endif 56 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 3, 1); 57 static const struct pll_div npll_init_cfg = PLL_DIVISORS(NPLL_HZ, 1, 3, 1); 58 static const struct pll_div apll_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1); 59 static const struct pll_div apll_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1); 60 61 static const struct pll_div *apll_cfgs[] = { 62 [APLL_1600_MHZ] = &apll_1600_cfg, 63 [APLL_600_MHZ] = &apll_600_cfg, 64 }; 65 66 enum { 67 /* PLL_CON0 */ 68 PLL_FBDIV_MASK = 0xfff, 69 PLL_FBDIV_SHIFT = 0, 70 71 /* PLL_CON1 */ 72 PLL_POSTDIV2_SHIFT = 12, 73 PLL_POSTDIV2_MASK = 0x7 << PLL_POSTDIV2_SHIFT, 74 PLL_POSTDIV1_SHIFT = 8, 75 PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT, 76 PLL_REFDIV_MASK = 0x3f, 77 PLL_REFDIV_SHIFT = 0, 78 79 /* PLL_CON2 */ 80 PLL_LOCK_STATUS_SHIFT = 31, 81 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, 82 PLL_FRACDIV_MASK = 0xffffff, 83 PLL_FRACDIV_SHIFT = 0, 84 85 /* PLL_CON3 */ 86 PLL_MODE_SHIFT = 8, 87 PLL_MODE_MASK = 3 << PLL_MODE_SHIFT, 88 PLL_MODE_SLOW = 0, 89 PLL_MODE_NORM, 90 PLL_MODE_DEEP, 91 PLL_DSMPD_SHIFT = 3, 92 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, 93 PLL_INTEGER_MODE = 1, 94 95 /* PMUCRU_CLKSEL_CON0 */ 96 PMU_PCLK_DIV_CON_MASK = 0x1f, 97 PMU_PCLK_DIV_CON_SHIFT = 0, 98 99 /* PMUCRU_CLKSEL_CON1 */ 100 SPI3_PLL_SEL_SHIFT = 7, 101 SPI3_PLL_SEL_MASK = 1 << SPI3_PLL_SEL_SHIFT, 102 SPI3_PLL_SEL_24M = 0, 103 SPI3_PLL_SEL_PPLL = 1, 104 SPI3_DIV_CON_SHIFT = 0x0, 105 SPI3_DIV_CON_MASK = 0x7f, 106 107 /* PMUCRU_CLKSEL_CON2 */ 108 I2C_DIV_CON_MASK = 0x7f, 109 CLK_I2C8_DIV_CON_SHIFT = 8, 110 CLK_I2C0_DIV_CON_SHIFT = 0, 111 112 /* PMUCRU_CLKSEL_CON3 */ 113 CLK_I2C4_DIV_CON_SHIFT = 0, 114 115 /* CLKSEL_CON0 / CLKSEL_CON2 */ 116 ACLKM_CORE_DIV_CON_MASK = 0x1f, 117 ACLKM_CORE_DIV_CON_SHIFT = 8, 118 CLK_CORE_PLL_SEL_MASK = 3, 119 CLK_CORE_PLL_SEL_SHIFT = 6, 120 CLK_CORE_PLL_SEL_ALPLL = 0x0, 121 CLK_CORE_PLL_SEL_ABPLL = 0x1, 122 CLK_CORE_PLL_SEL_DPLL = 0x10, 123 CLK_CORE_PLL_SEL_GPLL = 0x11, 124 CLK_CORE_DIV_MASK = 0x1f, 125 CLK_CORE_DIV_SHIFT = 0, 126 127 /* CLKSEL_CON1 / CLKSEL_CON3 */ 128 PCLK_DBG_DIV_MASK = 0x1f, 129 PCLK_DBG_DIV_SHIFT = 0x8, 130 ATCLK_CORE_DIV_MASK = 0x1f, 131 ATCLK_CORE_DIV_SHIFT = 0, 132 133 /* CLKSEL_CON14 */ 134 PCLK_PERIHP_DIV_CON_SHIFT = 12, 135 PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT, 136 HCLK_PERIHP_DIV_CON_SHIFT = 8, 137 HCLK_PERIHP_DIV_CON_MASK = 3 << HCLK_PERIHP_DIV_CON_SHIFT, 138 ACLK_PERIHP_PLL_SEL_SHIFT = 7, 139 ACLK_PERIHP_PLL_SEL_MASK = 1 << ACLK_PERIHP_PLL_SEL_SHIFT, 140 ACLK_PERIHP_PLL_SEL_CPLL = 0, 141 ACLK_PERIHP_PLL_SEL_GPLL = 1, 142 ACLK_PERIHP_DIV_CON_SHIFT = 0, 143 ACLK_PERIHP_DIV_CON_MASK = 0x1f, 144 145 /* CLKSEL_CON21 */ 146 ACLK_EMMC_PLL_SEL_SHIFT = 7, 147 ACLK_EMMC_PLL_SEL_MASK = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT, 148 ACLK_EMMC_PLL_SEL_GPLL = 0x1, 149 ACLK_EMMC_DIV_CON_SHIFT = 0, 150 ACLK_EMMC_DIV_CON_MASK = 0x1f, 151 152 /* CLKSEL_CON22 */ 153 CLK_EMMC_PLL_SHIFT = 8, 154 CLK_EMMC_PLL_MASK = 0x7 << CLK_EMMC_PLL_SHIFT, 155 CLK_EMMC_PLL_SEL_GPLL = 0x1, 156 CLK_EMMC_PLL_SEL_24M = 0x5, 157 CLK_EMMC_DIV_CON_SHIFT = 0, 158 CLK_EMMC_DIV_CON_MASK = 0x7f << CLK_EMMC_DIV_CON_SHIFT, 159 160 /* CLKSEL_CON23 */ 161 PCLK_PERILP0_DIV_CON_SHIFT = 12, 162 PCLK_PERILP0_DIV_CON_MASK = 0x7 << PCLK_PERILP0_DIV_CON_SHIFT, 163 HCLK_PERILP0_DIV_CON_SHIFT = 8, 164 HCLK_PERILP0_DIV_CON_MASK = 3 << HCLK_PERILP0_DIV_CON_SHIFT, 165 ACLK_PERILP0_PLL_SEL_SHIFT = 7, 166 ACLK_PERILP0_PLL_SEL_MASK = 1 << ACLK_PERILP0_PLL_SEL_SHIFT, 167 ACLK_PERILP0_PLL_SEL_CPLL = 0, 168 ACLK_PERILP0_PLL_SEL_GPLL = 1, 169 ACLK_PERILP0_DIV_CON_SHIFT = 0, 170 ACLK_PERILP0_DIV_CON_MASK = 0x1f, 171 172 /* CLKSEL_CON25 */ 173 PCLK_PERILP1_DIV_CON_SHIFT = 8, 174 PCLK_PERILP1_DIV_CON_MASK = 0x7 << PCLK_PERILP1_DIV_CON_SHIFT, 175 HCLK_PERILP1_PLL_SEL_SHIFT = 7, 176 HCLK_PERILP1_PLL_SEL_MASK = 1 << HCLK_PERILP1_PLL_SEL_SHIFT, 177 HCLK_PERILP1_PLL_SEL_CPLL = 0, 178 HCLK_PERILP1_PLL_SEL_GPLL = 1, 179 HCLK_PERILP1_DIV_CON_SHIFT = 0, 180 HCLK_PERILP1_DIV_CON_MASK = 0x1f, 181 182 /* CLKSEL_CON26 */ 183 CLK_SARADC_DIV_CON_SHIFT = 8, 184 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8), 185 CLK_SARADC_DIV_CON_WIDTH = 8, 186 187 /* CLKSEL_CON27 */ 188 CLK_TSADC_SEL_X24M = 0x0, 189 CLK_TSADC_SEL_SHIFT = 15, 190 CLK_TSADC_SEL_MASK = 1 << CLK_TSADC_SEL_SHIFT, 191 CLK_TSADC_DIV_CON_SHIFT = 0, 192 CLK_TSADC_DIV_CON_MASK = 0x3ff, 193 194 /* CLKSEL_CON47 & CLKSEL_CON48 */ 195 ACLK_VOP_PLL_SEL_SHIFT = 6, 196 ACLK_VOP_PLL_SEL_MASK = 0x3 << ACLK_VOP_PLL_SEL_SHIFT, 197 ACLK_VOP_PLL_SEL_CPLL = 0x1, 198 ACLK_VOP_PLL_SEL_GPLL = 0x2, 199 ACLK_VOP_DIV_CON_SHIFT = 0, 200 ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT, 201 202 /* CLKSEL_CON49 & CLKSEL_CON50 */ 203 DCLK_VOP_DCLK_SEL_SHIFT = 11, 204 DCLK_VOP_DCLK_SEL_MASK = 1 << DCLK_VOP_DCLK_SEL_SHIFT, 205 DCLK_VOP_DCLK_SEL_DIVOUT = 0, 206 DCLK_VOP_PLL_SEL_SHIFT = 8, 207 DCLK_VOP_PLL_SEL_MASK = 3 << DCLK_VOP_PLL_SEL_SHIFT, 208 DCLK_VOP_PLL_SEL_VPLL = 0, 209 DCLK_VOP_PLL_SEL_CPLL = 1, 210 DCLK_VOP_DIV_CON_MASK = 0xff, 211 DCLK_VOP_DIV_CON_SHIFT = 0, 212 213 /* CLKSEL_CON58 */ 214 CLK_SPI_PLL_SEL_WIDTH = 1, 215 CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1), 216 CLK_SPI_PLL_SEL_CPLL = 0, 217 CLK_SPI_PLL_SEL_GPLL = 1, 218 CLK_SPI_PLL_DIV_CON_WIDTH = 7, 219 CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1), 220 221 CLK_SPI5_PLL_DIV_CON_SHIFT = 8, 222 CLK_SPI5_PLL_SEL_SHIFT = 15, 223 224 /* CLKSEL_CON59 */ 225 CLK_SPI1_PLL_SEL_SHIFT = 15, 226 CLK_SPI1_PLL_DIV_CON_SHIFT = 8, 227 CLK_SPI0_PLL_SEL_SHIFT = 7, 228 CLK_SPI0_PLL_DIV_CON_SHIFT = 0, 229 230 /* CLKSEL_CON60 */ 231 CLK_SPI4_PLL_SEL_SHIFT = 15, 232 CLK_SPI4_PLL_DIV_CON_SHIFT = 8, 233 CLK_SPI2_PLL_SEL_SHIFT = 7, 234 CLK_SPI2_PLL_DIV_CON_SHIFT = 0, 235 236 /* CLKSEL_CON61 */ 237 CLK_I2C_PLL_SEL_MASK = 1, 238 CLK_I2C_PLL_SEL_CPLL = 0, 239 CLK_I2C_PLL_SEL_GPLL = 1, 240 CLK_I2C5_PLL_SEL_SHIFT = 15, 241 CLK_I2C5_DIV_CON_SHIFT = 8, 242 CLK_I2C1_PLL_SEL_SHIFT = 7, 243 CLK_I2C1_DIV_CON_SHIFT = 0, 244 245 /* CLKSEL_CON62 */ 246 CLK_I2C6_PLL_SEL_SHIFT = 15, 247 CLK_I2C6_DIV_CON_SHIFT = 8, 248 CLK_I2C2_PLL_SEL_SHIFT = 7, 249 CLK_I2C2_DIV_CON_SHIFT = 0, 250 251 /* CLKSEL_CON63 */ 252 CLK_I2C7_PLL_SEL_SHIFT = 15, 253 CLK_I2C7_DIV_CON_SHIFT = 8, 254 CLK_I2C3_PLL_SEL_SHIFT = 7, 255 CLK_I2C3_DIV_CON_SHIFT = 0, 256 257 /* CRU_SOFTRST_CON4 */ 258 RESETN_DDR0_REQ_SHIFT = 8, 259 RESETN_DDR0_REQ_MASK = 1 << RESETN_DDR0_REQ_SHIFT, 260 RESETN_DDRPHY0_REQ_SHIFT = 9, 261 RESETN_DDRPHY0_REQ_MASK = 1 << RESETN_DDRPHY0_REQ_SHIFT, 262 RESETN_DDR1_REQ_SHIFT = 12, 263 RESETN_DDR1_REQ_MASK = 1 << RESETN_DDR1_REQ_SHIFT, 264 RESETN_DDRPHY1_REQ_SHIFT = 13, 265 RESETN_DDRPHY1_REQ_MASK = 1 << RESETN_DDRPHY1_REQ_SHIFT, 266 }; 267 268 #define VCO_MAX_KHZ (3200 * (MHz / KHz)) 269 #define VCO_MIN_KHZ (800 * (MHz / KHz)) 270 #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz)) 271 #define OUTPUT_MIN_KHZ (16 * (MHz / KHz)) 272 273 /* 274 * the div restructions of pll in integer mode, these are defined in 275 * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0 276 */ 277 #define PLL_DIV_MIN 16 278 #define PLL_DIV_MAX 3200 279 280 /* 281 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63): 282 * Formulas also embedded within the Fractional PLL Verilog model: 283 * If DSMPD = 1 (DSM is disabled, "integer mode") 284 * FOUTVCO = FREF / REFDIV * FBDIV 285 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 286 * Where: 287 * FOUTVCO = Fractional PLL non-divided output frequency 288 * FOUTPOSTDIV = Fractional PLL divided output frequency 289 * (output of second post divider) 290 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input) 291 * REFDIV = Fractional PLL input reference clock divider 292 * FBDIV = Integer value programmed into feedback divide 293 * 294 */ 295 296 static uint32_t rkclk_pll_get_rate(u32 *pll_con) 297 { 298 u32 refdiv, fbdiv, postdiv1, postdiv2; 299 u32 con; 300 301 con = readl(&pll_con[3]); 302 switch ((con & PLL_MODE_MASK) >> PLL_MODE_SHIFT) { 303 case PLL_MODE_SLOW: 304 return OSC_HZ; 305 case PLL_MODE_NORM: 306 /* normal mode */ 307 con = readl(&pll_con[0]); 308 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; 309 con = readl(&pll_con[1]); 310 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; 311 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; 312 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; 313 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; 314 case PLL_MODE_DEEP: 315 default: 316 return 32768; 317 } 318 } 319 320 static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div) 321 { 322 /* All 8 PLLs have same VCO and output frequency range restrictions. */ 323 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; 324 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; 325 326 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, " 327 "postdiv2=%d, vco=%u khz, output=%u khz\n", 328 pll_con, div->fbdiv, div->refdiv, div->postdiv1, 329 div->postdiv2, vco_khz, output_khz); 330 assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ && 331 output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ && 332 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); 333 334 /* 335 * When power on or changing PLL setting, 336 * we must force PLL into slow mode to ensure output stable clock. 337 */ 338 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, 339 PLL_MODE_SLOW << PLL_MODE_SHIFT); 340 341 /* use integer mode */ 342 rk_clrsetreg(&pll_con[3], PLL_DSMPD_MASK, 343 PLL_INTEGER_MODE << PLL_DSMPD_SHIFT); 344 345 rk_clrsetreg(&pll_con[0], PLL_FBDIV_MASK, 346 div->fbdiv << PLL_FBDIV_SHIFT); 347 rk_clrsetreg(&pll_con[1], 348 PLL_POSTDIV2_MASK | PLL_POSTDIV1_MASK | 349 PLL_REFDIV_MASK | PLL_REFDIV_SHIFT, 350 (div->postdiv2 << PLL_POSTDIV2_SHIFT) | 351 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | 352 (div->refdiv << PLL_REFDIV_SHIFT)); 353 354 /* waiting for pll lock */ 355 while (!(readl(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT))) 356 udelay(1); 357 358 /* pll enter normal mode */ 359 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, 360 PLL_MODE_NORM << PLL_MODE_SHIFT); 361 } 362 363 static ulong rk3399_pll_get_rate(struct rk3399_clk_priv *priv, 364 enum rk3399_pll_id pll_id) 365 { 366 struct rk3399_cru *cru = priv->cru; 367 u32 *pll_con; 368 369 switch (pll_id) { 370 case PLL_APLLL: 371 pll_con = &cru->apll_l_con[0]; 372 break; 373 case PLL_APLLB: 374 pll_con = &cru->apll_b_con[0]; 375 break; 376 case PLL_DPLL: 377 pll_con = &cru->dpll_con[0]; 378 break; 379 case PLL_CPLL: 380 pll_con = &cru->cpll_con[0]; 381 break; 382 case PLL_GPLL: 383 pll_con = &cru->gpll_con[0]; 384 break; 385 case PLL_NPLL: 386 pll_con = &cru->npll_con[0]; 387 break; 388 case PLL_VPLL: 389 pll_con = &cru->vpll_con[0]; 390 break; 391 default: 392 pll_con = &cru->vpll_con[0]; 393 break; 394 } 395 396 return rkclk_pll_get_rate(pll_con); 397 } 398 399 static int pll_para_config(u32 freq_hz, struct pll_div *div) 400 { 401 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; 402 u32 postdiv1, postdiv2 = 1; 403 u32 fref_khz; 404 u32 diff_khz, best_diff_khz; 405 const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16; 406 const u32 max_postdiv1 = 7, max_postdiv2 = 7; 407 u32 vco_khz; 408 u32 freq_khz = freq_hz / KHz; 409 410 if (!freq_hz) { 411 printf("%s: the frequency can't be 0 Hz\n", __func__); 412 return -1; 413 } 414 415 postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz); 416 if (postdiv1 > max_postdiv1) { 417 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); 418 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); 419 } 420 421 vco_khz = freq_khz * postdiv1 * postdiv2; 422 423 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || 424 postdiv2 > max_postdiv2) { 425 printf("%s: Cannot find out a supported VCO" 426 " for Frequency (%uHz).\n", __func__, freq_hz); 427 return -1; 428 } 429 430 div->postdiv1 = postdiv1; 431 div->postdiv2 = postdiv2; 432 433 best_diff_khz = vco_khz; 434 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { 435 fref_khz = ref_khz / refdiv; 436 437 fbdiv = vco_khz / fref_khz; 438 if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv)) 439 continue; 440 diff_khz = vco_khz - fbdiv * fref_khz; 441 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) { 442 fbdiv++; 443 diff_khz = fref_khz - diff_khz; 444 } 445 446 if (diff_khz >= best_diff_khz) 447 continue; 448 449 best_diff_khz = diff_khz; 450 div->refdiv = refdiv; 451 div->fbdiv = fbdiv; 452 } 453 454 if (best_diff_khz > 4 * (MHz/KHz)) { 455 printf("%s: Failed to match output frequency %u, " 456 "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz, 457 best_diff_khz * KHz); 458 return -1; 459 } 460 return 0; 461 } 462 463 void rk3399_configure_cpu(struct rk3399_cru *cru, 464 enum apll_frequencies freq, 465 enum cpu_cluster cluster) 466 { 467 u32 aclkm_div; 468 u32 pclk_dbg_div; 469 u32 atclk_div, apll_hz; 470 int con_base, parent; 471 u32 *pll_con; 472 473 switch (cluster) { 474 case CPU_CLUSTER_LITTLE: 475 con_base = 0; 476 parent = CLK_CORE_PLL_SEL_ALPLL; 477 pll_con = &cru->apll_l_con[0]; 478 break; 479 case CPU_CLUSTER_BIG: 480 default: 481 con_base = 2; 482 parent = CLK_CORE_PLL_SEL_ABPLL; 483 pll_con = &cru->apll_b_con[0]; 484 break; 485 } 486 487 apll_hz = apll_cfgs[freq]->freq; 488 rkclk_set_pll(pll_con, apll_cfgs[freq]); 489 490 aclkm_div = apll_hz / ACLKM_CORE_HZ - 1; 491 assert((aclkm_div + 1) * ACLKM_CORE_HZ == apll_hz && 492 aclkm_div < 0x1f); 493 494 pclk_dbg_div = apll_hz / PCLK_DBG_HZ - 1; 495 assert((pclk_dbg_div + 1) * PCLK_DBG_HZ == apll_hz && 496 pclk_dbg_div < 0x1f); 497 498 atclk_div = apll_hz / ATCLK_CORE_HZ - 1; 499 assert((atclk_div + 1) * ATCLK_CORE_HZ == apll_hz && 500 atclk_div < 0x1f); 501 502 rk_clrsetreg(&cru->clksel_con[con_base], 503 ACLKM_CORE_DIV_CON_MASK | CLK_CORE_PLL_SEL_MASK | 504 CLK_CORE_DIV_MASK, 505 aclkm_div << ACLKM_CORE_DIV_CON_SHIFT | 506 parent << CLK_CORE_PLL_SEL_SHIFT | 507 0 << CLK_CORE_DIV_SHIFT); 508 509 rk_clrsetreg(&cru->clksel_con[con_base + 1], 510 PCLK_DBG_DIV_MASK | ATCLK_CORE_DIV_MASK, 511 pclk_dbg_div << PCLK_DBG_DIV_SHIFT | 512 atclk_div << ATCLK_CORE_DIV_SHIFT); 513 } 514 #define I2C_CLK_REG_MASK(bus) \ 515 (I2C_DIV_CON_MASK << \ 516 CLK_I2C ##bus## _DIV_CON_SHIFT | \ 517 CLK_I2C_PLL_SEL_MASK << \ 518 CLK_I2C ##bus## _PLL_SEL_SHIFT) 519 520 #define I2C_CLK_REG_VALUE(bus, clk_div) \ 521 ((clk_div - 1) << \ 522 CLK_I2C ##bus## _DIV_CON_SHIFT | \ 523 CLK_I2C_PLL_SEL_GPLL << \ 524 CLK_I2C ##bus## _PLL_SEL_SHIFT) 525 526 #define I2C_CLK_DIV_VALUE(con, bus) \ 527 (con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \ 528 I2C_DIV_CON_MASK; 529 530 #define I2C_PMUCLK_REG_MASK(bus) \ 531 (I2C_DIV_CON_MASK << \ 532 CLK_I2C ##bus## _DIV_CON_SHIFT) 533 534 #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \ 535 ((clk_div - 1) << \ 536 CLK_I2C ##bus## _DIV_CON_SHIFT) 537 538 static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id) 539 { 540 u32 div, con; 541 542 switch (clk_id) { 543 case SCLK_I2C1: 544 con = readl(&cru->clksel_con[61]); 545 div = I2C_CLK_DIV_VALUE(con, 1); 546 break; 547 case SCLK_I2C2: 548 con = readl(&cru->clksel_con[62]); 549 div = I2C_CLK_DIV_VALUE(con, 2); 550 break; 551 case SCLK_I2C3: 552 con = readl(&cru->clksel_con[63]); 553 div = I2C_CLK_DIV_VALUE(con, 3); 554 break; 555 case SCLK_I2C5: 556 con = readl(&cru->clksel_con[61]); 557 div = I2C_CLK_DIV_VALUE(con, 5); 558 break; 559 case SCLK_I2C6: 560 con = readl(&cru->clksel_con[62]); 561 div = I2C_CLK_DIV_VALUE(con, 6); 562 break; 563 case SCLK_I2C7: 564 con = readl(&cru->clksel_con[63]); 565 div = I2C_CLK_DIV_VALUE(con, 7); 566 break; 567 default: 568 printf("do not support this i2c bus\n"); 569 return -EINVAL; 570 } 571 572 return DIV_TO_RATE(GPLL_HZ, div); 573 } 574 575 static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) 576 { 577 int src_clk_div; 578 579 /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/ 580 src_clk_div = GPLL_HZ / hz; 581 assert(src_clk_div - 1 <= 127); 582 583 switch (clk_id) { 584 case SCLK_I2C1: 585 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(1), 586 I2C_CLK_REG_VALUE(1, src_clk_div)); 587 break; 588 case SCLK_I2C2: 589 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(2), 590 I2C_CLK_REG_VALUE(2, src_clk_div)); 591 break; 592 case SCLK_I2C3: 593 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(3), 594 I2C_CLK_REG_VALUE(3, src_clk_div)); 595 break; 596 case SCLK_I2C5: 597 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(5), 598 I2C_CLK_REG_VALUE(5, src_clk_div)); 599 break; 600 case SCLK_I2C6: 601 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(6), 602 I2C_CLK_REG_VALUE(6, src_clk_div)); 603 break; 604 case SCLK_I2C7: 605 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(7), 606 I2C_CLK_REG_VALUE(7, src_clk_div)); 607 break; 608 default: 609 printf("do not support this i2c bus\n"); 610 return -EINVAL; 611 } 612 613 return rk3399_i2c_get_clk(cru, clk_id); 614 } 615 616 /* 617 * RK3399 SPI clocks have a common divider-width (7 bits) and a single bit 618 * to select either CPLL or GPLL as the clock-parent. The location within 619 * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable. 620 */ 621 622 struct spi_clkreg { 623 uint8_t reg; /* CLKSEL_CON[reg] register in CRU */ 624 uint8_t div_shift; 625 uint8_t sel_shift; 626 }; 627 628 /* 629 * The entries are numbered relative to their offset from SCLK_SPI0. 630 * 631 * Note that SCLK_SPI3 (which is configured via PMUCRU and requires different 632 * logic is not supported). 633 */ 634 static const struct spi_clkreg spi_clkregs[] = { 635 [0] = { .reg = 59, 636 .div_shift = CLK_SPI0_PLL_DIV_CON_SHIFT, 637 .sel_shift = CLK_SPI0_PLL_SEL_SHIFT, }, 638 [1] = { .reg = 59, 639 .div_shift = CLK_SPI1_PLL_DIV_CON_SHIFT, 640 .sel_shift = CLK_SPI1_PLL_SEL_SHIFT, }, 641 [2] = { .reg = 60, 642 .div_shift = CLK_SPI2_PLL_DIV_CON_SHIFT, 643 .sel_shift = CLK_SPI2_PLL_SEL_SHIFT, }, 644 [3] = { .reg = 60, 645 .div_shift = CLK_SPI4_PLL_DIV_CON_SHIFT, 646 .sel_shift = CLK_SPI4_PLL_SEL_SHIFT, }, 647 [4] = { .reg = 58, 648 .div_shift = CLK_SPI5_PLL_DIV_CON_SHIFT, 649 .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, }, 650 }; 651 652 static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id) 653 { 654 const struct spi_clkreg *spiclk = NULL; 655 u32 div, val; 656 657 switch (clk_id) { 658 case SCLK_SPI0 ... SCLK_SPI5: 659 spiclk = &spi_clkregs[clk_id - SCLK_SPI0]; 660 break; 661 662 default: 663 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id); 664 return -EINVAL; 665 } 666 667 val = readl(&cru->clksel_con[spiclk->reg]); 668 div = bitfield_extract(val, spiclk->div_shift, 669 CLK_SPI_PLL_DIV_CON_WIDTH); 670 671 return DIV_TO_RATE(GPLL_HZ, div); 672 } 673 674 static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) 675 { 676 const struct spi_clkreg *spiclk = NULL; 677 int src_clk_div; 678 679 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; 680 assert(src_clk_div < 128); 681 682 switch (clk_id) { 683 case SCLK_SPI1 ... SCLK_SPI5: 684 spiclk = &spi_clkregs[clk_id - SCLK_SPI0]; 685 break; 686 687 default: 688 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id); 689 return -EINVAL; 690 } 691 692 rk_clrsetreg(&cru->clksel_con[spiclk->reg], 693 ((CLK_SPI_PLL_DIV_CON_MASK << spiclk->div_shift) | 694 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)), 695 ((src_clk_div << spiclk->div_shift) | 696 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift))); 697 698 return rk3399_spi_get_clk(cru, clk_id); 699 } 700 701 #define RK3399_LIMIT_PLL_ACLK_VOP (400 * 1000000) 702 703 static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz) 704 { 705 struct pll_div vpll_config = {0}, cpll_config = {0}; 706 int aclk_vop = RK3399_LIMIT_PLL_ACLK_VOP; 707 void *aclkreg_addr, *dclkreg_addr; 708 u32 div = 1; 709 710 switch (clk_id) { 711 case DCLK_VOP0: 712 aclkreg_addr = &cru->clksel_con[47]; 713 dclkreg_addr = &cru->clksel_con[49]; 714 break; 715 case DCLK_VOP1: 716 aclkreg_addr = &cru->clksel_con[48]; 717 dclkreg_addr = &cru->clksel_con[50]; 718 break; 719 default: 720 return -EINVAL; 721 } 722 /* vop aclk source clk: cpll */ 723 div = GPLL_HZ / aclk_vop; 724 assert(div - 1 <= 31); 725 726 rk_clrsetreg(aclkreg_addr, 727 ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK, 728 ACLK_VOP_PLL_SEL_GPLL << ACLK_VOP_PLL_SEL_SHIFT | 729 (div - 1) << ACLK_VOP_DIV_CON_SHIFT); 730 731 if (readl(dclkreg_addr) & DCLK_VOP_PLL_SEL_MASK) { 732 if (pll_para_config(hz, &cpll_config)) 733 return -1; 734 rkclk_set_pll(&cru->cpll_con[0], &cpll_config); 735 } else { 736 if (pll_para_config(hz, &vpll_config)) 737 return -1; 738 rkclk_set_pll(&cru->vpll_con[0], &vpll_config); 739 } 740 741 rk_clrsetreg(dclkreg_addr, 742 DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_DIV_CON_MASK, 743 DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT | 744 (1 - 1) << DCLK_VOP_DIV_CON_SHIFT); 745 746 return hz; 747 } 748 749 static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id) 750 { 751 u32 div, con; 752 753 switch (clk_id) { 754 case HCLK_SDMMC: 755 case SCLK_SDMMC: 756 con = readl(&cru->clksel_con[16]); 757 /* dwmmc controller have internal div 2 */ 758 div = 2; 759 break; 760 case SCLK_EMMC: 761 con = readl(&cru->clksel_con[22]); 762 div = 1; 763 break; 764 default: 765 return -EINVAL; 766 } 767 768 div *= (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT; 769 if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT 770 == CLK_EMMC_PLL_SEL_24M) 771 return DIV_TO_RATE(OSC_HZ, div); 772 else 773 return DIV_TO_RATE(GPLL_HZ, div); 774 } 775 776 static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru, 777 ulong clk_id, ulong set_rate) 778 { 779 int src_clk_div; 780 int aclk_emmc = 198*MHz; 781 782 switch (clk_id) { 783 case HCLK_SDMMC: 784 case SCLK_SDMMC: 785 /* Select clk_sdmmc source from GPLL by default */ 786 /* mmc clock defaulg div 2 internal, provide double in cru */ 787 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate); 788 789 if (src_clk_div > 128) { 790 /* use 24MHz source for 400KHz clock */ 791 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); 792 assert(src_clk_div - 1 < 128); 793 rk_clrsetreg(&cru->clksel_con[16], 794 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 795 CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT | 796 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 797 } else { 798 rk_clrsetreg(&cru->clksel_con[16], 799 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 800 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | 801 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 802 } 803 break; 804 case SCLK_EMMC: 805 /* Select aclk_emmc source from GPLL */ 806 src_clk_div = DIV_ROUND_UP(GPLL_HZ , aclk_emmc); 807 assert(src_clk_div - 1 < 32); 808 809 rk_clrsetreg(&cru->clksel_con[21], 810 ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK, 811 ACLK_EMMC_PLL_SEL_GPLL << ACLK_EMMC_PLL_SEL_SHIFT | 812 (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT); 813 814 /* Select clk_emmc source from GPLL too */ 815 src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate); 816 if (src_clk_div > 128) { 817 /* use 24MHz source for 400KHz clock */ 818 src_clk_div = DIV_ROUND_UP(OSC_HZ, set_rate); 819 assert(src_clk_div - 1 < 128); 820 rk_clrsetreg(&cru->clksel_con[22], 821 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 822 CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT | 823 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 824 } else { 825 rk_clrsetreg(&cru->clksel_con[22], 826 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 827 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | 828 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 829 } 830 break; 831 default: 832 return -EINVAL; 833 } 834 return rk3399_mmc_get_clk(cru, clk_id); 835 } 836 837 static ulong rk3399_gmac_set_clk(struct rk3399_cru *cru, ulong rate) 838 { 839 ulong ret; 840 841 /* 842 * The RGMII CLK can be derived either from an external "clkin" 843 * or can be generated from internally by a divider from SCLK_MAC. 844 */ 845 if (readl(&cru->clksel_con[19]) & BIT(4)) { 846 /* An external clock will always generate the right rate... */ 847 ret = rate; 848 } else { 849 /* 850 * No platform uses an internal clock to date. 851 * Implement this once it becomes necessary and print an error 852 * if someone tries to use it (while it remains unimplemented). 853 */ 854 pr_err("%s: internal clock is UNIMPLEMENTED\n", __func__); 855 ret = 0; 856 } 857 858 return ret; 859 } 860 861 #define PMUSGRF_DDR_RGN_CON16 0xff330040 862 static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru, 863 ulong set_rate) 864 { 865 struct pll_div dpll_cfg; 866 867 /* IC ECO bug, need to set this register */ 868 writel(0xc000c000, PMUSGRF_DDR_RGN_CON16); 869 870 /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */ 871 switch (set_rate) { 872 case 200*MHz: 873 dpll_cfg = (struct pll_div) 874 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1}; 875 break; 876 case 300*MHz: 877 dpll_cfg = (struct pll_div) 878 {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1}; 879 break; 880 case 666*MHz: 881 dpll_cfg = (struct pll_div) 882 {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1}; 883 break; 884 case 800*MHz: 885 dpll_cfg = (struct pll_div) 886 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}; 887 break; 888 case 933*MHz: 889 dpll_cfg = (struct pll_div) 890 {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1}; 891 break; 892 default: 893 pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate); 894 } 895 rkclk_set_pll(&cru->dpll_con[0], &dpll_cfg); 896 897 return set_rate; 898 } 899 900 static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru) 901 { 902 u32 div, val; 903 904 val = readl(&cru->clksel_con[26]); 905 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT, 906 CLK_SARADC_DIV_CON_WIDTH); 907 908 return DIV_TO_RATE(OSC_HZ, div); 909 } 910 911 static ulong rk3399_saradc_set_clk(struct rk3399_cru *cru, uint hz) 912 { 913 int src_clk_div; 914 915 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; 916 assert(src_clk_div <= 255); 917 918 rk_clrsetreg(&cru->clksel_con[26], 919 CLK_SARADC_DIV_CON_MASK, 920 src_clk_div << CLK_SARADC_DIV_CON_SHIFT); 921 922 return rk3399_saradc_get_clk(cru); 923 } 924 925 static ulong rk3399_tsadc_get_clk(struct rk3399_cru *cru) 926 { 927 u32 div, val; 928 929 val = readl(&cru->clksel_con[27]); 930 div = bitfield_extract(val, CLK_TSADC_SEL_SHIFT, 931 10); 932 933 return DIV_TO_RATE(OSC_HZ, div); 934 } 935 936 static ulong rk3399_tsadc_set_clk(struct rk3399_cru *cru, uint hz) 937 { 938 int src_clk_div; 939 940 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; 941 assert(src_clk_div <= 255); 942 943 rk_clrsetreg(&cru->clksel_con[27], 944 CLK_TSADC_DIV_CON_MASK | CLK_TSADC_SEL_MASK, 945 (CLK_TSADC_SEL_X24M << CLK_TSADC_SEL_SHIFT) | 946 (src_clk_div << CLK_TSADC_DIV_CON_SHIFT)); 947 948 return rk3399_tsadc_get_clk(cru); 949 } 950 951 static ulong rk3399_clk_get_rate(struct clk *clk) 952 { 953 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 954 ulong rate = 0; 955 956 switch (clk->id) { 957 case PLL_APLLL: 958 case PLL_APLLB: 959 case PLL_DPLL: 960 case PLL_CPLL: 961 case PLL_GPLL: 962 case PLL_NPLL: 963 case PLL_VPLL: 964 rate = rk3399_pll_get_rate(priv, clk->id - 1); 965 break; 966 case HCLK_SDMMC: 967 case SCLK_SDMMC: 968 case SCLK_EMMC: 969 rate = rk3399_mmc_get_clk(priv->cru, clk->id); 970 break; 971 case SCLK_I2C1: 972 case SCLK_I2C2: 973 case SCLK_I2C3: 974 case SCLK_I2C5: 975 case SCLK_I2C6: 976 case SCLK_I2C7: 977 rate = rk3399_i2c_get_clk(priv->cru, clk->id); 978 break; 979 case SCLK_SPI0...SCLK_SPI5: 980 rate = rk3399_spi_get_clk(priv->cru, clk->id); 981 break; 982 case SCLK_UART0: 983 case SCLK_UART1: 984 case SCLK_UART2: 985 case SCLK_UART3: 986 return 24000000; 987 break; 988 case PCLK_HDMI_CTRL: 989 break; 990 case DCLK_VOP0: 991 case DCLK_VOP1: 992 break; 993 case PCLK_EFUSE1024NS: 994 break; 995 case SCLK_SARADC: 996 rate = rk3399_saradc_get_clk(priv->cru); 997 break; 998 case SCLK_TSADC: 999 rate = rk3399_tsadc_get_clk(priv->cru); 1000 break; 1001 default: 1002 return -ENOENT; 1003 } 1004 1005 return rate; 1006 } 1007 1008 static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) 1009 { 1010 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 1011 ulong ret = 0; 1012 1013 switch (clk->id) { 1014 case 0 ... 63: 1015 return 0; 1016 1017 case ACLK_PERIHP: 1018 case HCLK_PERIHP: 1019 case PCLK_PERIHP: 1020 return 0; 1021 1022 case ACLK_PERILP0: 1023 case HCLK_PERILP0: 1024 case PCLK_PERILP0: 1025 return 0; 1026 1027 case ACLK_CCI: 1028 return 0; 1029 1030 case HCLK_PERILP1: 1031 case PCLK_PERILP1: 1032 return 0; 1033 1034 case HCLK_SDMMC: 1035 case SCLK_SDMMC: 1036 case SCLK_EMMC: 1037 ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate); 1038 break; 1039 case SCLK_MAC: 1040 ret = rk3399_gmac_set_clk(priv->cru, rate); 1041 break; 1042 case SCLK_I2C1: 1043 case SCLK_I2C2: 1044 case SCLK_I2C3: 1045 case SCLK_I2C5: 1046 case SCLK_I2C6: 1047 case SCLK_I2C7: 1048 ret = rk3399_i2c_set_clk(priv->cru, clk->id, rate); 1049 break; 1050 case SCLK_SPI0...SCLK_SPI5: 1051 ret = rk3399_spi_set_clk(priv->cru, clk->id, rate); 1052 break; 1053 case PCLK_HDMI_CTRL: 1054 case PCLK_VIO_GRF: 1055 /* the PCLK gates for video are enabled by default */ 1056 break; 1057 case DCLK_VOP0: 1058 case DCLK_VOP1: 1059 ret = rk3399_vop_set_clk(priv->cru, clk->id, rate); 1060 break; 1061 case SCLK_DDRCLK: 1062 ret = rk3399_ddr_set_clk(priv->cru, rate); 1063 break; 1064 case PCLK_EFUSE1024NS: 1065 break; 1066 case SCLK_SARADC: 1067 ret = rk3399_saradc_set_clk(priv->cru, rate); 1068 break; 1069 case SCLK_TSADC: 1070 ret = rk3399_tsadc_set_clk(priv->cru, rate); 1071 break; 1072 default: 1073 return -ENOENT; 1074 } 1075 1076 return ret; 1077 } 1078 1079 static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk, struct clk *parent) 1080 { 1081 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 1082 const char *clock_output_name; 1083 int ret; 1084 1085 /* 1086 * If the requested parent is in the same clock-controller and 1087 * the id is SCLK_MAC ("clk_gmac"), switch to the internal clock. 1088 */ 1089 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC)) { 1090 debug("%s: switching RGMII to SCLK_MAC\n", __func__); 1091 rk_clrreg(&priv->cru->clksel_con[19], BIT(4)); 1092 return 0; 1093 } 1094 1095 /* 1096 * Otherwise, we need to check the clock-output-names of the 1097 * requested parent to see if the requested id is "clkin_gmac". 1098 */ 1099 ret = dev_read_string_index(parent->dev, "clock-output-names", 1100 parent->id, &clock_output_name); 1101 if (ret < 0) 1102 return -ENODATA; 1103 1104 /* If this is "clkin_gmac", switch to the external clock input */ 1105 if (!strcmp(clock_output_name, "clkin_gmac")) { 1106 debug("%s: switching RGMII to CLKIN\n", __func__); 1107 rk_setreg(&priv->cru->clksel_con[19], BIT(4)); 1108 return 0; 1109 } 1110 1111 return -EINVAL; 1112 } 1113 1114 static int __maybe_unused rk3399_dclk_vop_set_parent(struct clk *clk, 1115 struct clk *parent) 1116 { 1117 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 1118 void *dclkreg_addr; 1119 1120 switch (clk->id) { 1121 case DCLK_VOP0_DIV: 1122 dclkreg_addr = &priv->cru->clksel_con[49]; 1123 break; 1124 case DCLK_VOP1_DIV: 1125 dclkreg_addr = &priv->cru->clksel_con[50]; 1126 break; 1127 default: 1128 return -EINVAL; 1129 } 1130 if (parent->id == PLL_CPLL) { 1131 rk_clrsetreg(dclkreg_addr, DCLK_VOP_PLL_SEL_MASK, 1132 DCLK_VOP_PLL_SEL_CPLL << DCLK_VOP_PLL_SEL_SHIFT); 1133 } else { 1134 rk_clrsetreg(dclkreg_addr, DCLK_VOP_PLL_SEL_MASK, 1135 DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT); 1136 } 1137 1138 return 0; 1139 } 1140 1141 static int __maybe_unused rk3399_clk_set_parent(struct clk *clk, struct clk *parent) 1142 { 1143 switch (clk->id) { 1144 case SCLK_RMII_SRC: 1145 return rk3399_gmac_set_parent(clk, parent); 1146 case DCLK_VOP0_DIV: 1147 case DCLK_VOP1_DIV: 1148 return rk3399_dclk_vop_set_parent(clk, parent); 1149 } 1150 1151 debug("%s: unsupported clk %ld\n", __func__, clk->id); 1152 return -ENOENT; 1153 } 1154 1155 static int rk3399_clk_enable(struct clk *clk) 1156 { 1157 switch (clk->id) { 1158 case HCLK_HOST0: 1159 case HCLK_HOST0_ARB: 1160 case SCLK_USBPHY0_480M_SRC: 1161 case HCLK_HOST1: 1162 case HCLK_HOST1_ARB: 1163 case SCLK_USBPHY1_480M_SRC: 1164 return 0; 1165 } 1166 1167 debug("%s: unsupported clk %ld\n", __func__, clk->id); 1168 return -ENOENT; 1169 } 1170 1171 static struct clk_ops rk3399_clk_ops = { 1172 .get_rate = rk3399_clk_get_rate, 1173 .set_rate = rk3399_clk_set_rate, 1174 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 1175 .set_parent = rk3399_clk_set_parent, 1176 #endif 1177 .enable = rk3399_clk_enable, 1178 }; 1179 1180 static void rkclk_init(struct rk3399_cru *cru) 1181 { 1182 u32 aclk_div; 1183 u32 hclk_div; 1184 u32 pclk_div; 1185 1186 rk3399_configure_cpu(cru, APLL_600_MHZ, CPU_CLUSTER_LITTLE); 1187 1188 /* 1189 * some cru registers changed by bootrom, we'd better reset them to 1190 * reset/default values described in TRM to avoid confusion in kernel. 1191 * Please consider these three lines as a fix of bootrom bug. 1192 */ 1193 if (rkclk_pll_get_rate(&cru->npll_con[0]) != NPLL_HZ) 1194 rkclk_set_pll(&cru->npll_con[0], &npll_init_cfg); 1195 1196 if (rkclk_pll_get_rate(&cru->gpll_con[0]) == GPLL_HZ) 1197 return; 1198 1199 rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101); 1200 rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f); 1201 rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003); 1202 1203 /* configure perihp aclk, hclk, pclk */ 1204 aclk_div = DIV_ROUND_UP(GPLL_HZ, PERIHP_ACLK_HZ) - 1; 1205 1206 hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1; 1207 assert((hclk_div + 1) * PERIHP_HCLK_HZ == 1208 PERIHP_ACLK_HZ && (hclk_div <= 0x3)); 1209 1210 pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1; 1211 assert((pclk_div + 1) * PERIHP_PCLK_HZ == 1212 PERIHP_ACLK_HZ && (pclk_div <= 0x7)); 1213 1214 rk_clrsetreg(&cru->clksel_con[14], 1215 PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK | 1216 ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK, 1217 pclk_div << PCLK_PERIHP_DIV_CON_SHIFT | 1218 hclk_div << HCLK_PERIHP_DIV_CON_SHIFT | 1219 ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT | 1220 aclk_div << ACLK_PERIHP_DIV_CON_SHIFT); 1221 1222 /* configure perilp0 aclk, hclk, pclk */ 1223 aclk_div = DIV_ROUND_UP(GPLL_HZ, PERILP0_ACLK_HZ) - 1; 1224 1225 hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1; 1226 assert((hclk_div + 1) * PERILP0_HCLK_HZ == 1227 PERILP0_ACLK_HZ && (hclk_div <= 0x3)); 1228 1229 pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1; 1230 assert((pclk_div + 1) * PERILP0_PCLK_HZ == 1231 PERILP0_ACLK_HZ && (pclk_div <= 0x7)); 1232 1233 rk_clrsetreg(&cru->clksel_con[23], 1234 PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK | 1235 ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK, 1236 pclk_div << PCLK_PERILP0_DIV_CON_SHIFT | 1237 hclk_div << HCLK_PERILP0_DIV_CON_SHIFT | 1238 ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT | 1239 aclk_div << ACLK_PERILP0_DIV_CON_SHIFT); 1240 1241 /* perilp1 hclk select gpll as source */ 1242 hclk_div = DIV_ROUND_UP(GPLL_HZ, PERILP1_HCLK_HZ) - 1; 1243 assert((hclk_div + 1) * PERILP1_HCLK_HZ == 1244 GPLL_HZ && (hclk_div <= 0x1f)); 1245 1246 pclk_div = PERILP1_HCLK_HZ / PERILP1_PCLK_HZ - 1; 1247 assert((pclk_div + 1) * PERILP1_PCLK_HZ == 1248 PERILP1_HCLK_HZ && (pclk_div <= 0x7)); 1249 1250 rk_clrsetreg(&cru->clksel_con[25], 1251 PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK | 1252 HCLK_PERILP1_PLL_SEL_MASK, 1253 pclk_div << PCLK_PERILP1_DIV_CON_SHIFT | 1254 hclk_div << HCLK_PERILP1_DIV_CON_SHIFT | 1255 HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT); 1256 1257 rk_clrsetreg(&cru->clksel_con[21], 1258 ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK, 1259 ACLK_EMMC_PLL_SEL_GPLL << ACLK_EMMC_PLL_SEL_SHIFT | 1260 (4 - 1) << ACLK_EMMC_DIV_CON_SHIFT); 1261 rk_clrsetreg(&cru->clksel_con[22], 0x3f << 0, 7 << 0); 1262 1263 rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg); 1264 } 1265 1266 static int rk3399_clk_probe(struct udevice *dev) 1267 { 1268 struct rk3399_clk_priv *priv = dev_get_priv(dev); 1269 1270 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1271 struct rk3399_clk_plat *plat = dev_get_platdata(dev); 1272 1273 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); 1274 #endif 1275 rkclk_init(priv->cru); 1276 return 0; 1277 } 1278 1279 static int rk3399_clk_ofdata_to_platdata(struct udevice *dev) 1280 { 1281 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 1282 struct rk3399_clk_priv *priv = dev_get_priv(dev); 1283 1284 priv->cru = dev_read_addr_ptr(dev); 1285 #endif 1286 return 0; 1287 } 1288 1289 static int rk3399_clk_bind(struct udevice *dev) 1290 { 1291 int ret; 1292 struct udevice *sys_child, *sf_child; 1293 struct sysreset_reg *priv; 1294 struct softreset_reg *sf_priv; 1295 1296 /* The reset driver does not have a device node, so bind it here */ 1297 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", 1298 &sys_child); 1299 if (ret) { 1300 debug("Warning: No sysreset driver: ret=%d\n", ret); 1301 } else { 1302 priv = malloc(sizeof(struct sysreset_reg)); 1303 priv->glb_srst_fst_value = offsetof(struct rk3399_cru, 1304 glb_srst_fst_value); 1305 priv->glb_srst_snd_value = offsetof(struct rk3399_cru, 1306 glb_srst_snd_value); 1307 sys_child->priv = priv; 1308 } 1309 1310 ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset", 1311 dev_ofnode(dev), &sf_child); 1312 if (ret) { 1313 debug("Warning: No rockchip reset driver: ret=%d\n", ret); 1314 } else { 1315 sf_priv = malloc(sizeof(struct softreset_reg)); 1316 sf_priv->sf_reset_offset = offsetof(struct rk3399_cru, 1317 softrst_con[0]); 1318 sf_priv->sf_reset_num = 21; 1319 sf_child->priv = sf_priv; 1320 } 1321 1322 return 0; 1323 } 1324 1325 static const struct udevice_id rk3399_clk_ids[] = { 1326 { .compatible = "rockchip,rk3399-cru" }, 1327 { } 1328 }; 1329 1330 U_BOOT_DRIVER(clk_rk3399) = { 1331 .name = "rockchip_rk3399_cru", 1332 .id = UCLASS_CLK, 1333 .of_match = rk3399_clk_ids, 1334 .priv_auto_alloc_size = sizeof(struct rk3399_clk_priv), 1335 .ofdata_to_platdata = rk3399_clk_ofdata_to_platdata, 1336 .ops = &rk3399_clk_ops, 1337 .bind = rk3399_clk_bind, 1338 .probe = rk3399_clk_probe, 1339 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1340 .platdata_auto_alloc_size = sizeof(struct rk3399_clk_plat), 1341 #endif 1342 }; 1343 1344 static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id) 1345 { 1346 u32 div, con; 1347 1348 switch (clk_id) { 1349 case SCLK_I2C0_PMU: 1350 con = readl(&pmucru->pmucru_clksel[2]); 1351 div = I2C_CLK_DIV_VALUE(con, 0); 1352 break; 1353 case SCLK_I2C4_PMU: 1354 con = readl(&pmucru->pmucru_clksel[3]); 1355 div = I2C_CLK_DIV_VALUE(con, 4); 1356 break; 1357 case SCLK_I2C8_PMU: 1358 con = readl(&pmucru->pmucru_clksel[2]); 1359 div = I2C_CLK_DIV_VALUE(con, 8); 1360 break; 1361 default: 1362 printf("do not support this i2c bus\n"); 1363 return -EINVAL; 1364 } 1365 1366 return DIV_TO_RATE(PPLL_HZ, div); 1367 } 1368 1369 static ulong rk3399_i2c_set_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id, 1370 uint hz) 1371 { 1372 int src_clk_div; 1373 1374 src_clk_div = PPLL_HZ / hz; 1375 assert(src_clk_div - 1 < 127); 1376 1377 switch (clk_id) { 1378 case SCLK_I2C0_PMU: 1379 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(0), 1380 I2C_PMUCLK_REG_VALUE(0, src_clk_div)); 1381 break; 1382 case SCLK_I2C4_PMU: 1383 rk_clrsetreg(&pmucru->pmucru_clksel[3], I2C_PMUCLK_REG_MASK(4), 1384 I2C_PMUCLK_REG_VALUE(4, src_clk_div)); 1385 break; 1386 case SCLK_I2C8_PMU: 1387 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(8), 1388 I2C_PMUCLK_REG_VALUE(8, src_clk_div)); 1389 break; 1390 default: 1391 printf("do not support this i2c bus\n"); 1392 return -EINVAL; 1393 } 1394 1395 return DIV_TO_RATE(PPLL_HZ, src_clk_div); 1396 } 1397 1398 static ulong rk3399_pwm_get_clk(struct rk3399_pmucru *pmucru) 1399 { 1400 u32 div, con; 1401 1402 /* PWM closk rate is same as pclk_pmu */ 1403 con = readl(&pmucru->pmucru_clksel[0]); 1404 div = con & PMU_PCLK_DIV_CON_MASK; 1405 1406 return DIV_TO_RATE(PPLL_HZ, div); 1407 } 1408 1409 static ulong rk3399_pmuclk_get_rate(struct clk *clk) 1410 { 1411 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev); 1412 ulong rate = 0; 1413 1414 switch (clk->id) { 1415 case PCLK_RKPWM_PMU: 1416 rate = rk3399_pwm_get_clk(priv->pmucru); 1417 break; 1418 case SCLK_I2C0_PMU: 1419 case SCLK_I2C4_PMU: 1420 case SCLK_I2C8_PMU: 1421 rate = rk3399_i2c_get_pmuclk(priv->pmucru, clk->id); 1422 break; 1423 case SCLK_UART4_PMU: 1424 rate = 24000000; 1425 break; 1426 default: 1427 return -ENOENT; 1428 } 1429 1430 return rate; 1431 } 1432 1433 static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate) 1434 { 1435 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev); 1436 ulong ret = 0; 1437 1438 switch (clk->id) { 1439 case SCLK_I2C0_PMU: 1440 case SCLK_I2C4_PMU: 1441 case SCLK_I2C8_PMU: 1442 ret = rk3399_i2c_set_pmuclk(priv->pmucru, clk->id, rate); 1443 break; 1444 default: 1445 return -ENOENT; 1446 } 1447 1448 return ret; 1449 } 1450 1451 static struct clk_ops rk3399_pmuclk_ops = { 1452 .get_rate = rk3399_pmuclk_get_rate, 1453 .set_rate = rk3399_pmuclk_set_rate, 1454 }; 1455 1456 #ifndef CONFIG_SPL_BUILD 1457 static void pmuclk_init(struct rk3399_pmucru *pmucru) 1458 { 1459 u32 pclk_div; 1460 1461 /* configure pmu pll(ppll) */ 1462 rkclk_set_pll(&pmucru->ppll_con[0], &ppll_init_cfg); 1463 1464 /* configure pmu pclk */ 1465 pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1; 1466 rk_clrsetreg(&pmucru->pmucru_clksel[0], 1467 PMU_PCLK_DIV_CON_MASK, 1468 pclk_div << PMU_PCLK_DIV_CON_SHIFT); 1469 } 1470 #endif 1471 1472 static int rk3399_pmuclk_probe(struct udevice *dev) 1473 { 1474 #if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_SPL_BUILD) 1475 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); 1476 #endif 1477 1478 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1479 struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev); 1480 1481 priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); 1482 #endif 1483 1484 #ifndef CONFIG_SPL_BUILD 1485 pmuclk_init(priv->pmucru); 1486 #endif 1487 return 0; 1488 } 1489 1490 static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev) 1491 { 1492 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 1493 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); 1494 1495 priv->pmucru = dev_read_addr_ptr(dev); 1496 #endif 1497 return 0; 1498 } 1499 1500 static int rk3399_pmuclk_bind(struct udevice *dev) 1501 { 1502 int ret = 0; 1503 struct udevice *sf_child; 1504 struct softreset_reg *sf_priv; 1505 1506 ret = device_bind_driver_to_node(dev, "rockchip_reset", 1507 "reset", dev_ofnode(dev), 1508 &sf_child); 1509 if (ret) { 1510 debug("Warning: No rockchip reset driver: ret=%d\n", ret); 1511 } else { 1512 sf_priv = malloc(sizeof(struct softreset_reg)); 1513 sf_priv->sf_reset_offset = offsetof(struct rk3399_pmucru, 1514 pmucru_softrst_con[0]); 1515 sf_priv->sf_reset_num = 2; 1516 sf_child->priv = sf_priv; 1517 } 1518 1519 return 0; 1520 } 1521 1522 static const struct udevice_id rk3399_pmuclk_ids[] = { 1523 { .compatible = "rockchip,rk3399-pmucru" }, 1524 { } 1525 }; 1526 1527 U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = { 1528 .name = "rockchip_rk3399_pmucru", 1529 .id = UCLASS_CLK, 1530 .of_match = rk3399_pmuclk_ids, 1531 .priv_auto_alloc_size = sizeof(struct rk3399_pmuclk_priv), 1532 .ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata, 1533 .ops = &rk3399_pmuclk_ops, 1534 .probe = rk3399_pmuclk_probe, 1535 .bind = rk3399_pmuclk_bind, 1536 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1537 .platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat), 1538 #endif 1539 }; 1540