1 /* 2 * (C) Copyright 2015 Google, Inc 3 * (C) 2017 Theobroma Systems Design und Consulting GmbH 4 * 5 * SPDX-License-Identifier: GPL-2.0 6 */ 7 8 #include <common.h> 9 #include <clk-uclass.h> 10 #include <dm.h> 11 #include <dt-structs.h> 12 #include <errno.h> 13 #include <mapmem.h> 14 #include <syscon.h> 15 #include <asm/io.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/cru_rk3399.h> 18 #include <asm/arch/hardware.h> 19 #include <dm/lists.h> 20 #include <dt-bindings/clock/rk3399-cru.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 #if CONFIG_IS_ENABLED(OF_PLATDATA) 25 struct rk3399_clk_plat { 26 struct dtd_rockchip_rk3399_cru dtd; 27 }; 28 29 struct rk3399_pmuclk_plat { 30 struct dtd_rockchip_rk3399_pmucru dtd; 31 }; 32 #endif 33 34 struct pll_div { 35 u32 refdiv; 36 u32 fbdiv; 37 u32 postdiv1; 38 u32 postdiv2; 39 u32 frac; 40 }; 41 42 #define RATE_TO_DIV(input_rate, output_rate) \ 43 ((input_rate) / (output_rate) - 1); 44 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 45 46 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ 47 .refdiv = _refdiv,\ 48 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ 49 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2}; 50 51 #if defined(CONFIG_SPL_BUILD) 52 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); 53 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2); 54 #else 55 static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1); 56 #endif 57 58 static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1); 59 static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1); 60 61 static const struct pll_div *apll_l_cfgs[] = { 62 [APLL_L_1600_MHZ] = &apll_l_1600_cfg, 63 [APLL_L_600_MHZ] = &apll_l_600_cfg, 64 }; 65 66 enum { 67 /* PLL_CON0 */ 68 PLL_FBDIV_MASK = 0xfff, 69 PLL_FBDIV_SHIFT = 0, 70 71 /* PLL_CON1 */ 72 PLL_POSTDIV2_SHIFT = 12, 73 PLL_POSTDIV2_MASK = 0x7 << PLL_POSTDIV2_SHIFT, 74 PLL_POSTDIV1_SHIFT = 8, 75 PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT, 76 PLL_REFDIV_MASK = 0x3f, 77 PLL_REFDIV_SHIFT = 0, 78 79 /* PLL_CON2 */ 80 PLL_LOCK_STATUS_SHIFT = 31, 81 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, 82 PLL_FRACDIV_MASK = 0xffffff, 83 PLL_FRACDIV_SHIFT = 0, 84 85 /* PLL_CON3 */ 86 PLL_MODE_SHIFT = 8, 87 PLL_MODE_MASK = 3 << PLL_MODE_SHIFT, 88 PLL_MODE_SLOW = 0, 89 PLL_MODE_NORM, 90 PLL_MODE_DEEP, 91 PLL_DSMPD_SHIFT = 3, 92 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, 93 PLL_INTEGER_MODE = 1, 94 95 /* PMUCRU_CLKSEL_CON0 */ 96 PMU_PCLK_DIV_CON_MASK = 0x1f, 97 PMU_PCLK_DIV_CON_SHIFT = 0, 98 99 /* PMUCRU_CLKSEL_CON1 */ 100 SPI3_PLL_SEL_SHIFT = 7, 101 SPI3_PLL_SEL_MASK = 1 << SPI3_PLL_SEL_SHIFT, 102 SPI3_PLL_SEL_24M = 0, 103 SPI3_PLL_SEL_PPLL = 1, 104 SPI3_DIV_CON_SHIFT = 0x0, 105 SPI3_DIV_CON_MASK = 0x7f, 106 107 /* PMUCRU_CLKSEL_CON2 */ 108 I2C_DIV_CON_MASK = 0x7f, 109 CLK_I2C8_DIV_CON_SHIFT = 8, 110 CLK_I2C0_DIV_CON_SHIFT = 0, 111 112 /* PMUCRU_CLKSEL_CON3 */ 113 CLK_I2C4_DIV_CON_SHIFT = 0, 114 115 /* CLKSEL_CON0 */ 116 ACLKM_CORE_L_DIV_CON_SHIFT = 8, 117 ACLKM_CORE_L_DIV_CON_MASK = 0x1f << ACLKM_CORE_L_DIV_CON_SHIFT, 118 CLK_CORE_L_PLL_SEL_SHIFT = 6, 119 CLK_CORE_L_PLL_SEL_MASK = 3 << CLK_CORE_L_PLL_SEL_SHIFT, 120 CLK_CORE_L_PLL_SEL_ALPLL = 0x0, 121 CLK_CORE_L_PLL_SEL_ABPLL = 0x1, 122 CLK_CORE_L_PLL_SEL_DPLL = 0x10, 123 CLK_CORE_L_PLL_SEL_GPLL = 0x11, 124 CLK_CORE_L_DIV_MASK = 0x1f, 125 CLK_CORE_L_DIV_SHIFT = 0, 126 127 /* CLKSEL_CON1 */ 128 PCLK_DBG_L_DIV_SHIFT = 0x8, 129 PCLK_DBG_L_DIV_MASK = 0x1f << PCLK_DBG_L_DIV_SHIFT, 130 ATCLK_CORE_L_DIV_SHIFT = 0, 131 ATCLK_CORE_L_DIV_MASK = 0x1f << ATCLK_CORE_L_DIV_SHIFT, 132 133 /* CLKSEL_CON14 */ 134 PCLK_PERIHP_DIV_CON_SHIFT = 12, 135 PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT, 136 HCLK_PERIHP_DIV_CON_SHIFT = 8, 137 HCLK_PERIHP_DIV_CON_MASK = 3 << HCLK_PERIHP_DIV_CON_SHIFT, 138 ACLK_PERIHP_PLL_SEL_SHIFT = 7, 139 ACLK_PERIHP_PLL_SEL_MASK = 1 << ACLK_PERIHP_PLL_SEL_SHIFT, 140 ACLK_PERIHP_PLL_SEL_CPLL = 0, 141 ACLK_PERIHP_PLL_SEL_GPLL = 1, 142 ACLK_PERIHP_DIV_CON_SHIFT = 0, 143 ACLK_PERIHP_DIV_CON_MASK = 0x1f, 144 145 /* CLKSEL_CON21 */ 146 ACLK_EMMC_PLL_SEL_SHIFT = 7, 147 ACLK_EMMC_PLL_SEL_MASK = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT, 148 ACLK_EMMC_PLL_SEL_GPLL = 0x1, 149 ACLK_EMMC_DIV_CON_SHIFT = 0, 150 ACLK_EMMC_DIV_CON_MASK = 0x1f, 151 152 /* CLKSEL_CON22 */ 153 CLK_EMMC_PLL_SHIFT = 8, 154 CLK_EMMC_PLL_MASK = 0x7 << CLK_EMMC_PLL_SHIFT, 155 CLK_EMMC_PLL_SEL_GPLL = 0x1, 156 CLK_EMMC_PLL_SEL_24M = 0x5, 157 CLK_EMMC_DIV_CON_SHIFT = 0, 158 CLK_EMMC_DIV_CON_MASK = 0x7f << CLK_EMMC_DIV_CON_SHIFT, 159 160 /* CLKSEL_CON23 */ 161 PCLK_PERILP0_DIV_CON_SHIFT = 12, 162 PCLK_PERILP0_DIV_CON_MASK = 0x7 << PCLK_PERILP0_DIV_CON_SHIFT, 163 HCLK_PERILP0_DIV_CON_SHIFT = 8, 164 HCLK_PERILP0_DIV_CON_MASK = 3 << HCLK_PERILP0_DIV_CON_SHIFT, 165 ACLK_PERILP0_PLL_SEL_SHIFT = 7, 166 ACLK_PERILP0_PLL_SEL_MASK = 1 << ACLK_PERILP0_PLL_SEL_SHIFT, 167 ACLK_PERILP0_PLL_SEL_CPLL = 0, 168 ACLK_PERILP0_PLL_SEL_GPLL = 1, 169 ACLK_PERILP0_DIV_CON_SHIFT = 0, 170 ACLK_PERILP0_DIV_CON_MASK = 0x1f, 171 172 /* CLKSEL_CON25 */ 173 PCLK_PERILP1_DIV_CON_SHIFT = 8, 174 PCLK_PERILP1_DIV_CON_MASK = 0x7 << PCLK_PERILP1_DIV_CON_SHIFT, 175 HCLK_PERILP1_PLL_SEL_SHIFT = 7, 176 HCLK_PERILP1_PLL_SEL_MASK = 1 << HCLK_PERILP1_PLL_SEL_SHIFT, 177 HCLK_PERILP1_PLL_SEL_CPLL = 0, 178 HCLK_PERILP1_PLL_SEL_GPLL = 1, 179 HCLK_PERILP1_DIV_CON_SHIFT = 0, 180 HCLK_PERILP1_DIV_CON_MASK = 0x1f, 181 182 /* CLKSEL_CON26 */ 183 CLK_SARADC_DIV_CON_SHIFT = 8, 184 CLK_SARADC_DIV_CON_MASK = 0xff << CLK_SARADC_DIV_CON_SHIFT, 185 186 /* CLKSEL_CON27 */ 187 CLK_TSADC_SEL_X24M = 0x0, 188 CLK_TSADC_SEL_SHIFT = 15, 189 CLK_TSADC_SEL_MASK = 1 << CLK_TSADC_SEL_SHIFT, 190 CLK_TSADC_DIV_CON_SHIFT = 0, 191 CLK_TSADC_DIV_CON_MASK = 0x3ff, 192 193 /* CLKSEL_CON47 & CLKSEL_CON48 */ 194 ACLK_VOP_PLL_SEL_SHIFT = 6, 195 ACLK_VOP_PLL_SEL_MASK = 0x3 << ACLK_VOP_PLL_SEL_SHIFT, 196 ACLK_VOP_PLL_SEL_CPLL = 0x1, 197 ACLK_VOP_DIV_CON_SHIFT = 0, 198 ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT, 199 200 /* CLKSEL_CON49 & CLKSEL_CON50 */ 201 DCLK_VOP_DCLK_SEL_SHIFT = 11, 202 DCLK_VOP_DCLK_SEL_MASK = 1 << DCLK_VOP_DCLK_SEL_SHIFT, 203 DCLK_VOP_DCLK_SEL_DIVOUT = 0, 204 DCLK_VOP_PLL_SEL_SHIFT = 8, 205 DCLK_VOP_PLL_SEL_MASK = 3 << DCLK_VOP_PLL_SEL_SHIFT, 206 DCLK_VOP_PLL_SEL_VPLL = 0, 207 DCLK_VOP_DIV_CON_MASK = 0xff, 208 DCLK_VOP_DIV_CON_SHIFT = 0, 209 210 /* CLKSEL_CON58 */ 211 CLK_SPI_PLL_SEL_WIDTH = 1, 212 CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1), 213 CLK_SPI_PLL_SEL_CPLL = 0, 214 CLK_SPI_PLL_SEL_GPLL = 1, 215 CLK_SPI_PLL_DIV_CON_WIDTH = 7, 216 CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1), 217 218 CLK_SPI5_PLL_DIV_CON_SHIFT = 8, 219 CLK_SPI5_PLL_SEL_SHIFT = 15, 220 221 /* CLKSEL_CON59 */ 222 CLK_SPI1_PLL_SEL_SHIFT = 15, 223 CLK_SPI1_PLL_DIV_CON_SHIFT = 8, 224 CLK_SPI0_PLL_SEL_SHIFT = 7, 225 CLK_SPI0_PLL_DIV_CON_SHIFT = 0, 226 227 /* CLKSEL_CON60 */ 228 CLK_SPI4_PLL_SEL_SHIFT = 15, 229 CLK_SPI4_PLL_DIV_CON_SHIFT = 8, 230 CLK_SPI2_PLL_SEL_SHIFT = 7, 231 CLK_SPI2_PLL_DIV_CON_SHIFT = 0, 232 233 /* CLKSEL_CON61 */ 234 CLK_I2C_PLL_SEL_MASK = 1, 235 CLK_I2C_PLL_SEL_CPLL = 0, 236 CLK_I2C_PLL_SEL_GPLL = 1, 237 CLK_I2C5_PLL_SEL_SHIFT = 15, 238 CLK_I2C5_DIV_CON_SHIFT = 8, 239 CLK_I2C1_PLL_SEL_SHIFT = 7, 240 CLK_I2C1_DIV_CON_SHIFT = 0, 241 242 /* CLKSEL_CON62 */ 243 CLK_I2C6_PLL_SEL_SHIFT = 15, 244 CLK_I2C6_DIV_CON_SHIFT = 8, 245 CLK_I2C2_PLL_SEL_SHIFT = 7, 246 CLK_I2C2_DIV_CON_SHIFT = 0, 247 248 /* CLKSEL_CON63 */ 249 CLK_I2C7_PLL_SEL_SHIFT = 15, 250 CLK_I2C7_DIV_CON_SHIFT = 8, 251 CLK_I2C3_PLL_SEL_SHIFT = 7, 252 CLK_I2C3_DIV_CON_SHIFT = 0, 253 254 /* CRU_SOFTRST_CON4 */ 255 RESETN_DDR0_REQ_SHIFT = 8, 256 RESETN_DDR0_REQ_MASK = 1 << RESETN_DDR0_REQ_SHIFT, 257 RESETN_DDRPHY0_REQ_SHIFT = 9, 258 RESETN_DDRPHY0_REQ_MASK = 1 << RESETN_DDRPHY0_REQ_SHIFT, 259 RESETN_DDR1_REQ_SHIFT = 12, 260 RESETN_DDR1_REQ_MASK = 1 << RESETN_DDR1_REQ_SHIFT, 261 RESETN_DDRPHY1_REQ_SHIFT = 13, 262 RESETN_DDRPHY1_REQ_MASK = 1 << RESETN_DDRPHY1_REQ_SHIFT, 263 }; 264 265 #define VCO_MAX_KHZ (3200 * (MHz / KHz)) 266 #define VCO_MIN_KHZ (800 * (MHz / KHz)) 267 #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz)) 268 #define OUTPUT_MIN_KHZ (16 * (MHz / KHz)) 269 270 /* 271 * the div restructions of pll in integer mode, these are defined in 272 * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0 273 */ 274 #define PLL_DIV_MIN 16 275 #define PLL_DIV_MAX 3200 276 277 /* 278 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63): 279 * Formulas also embedded within the Fractional PLL Verilog model: 280 * If DSMPD = 1 (DSM is disabled, "integer mode") 281 * FOUTVCO = FREF / REFDIV * FBDIV 282 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 283 * Where: 284 * FOUTVCO = Fractional PLL non-divided output frequency 285 * FOUTPOSTDIV = Fractional PLL divided output frequency 286 * (output of second post divider) 287 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input) 288 * REFDIV = Fractional PLL input reference clock divider 289 * FBDIV = Integer value programmed into feedback divide 290 * 291 */ 292 static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div) 293 { 294 /* All 8 PLLs have same VCO and output frequency range restrictions. */ 295 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; 296 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; 297 298 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, " 299 "postdiv2=%d, vco=%u khz, output=%u khz\n", 300 pll_con, div->fbdiv, div->refdiv, div->postdiv1, 301 div->postdiv2, vco_khz, output_khz); 302 assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ && 303 output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ && 304 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); 305 306 /* 307 * When power on or changing PLL setting, 308 * we must force PLL into slow mode to ensure output stable clock. 309 */ 310 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, 311 PLL_MODE_SLOW << PLL_MODE_SHIFT); 312 313 /* use integer mode */ 314 rk_clrsetreg(&pll_con[3], PLL_DSMPD_MASK, 315 PLL_INTEGER_MODE << PLL_DSMPD_SHIFT); 316 317 rk_clrsetreg(&pll_con[0], PLL_FBDIV_MASK, 318 div->fbdiv << PLL_FBDIV_SHIFT); 319 rk_clrsetreg(&pll_con[1], 320 PLL_POSTDIV2_MASK | PLL_POSTDIV1_MASK | 321 PLL_REFDIV_MASK | PLL_REFDIV_SHIFT, 322 (div->postdiv2 << PLL_POSTDIV2_SHIFT) | 323 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | 324 (div->refdiv << PLL_REFDIV_SHIFT)); 325 326 /* waiting for pll lock */ 327 while (!(readl(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT))) 328 udelay(1); 329 330 /* pll enter normal mode */ 331 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, 332 PLL_MODE_NORM << PLL_MODE_SHIFT); 333 } 334 335 static int pll_para_config(u32 freq_hz, struct pll_div *div) 336 { 337 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; 338 u32 postdiv1, postdiv2 = 1; 339 u32 fref_khz; 340 u32 diff_khz, best_diff_khz; 341 const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16; 342 const u32 max_postdiv1 = 7, max_postdiv2 = 7; 343 u32 vco_khz; 344 u32 freq_khz = freq_hz / KHz; 345 346 if (!freq_hz) { 347 printf("%s: the frequency can't be 0 Hz\n", __func__); 348 return -1; 349 } 350 351 postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz); 352 if (postdiv1 > max_postdiv1) { 353 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); 354 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); 355 } 356 357 vco_khz = freq_khz * postdiv1 * postdiv2; 358 359 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || 360 postdiv2 > max_postdiv2) { 361 printf("%s: Cannot find out a supported VCO" 362 " for Frequency (%uHz).\n", __func__, freq_hz); 363 return -1; 364 } 365 366 div->postdiv1 = postdiv1; 367 div->postdiv2 = postdiv2; 368 369 best_diff_khz = vco_khz; 370 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { 371 fref_khz = ref_khz / refdiv; 372 373 fbdiv = vco_khz / fref_khz; 374 if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv)) 375 continue; 376 diff_khz = vco_khz - fbdiv * fref_khz; 377 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) { 378 fbdiv++; 379 diff_khz = fref_khz - diff_khz; 380 } 381 382 if (diff_khz >= best_diff_khz) 383 continue; 384 385 best_diff_khz = diff_khz; 386 div->refdiv = refdiv; 387 div->fbdiv = fbdiv; 388 } 389 390 if (best_diff_khz > 4 * (MHz/KHz)) { 391 printf("%s: Failed to match output frequency %u, " 392 "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz, 393 best_diff_khz * KHz); 394 return -1; 395 } 396 return 0; 397 } 398 399 #ifdef CONFIG_SPL_BUILD 400 static void rkclk_init(struct rk3399_cru *cru) 401 { 402 u32 aclk_div; 403 u32 hclk_div; 404 u32 pclk_div; 405 406 rk3399_configure_cpu(cru, APLL_L_600_MHZ); 407 /* 408 * some cru registers changed by bootrom, we'd better reset them to 409 * reset/default values described in TRM to avoid confusion in kernel. 410 * Please consider these three lines as a fix of bootrom bug. 411 */ 412 rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101); 413 rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f); 414 rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003); 415 416 /* configure gpll cpll */ 417 rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg); 418 rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg); 419 420 /* configure perihp aclk, hclk, pclk */ 421 aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1; 422 assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); 423 424 hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1; 425 assert((hclk_div + 1) * PERIHP_HCLK_HZ == 426 PERIHP_ACLK_HZ && (hclk_div < 0x4)); 427 428 pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1; 429 assert((pclk_div + 1) * PERIHP_PCLK_HZ == 430 PERIHP_ACLK_HZ && (pclk_div < 0x7)); 431 432 rk_clrsetreg(&cru->clksel_con[14], 433 PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK | 434 ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK, 435 pclk_div << PCLK_PERIHP_DIV_CON_SHIFT | 436 hclk_div << HCLK_PERIHP_DIV_CON_SHIFT | 437 ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT | 438 aclk_div << ACLK_PERIHP_DIV_CON_SHIFT); 439 440 /* configure perilp0 aclk, hclk, pclk */ 441 aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1; 442 assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); 443 444 hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1; 445 assert((hclk_div + 1) * PERILP0_HCLK_HZ == 446 PERILP0_ACLK_HZ && (hclk_div < 0x4)); 447 448 pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1; 449 assert((pclk_div + 1) * PERILP0_PCLK_HZ == 450 PERILP0_ACLK_HZ && (pclk_div < 0x7)); 451 452 rk_clrsetreg(&cru->clksel_con[23], 453 PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK | 454 ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK, 455 pclk_div << PCLK_PERILP0_DIV_CON_SHIFT | 456 hclk_div << HCLK_PERILP0_DIV_CON_SHIFT | 457 ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT | 458 aclk_div << ACLK_PERILP0_DIV_CON_SHIFT); 459 460 /* perilp1 hclk select gpll as source */ 461 hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1; 462 assert((hclk_div + 1) * PERILP1_HCLK_HZ == 463 GPLL_HZ && (hclk_div < 0x1f)); 464 465 pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1; 466 assert((pclk_div + 1) * PERILP1_HCLK_HZ == 467 PERILP1_HCLK_HZ && (hclk_div < 0x7)); 468 469 rk_clrsetreg(&cru->clksel_con[25], 470 PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK | 471 HCLK_PERILP1_PLL_SEL_MASK, 472 pclk_div << PCLK_PERILP1_DIV_CON_SHIFT | 473 hclk_div << HCLK_PERILP1_DIV_CON_SHIFT | 474 HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT); 475 } 476 #endif 477 478 void rk3399_configure_cpu(struct rk3399_cru *cru, 479 enum apll_l_frequencies apll_l_freq) 480 { 481 u32 aclkm_div; 482 u32 pclk_dbg_div; 483 u32 atclk_div; 484 485 rkclk_set_pll(&cru->apll_l_con[0], apll_l_cfgs[apll_l_freq]); 486 487 aclkm_div = APLL_HZ / ACLKM_CORE_HZ - 1; 488 assert((aclkm_div + 1) * ACLKM_CORE_HZ == APLL_HZ && 489 aclkm_div < 0x1f); 490 491 pclk_dbg_div = APLL_HZ / PCLK_DBG_HZ - 1; 492 assert((pclk_dbg_div + 1) * PCLK_DBG_HZ == APLL_HZ && 493 pclk_dbg_div < 0x1f); 494 495 atclk_div = APLL_HZ / ATCLK_CORE_HZ - 1; 496 assert((atclk_div + 1) * ATCLK_CORE_HZ == APLL_HZ && 497 atclk_div < 0x1f); 498 499 rk_clrsetreg(&cru->clksel_con[0], 500 ACLKM_CORE_L_DIV_CON_MASK | CLK_CORE_L_PLL_SEL_MASK | 501 CLK_CORE_L_DIV_MASK, 502 aclkm_div << ACLKM_CORE_L_DIV_CON_SHIFT | 503 CLK_CORE_L_PLL_SEL_ALPLL << CLK_CORE_L_PLL_SEL_SHIFT | 504 0 << CLK_CORE_L_DIV_SHIFT); 505 506 rk_clrsetreg(&cru->clksel_con[1], 507 PCLK_DBG_L_DIV_MASK | ATCLK_CORE_L_DIV_MASK, 508 pclk_dbg_div << PCLK_DBG_L_DIV_SHIFT | 509 atclk_div << ATCLK_CORE_L_DIV_SHIFT); 510 } 511 #define I2C_CLK_REG_MASK(bus) \ 512 (I2C_DIV_CON_MASK << \ 513 CLK_I2C ##bus## _DIV_CON_SHIFT | \ 514 CLK_I2C_PLL_SEL_MASK << \ 515 CLK_I2C ##bus## _PLL_SEL_SHIFT) 516 517 #define I2C_CLK_REG_VALUE(bus, clk_div) \ 518 ((clk_div - 1) << \ 519 CLK_I2C ##bus## _DIV_CON_SHIFT | \ 520 CLK_I2C_PLL_SEL_GPLL << \ 521 CLK_I2C ##bus## _PLL_SEL_SHIFT) 522 523 #define I2C_CLK_DIV_VALUE(con, bus) \ 524 (con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \ 525 I2C_DIV_CON_MASK; 526 527 #define I2C_PMUCLK_REG_MASK(bus) \ 528 (I2C_DIV_CON_MASK << \ 529 CLK_I2C ##bus## _DIV_CON_SHIFT) 530 531 #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \ 532 ((clk_div - 1) << \ 533 CLK_I2C ##bus## _DIV_CON_SHIFT) 534 535 static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id) 536 { 537 u32 div, con; 538 539 switch (clk_id) { 540 case SCLK_I2C1: 541 con = readl(&cru->clksel_con[61]); 542 div = I2C_CLK_DIV_VALUE(con, 1); 543 break; 544 case SCLK_I2C2: 545 con = readl(&cru->clksel_con[62]); 546 div = I2C_CLK_DIV_VALUE(con, 2); 547 break; 548 case SCLK_I2C3: 549 con = readl(&cru->clksel_con[63]); 550 div = I2C_CLK_DIV_VALUE(con, 3); 551 break; 552 case SCLK_I2C5: 553 con = readl(&cru->clksel_con[61]); 554 div = I2C_CLK_DIV_VALUE(con, 5); 555 break; 556 case SCLK_I2C6: 557 con = readl(&cru->clksel_con[62]); 558 div = I2C_CLK_DIV_VALUE(con, 6); 559 break; 560 case SCLK_I2C7: 561 con = readl(&cru->clksel_con[63]); 562 div = I2C_CLK_DIV_VALUE(con, 7); 563 break; 564 default: 565 printf("do not support this i2c bus\n"); 566 return -EINVAL; 567 } 568 569 return DIV_TO_RATE(GPLL_HZ, div); 570 } 571 572 static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) 573 { 574 int src_clk_div; 575 576 /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/ 577 src_clk_div = GPLL_HZ / hz; 578 assert(src_clk_div - 1 < 127); 579 580 switch (clk_id) { 581 case SCLK_I2C1: 582 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(1), 583 I2C_CLK_REG_VALUE(1, src_clk_div)); 584 break; 585 case SCLK_I2C2: 586 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(2), 587 I2C_CLK_REG_VALUE(2, src_clk_div)); 588 break; 589 case SCLK_I2C3: 590 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(3), 591 I2C_CLK_REG_VALUE(3, src_clk_div)); 592 break; 593 case SCLK_I2C5: 594 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(5), 595 I2C_CLK_REG_VALUE(5, src_clk_div)); 596 break; 597 case SCLK_I2C6: 598 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(6), 599 I2C_CLK_REG_VALUE(6, src_clk_div)); 600 break; 601 case SCLK_I2C7: 602 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(7), 603 I2C_CLK_REG_VALUE(7, src_clk_div)); 604 break; 605 default: 606 printf("do not support this i2c bus\n"); 607 return -EINVAL; 608 } 609 610 return rk3399_i2c_get_clk(cru, clk_id); 611 } 612 613 /* 614 * RK3399 SPI clocks have a common divider-width (7 bits) and a single bit 615 * to select either CPLL or GPLL as the clock-parent. The location within 616 * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable. 617 */ 618 619 struct spi_clkreg { 620 uint8_t reg; /* CLKSEL_CON[reg] register in CRU */ 621 uint8_t div_shift; 622 uint8_t sel_shift; 623 }; 624 625 /* 626 * The entries are numbered relative to their offset from SCLK_SPI0. 627 * 628 * Note that SCLK_SPI3 (which is configured via PMUCRU and requires different 629 * logic is not supported). 630 */ 631 static const struct spi_clkreg spi_clkregs[] = { 632 [0] = { .reg = 59, 633 .div_shift = CLK_SPI0_PLL_DIV_CON_SHIFT, 634 .sel_shift = CLK_SPI0_PLL_SEL_SHIFT, }, 635 [1] = { .reg = 59, 636 .div_shift = CLK_SPI1_PLL_DIV_CON_SHIFT, 637 .sel_shift = CLK_SPI1_PLL_SEL_SHIFT, }, 638 [2] = { .reg = 60, 639 .div_shift = CLK_SPI2_PLL_DIV_CON_SHIFT, 640 .sel_shift = CLK_SPI2_PLL_SEL_SHIFT, }, 641 [3] = { .reg = 60, 642 .div_shift = CLK_SPI4_PLL_DIV_CON_SHIFT, 643 .sel_shift = CLK_SPI4_PLL_SEL_SHIFT, }, 644 [4] = { .reg = 58, 645 .div_shift = CLK_SPI5_PLL_DIV_CON_SHIFT, 646 .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, }, 647 }; 648 649 static inline u32 extract_bits(u32 val, unsigned width, unsigned shift) 650 { 651 return (val >> shift) & ((1 << width) - 1); 652 } 653 654 static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id) 655 { 656 const struct spi_clkreg *spiclk = NULL; 657 u32 div, val; 658 659 switch (clk_id) { 660 case SCLK_SPI0 ... SCLK_SPI5: 661 spiclk = &spi_clkregs[clk_id - SCLK_SPI0]; 662 break; 663 664 default: 665 error("%s: SPI clk-id %ld not supported\n", __func__, clk_id); 666 return -EINVAL; 667 } 668 669 val = readl(&cru->clksel_con[spiclk->reg]); 670 div = extract_bits(val, CLK_SPI_PLL_DIV_CON_WIDTH, spiclk->div_shift); 671 672 return DIV_TO_RATE(GPLL_HZ, div); 673 } 674 675 static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) 676 { 677 const struct spi_clkreg *spiclk = NULL; 678 int src_clk_div; 679 680 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; 681 assert(src_clk_div < 128); 682 683 switch (clk_id) { 684 case SCLK_SPI1 ... SCLK_SPI5: 685 spiclk = &spi_clkregs[clk_id - SCLK_SPI0]; 686 break; 687 688 default: 689 error("%s: SPI clk-id %ld not supported\n", __func__, clk_id); 690 return -EINVAL; 691 } 692 693 rk_clrsetreg(&cru->clksel_con[spiclk->reg], 694 ((CLK_SPI_PLL_DIV_CON_MASK << spiclk->div_shift) | 695 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)), 696 ((src_clk_div << spiclk->div_shift) | 697 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift))); 698 699 return rk3399_spi_get_clk(cru, clk_id); 700 } 701 702 static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz) 703 { 704 struct pll_div vpll_config = {0}; 705 int aclk_vop = 198*MHz; 706 void *aclkreg_addr, *dclkreg_addr; 707 u32 div; 708 709 switch (clk_id) { 710 case DCLK_VOP0: 711 aclkreg_addr = &cru->clksel_con[47]; 712 dclkreg_addr = &cru->clksel_con[49]; 713 break; 714 case DCLK_VOP1: 715 aclkreg_addr = &cru->clksel_con[48]; 716 dclkreg_addr = &cru->clksel_con[50]; 717 break; 718 default: 719 return -EINVAL; 720 } 721 /* vop aclk source clk: cpll */ 722 div = CPLL_HZ / aclk_vop; 723 assert(div - 1 < 32); 724 725 rk_clrsetreg(aclkreg_addr, 726 ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK, 727 ACLK_VOP_PLL_SEL_CPLL << ACLK_VOP_PLL_SEL_SHIFT | 728 (div - 1) << ACLK_VOP_DIV_CON_SHIFT); 729 730 /* vop dclk source from vpll, and equals to vpll(means div == 1) */ 731 if (pll_para_config(hz, &vpll_config)) 732 return -1; 733 734 rkclk_set_pll(&cru->vpll_con[0], &vpll_config); 735 736 rk_clrsetreg(dclkreg_addr, 737 DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_PLL_SEL_MASK| 738 DCLK_VOP_DIV_CON_MASK, 739 DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT | 740 DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT | 741 (1 - 1) << DCLK_VOP_DIV_CON_SHIFT); 742 743 return hz; 744 } 745 746 static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id) 747 { 748 u32 div, con; 749 750 switch (clk_id) { 751 case HCLK_SDMMC: 752 case SCLK_SDMMC: 753 con = readl(&cru->clksel_con[16]); 754 /* dwmmc controller have internal div 2 */ 755 div = 2; 756 break; 757 case SCLK_EMMC: 758 con = readl(&cru->clksel_con[21]); 759 div = 1; 760 break; 761 default: 762 return -EINVAL; 763 } 764 765 div *= (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT; 766 if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT 767 == CLK_EMMC_PLL_SEL_24M) 768 return DIV_TO_RATE(OSC_HZ, div); 769 else 770 return DIV_TO_RATE(GPLL_HZ, div); 771 } 772 773 static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru, 774 ulong clk_id, ulong set_rate) 775 { 776 int src_clk_div; 777 int aclk_emmc = 198*MHz; 778 779 switch (clk_id) { 780 case HCLK_SDMMC: 781 case SCLK_SDMMC: 782 /* Select clk_sdmmc source from GPLL by default */ 783 /* mmc clock defaulg div 2 internal, provide double in cru */ 784 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate); 785 786 if (src_clk_div > 128) { 787 /* use 24MHz source for 400KHz clock */ 788 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); 789 assert(src_clk_div - 1 < 128); 790 rk_clrsetreg(&cru->clksel_con[16], 791 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 792 CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT | 793 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 794 } else { 795 rk_clrsetreg(&cru->clksel_con[16], 796 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 797 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | 798 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 799 } 800 break; 801 case SCLK_EMMC: 802 /* Select aclk_emmc source from GPLL */ 803 src_clk_div = DIV_ROUND_UP(GPLL_HZ , aclk_emmc); 804 assert(src_clk_div - 1 < 32); 805 806 rk_clrsetreg(&cru->clksel_con[21], 807 ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK, 808 ACLK_EMMC_PLL_SEL_GPLL << ACLK_EMMC_PLL_SEL_SHIFT | 809 (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT); 810 811 /* Select clk_emmc source from GPLL too */ 812 src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate); 813 assert(src_clk_div - 1 < 128); 814 815 rk_clrsetreg(&cru->clksel_con[22], 816 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 817 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | 818 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 819 break; 820 default: 821 return -EINVAL; 822 } 823 return rk3399_mmc_get_clk(cru, clk_id); 824 } 825 826 #define PMUSGRF_DDR_RGN_CON16 0xff330040 827 static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru, 828 ulong set_rate) 829 { 830 struct pll_div dpll_cfg; 831 832 /* IC ECO bug, need to set this register */ 833 writel(0xc000c000, PMUSGRF_DDR_RGN_CON16); 834 835 /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */ 836 switch (set_rate) { 837 case 200*MHz: 838 dpll_cfg = (struct pll_div) 839 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1}; 840 break; 841 case 300*MHz: 842 dpll_cfg = (struct pll_div) 843 {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1}; 844 break; 845 case 666*MHz: 846 dpll_cfg = (struct pll_div) 847 {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1}; 848 break; 849 case 800*MHz: 850 dpll_cfg = (struct pll_div) 851 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}; 852 break; 853 case 933*MHz: 854 dpll_cfg = (struct pll_div) 855 {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1}; 856 break; 857 default: 858 error("Unsupported SDRAM frequency!,%ld\n", set_rate); 859 } 860 rkclk_set_pll(&cru->dpll_con[0], &dpll_cfg); 861 862 return set_rate; 863 } 864 static ulong rk3399_clk_get_rate(struct clk *clk) 865 { 866 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 867 ulong rate = 0; 868 869 switch (clk->id) { 870 case 0 ... 63: 871 return 0; 872 case HCLK_SDMMC: 873 case SCLK_SDMMC: 874 case SCLK_EMMC: 875 rate = rk3399_mmc_get_clk(priv->cru, clk->id); 876 break; 877 case SCLK_I2C1: 878 case SCLK_I2C2: 879 case SCLK_I2C3: 880 case SCLK_I2C5: 881 case SCLK_I2C6: 882 case SCLK_I2C7: 883 rate = rk3399_i2c_get_clk(priv->cru, clk->id); 884 break; 885 case SCLK_SPI0...SCLK_SPI5: 886 rate = rk3399_spi_get_clk(priv->cru, clk->id); 887 break; 888 case SCLK_UART0: 889 case SCLK_UART2: 890 return 24000000; 891 break; 892 case PCLK_HDMI_CTRL: 893 break; 894 case DCLK_VOP0: 895 case DCLK_VOP1: 896 break; 897 case PCLK_EFUSE1024NS: 898 break; 899 default: 900 return -ENOENT; 901 } 902 903 return rate; 904 } 905 906 static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) 907 { 908 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 909 ulong ret = 0; 910 911 switch (clk->id) { 912 case 0 ... 63: 913 return 0; 914 case HCLK_SDMMC: 915 case SCLK_SDMMC: 916 case SCLK_EMMC: 917 ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate); 918 break; 919 case SCLK_MAC: 920 /* nothing to do, as this is an external clock */ 921 ret = rate; 922 break; 923 case SCLK_I2C1: 924 case SCLK_I2C2: 925 case SCLK_I2C3: 926 case SCLK_I2C5: 927 case SCLK_I2C6: 928 case SCLK_I2C7: 929 ret = rk3399_i2c_set_clk(priv->cru, clk->id, rate); 930 break; 931 case SCLK_SPI0...SCLK_SPI5: 932 ret = rk3399_spi_set_clk(priv->cru, clk->id, rate); 933 break; 934 case PCLK_HDMI_CTRL: 935 case PCLK_VIO_GRF: 936 /* the PCLK gates for video are enabled by default */ 937 break; 938 case DCLK_VOP0: 939 case DCLK_VOP1: 940 ret = rk3399_vop_set_clk(priv->cru, clk->id, rate); 941 break; 942 case SCLK_DDRCLK: 943 ret = rk3399_ddr_set_clk(priv->cru, rate); 944 break; 945 case PCLK_EFUSE1024NS: 946 break; 947 default: 948 return -ENOENT; 949 } 950 951 return ret; 952 } 953 954 static struct clk_ops rk3399_clk_ops = { 955 .get_rate = rk3399_clk_get_rate, 956 .set_rate = rk3399_clk_set_rate, 957 }; 958 959 static int rk3399_clk_probe(struct udevice *dev) 960 { 961 #ifdef CONFIG_SPL_BUILD 962 struct rk3399_clk_priv *priv = dev_get_priv(dev); 963 964 #if CONFIG_IS_ENABLED(OF_PLATDATA) 965 struct rk3399_clk_plat *plat = dev_get_platdata(dev); 966 967 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); 968 #endif 969 rkclk_init(priv->cru); 970 #endif 971 return 0; 972 } 973 974 static int rk3399_clk_ofdata_to_platdata(struct udevice *dev) 975 { 976 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 977 struct rk3399_clk_priv *priv = dev_get_priv(dev); 978 979 priv->cru = (struct rk3399_cru *)devfdt_get_addr(dev); 980 #endif 981 return 0; 982 } 983 984 static int rk3399_clk_bind(struct udevice *dev) 985 { 986 int ret; 987 988 /* The reset driver does not have a device node, so bind it here */ 989 ret = device_bind_driver(gd->dm_root, "rk3399_sysreset", "reset", &dev); 990 if (ret) 991 printf("Warning: No RK3399 reset driver: ret=%d\n", ret); 992 993 return 0; 994 } 995 996 static const struct udevice_id rk3399_clk_ids[] = { 997 { .compatible = "rockchip,rk3399-cru" }, 998 { } 999 }; 1000 1001 U_BOOT_DRIVER(clk_rk3399) = { 1002 .name = "rockchip_rk3399_cru", 1003 .id = UCLASS_CLK, 1004 .of_match = rk3399_clk_ids, 1005 .priv_auto_alloc_size = sizeof(struct rk3399_clk_priv), 1006 .ofdata_to_platdata = rk3399_clk_ofdata_to_platdata, 1007 .ops = &rk3399_clk_ops, 1008 .bind = rk3399_clk_bind, 1009 .probe = rk3399_clk_probe, 1010 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1011 .platdata_auto_alloc_size = sizeof(struct rk3399_clk_plat), 1012 #endif 1013 }; 1014 1015 static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id) 1016 { 1017 u32 div, con; 1018 1019 switch (clk_id) { 1020 case SCLK_I2C0_PMU: 1021 con = readl(&pmucru->pmucru_clksel[2]); 1022 div = I2C_CLK_DIV_VALUE(con, 0); 1023 break; 1024 case SCLK_I2C4_PMU: 1025 con = readl(&pmucru->pmucru_clksel[3]); 1026 div = I2C_CLK_DIV_VALUE(con, 4); 1027 break; 1028 case SCLK_I2C8_PMU: 1029 con = readl(&pmucru->pmucru_clksel[2]); 1030 div = I2C_CLK_DIV_VALUE(con, 8); 1031 break; 1032 default: 1033 printf("do not support this i2c bus\n"); 1034 return -EINVAL; 1035 } 1036 1037 return DIV_TO_RATE(PPLL_HZ, div); 1038 } 1039 1040 static ulong rk3399_i2c_set_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id, 1041 uint hz) 1042 { 1043 int src_clk_div; 1044 1045 src_clk_div = PPLL_HZ / hz; 1046 assert(src_clk_div - 1 < 127); 1047 1048 switch (clk_id) { 1049 case SCLK_I2C0_PMU: 1050 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(0), 1051 I2C_PMUCLK_REG_VALUE(0, src_clk_div)); 1052 break; 1053 case SCLK_I2C4_PMU: 1054 rk_clrsetreg(&pmucru->pmucru_clksel[3], I2C_PMUCLK_REG_MASK(4), 1055 I2C_PMUCLK_REG_VALUE(4, src_clk_div)); 1056 break; 1057 case SCLK_I2C8_PMU: 1058 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(8), 1059 I2C_PMUCLK_REG_VALUE(8, src_clk_div)); 1060 break; 1061 default: 1062 printf("do not support this i2c bus\n"); 1063 return -EINVAL; 1064 } 1065 1066 return DIV_TO_RATE(PPLL_HZ, src_clk_div); 1067 } 1068 1069 static ulong rk3399_pwm_get_clk(struct rk3399_pmucru *pmucru) 1070 { 1071 u32 div, con; 1072 1073 /* PWM closk rate is same as pclk_pmu */ 1074 con = readl(&pmucru->pmucru_clksel[0]); 1075 div = con & PMU_PCLK_DIV_CON_MASK; 1076 1077 return DIV_TO_RATE(PPLL_HZ, div); 1078 } 1079 1080 static ulong rk3399_pmuclk_get_rate(struct clk *clk) 1081 { 1082 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev); 1083 ulong rate = 0; 1084 1085 switch (clk->id) { 1086 case PCLK_RKPWM_PMU: 1087 rate = rk3399_pwm_get_clk(priv->pmucru); 1088 break; 1089 case SCLK_I2C0_PMU: 1090 case SCLK_I2C4_PMU: 1091 case SCLK_I2C8_PMU: 1092 rate = rk3399_i2c_get_pmuclk(priv->pmucru, clk->id); 1093 break; 1094 default: 1095 return -ENOENT; 1096 } 1097 1098 return rate; 1099 } 1100 1101 static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate) 1102 { 1103 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev); 1104 ulong ret = 0; 1105 1106 switch (clk->id) { 1107 case SCLK_I2C0_PMU: 1108 case SCLK_I2C4_PMU: 1109 case SCLK_I2C8_PMU: 1110 ret = rk3399_i2c_set_pmuclk(priv->pmucru, clk->id, rate); 1111 break; 1112 default: 1113 return -ENOENT; 1114 } 1115 1116 return ret; 1117 } 1118 1119 static struct clk_ops rk3399_pmuclk_ops = { 1120 .get_rate = rk3399_pmuclk_get_rate, 1121 .set_rate = rk3399_pmuclk_set_rate, 1122 }; 1123 1124 #ifndef CONFIG_SPL_BUILD 1125 static void pmuclk_init(struct rk3399_pmucru *pmucru) 1126 { 1127 u32 pclk_div; 1128 1129 /* configure pmu pll(ppll) */ 1130 rkclk_set_pll(&pmucru->ppll_con[0], &ppll_init_cfg); 1131 1132 /* configure pmu pclk */ 1133 pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1; 1134 rk_clrsetreg(&pmucru->pmucru_clksel[0], 1135 PMU_PCLK_DIV_CON_MASK, 1136 pclk_div << PMU_PCLK_DIV_CON_SHIFT); 1137 } 1138 #endif 1139 1140 static int rk3399_pmuclk_probe(struct udevice *dev) 1141 { 1142 #if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_SPL_BUILD) 1143 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); 1144 #endif 1145 1146 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1147 struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev); 1148 1149 priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); 1150 #endif 1151 1152 #ifndef CONFIG_SPL_BUILD 1153 pmuclk_init(priv->pmucru); 1154 #endif 1155 return 0; 1156 } 1157 1158 static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev) 1159 { 1160 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 1161 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); 1162 1163 priv->pmucru = (struct rk3399_pmucru *)devfdt_get_addr(dev); 1164 #endif 1165 return 0; 1166 } 1167 1168 static const struct udevice_id rk3399_pmuclk_ids[] = { 1169 { .compatible = "rockchip,rk3399-pmucru" }, 1170 { } 1171 }; 1172 1173 U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = { 1174 .name = "rockchip_rk3399_pmucru", 1175 .id = UCLASS_CLK, 1176 .of_match = rk3399_pmuclk_ids, 1177 .priv_auto_alloc_size = sizeof(struct rk3399_pmuclk_priv), 1178 .ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata, 1179 .ops = &rk3399_pmuclk_ops, 1180 .probe = rk3399_pmuclk_probe, 1181 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1182 .platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat), 1183 #endif 1184 }; 1185