1 /* 2 * (C) Copyright 2015 Google, Inc 3 * (C) 2017 Theobroma Systems Design und Consulting GmbH 4 * 5 * SPDX-License-Identifier: GPL-2.0 6 */ 7 8 #include <common.h> 9 #include <clk-uclass.h> 10 #include <dm.h> 11 #include <dt-structs.h> 12 #include <errno.h> 13 #include <mapmem.h> 14 #include <syscon.h> 15 #include <bitfield.h> 16 #include <asm/io.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/cru_rk3399.h> 19 #include <asm/arch/hardware.h> 20 #include <dm/lists.h> 21 #include <dt-bindings/clock/rk3399-cru.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #if CONFIG_IS_ENABLED(OF_PLATDATA) 26 struct rk3399_clk_plat { 27 struct dtd_rockchip_rk3399_cru dtd; 28 }; 29 30 struct rk3399_pmuclk_plat { 31 struct dtd_rockchip_rk3399_pmucru dtd; 32 }; 33 #endif 34 35 struct pll_div { 36 u32 refdiv; 37 u32 fbdiv; 38 u32 postdiv1; 39 u32 postdiv2; 40 u32 frac; 41 }; 42 43 #define RATE_TO_DIV(input_rate, output_rate) \ 44 ((input_rate) / (output_rate) - 1); 45 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 46 47 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ 48 .refdiv = _refdiv,\ 49 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ 50 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2}; 51 52 #if defined(CONFIG_SPL_BUILD) 53 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); 54 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2); 55 #else 56 static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1); 57 #endif 58 59 static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1); 60 static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1); 61 62 static const struct pll_div *apll_l_cfgs[] = { 63 [APLL_L_1600_MHZ] = &apll_l_1600_cfg, 64 [APLL_L_600_MHZ] = &apll_l_600_cfg, 65 }; 66 67 enum { 68 /* PLL_CON0 */ 69 PLL_FBDIV_MASK = 0xfff, 70 PLL_FBDIV_SHIFT = 0, 71 72 /* PLL_CON1 */ 73 PLL_POSTDIV2_SHIFT = 12, 74 PLL_POSTDIV2_MASK = 0x7 << PLL_POSTDIV2_SHIFT, 75 PLL_POSTDIV1_SHIFT = 8, 76 PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT, 77 PLL_REFDIV_MASK = 0x3f, 78 PLL_REFDIV_SHIFT = 0, 79 80 /* PLL_CON2 */ 81 PLL_LOCK_STATUS_SHIFT = 31, 82 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, 83 PLL_FRACDIV_MASK = 0xffffff, 84 PLL_FRACDIV_SHIFT = 0, 85 86 /* PLL_CON3 */ 87 PLL_MODE_SHIFT = 8, 88 PLL_MODE_MASK = 3 << PLL_MODE_SHIFT, 89 PLL_MODE_SLOW = 0, 90 PLL_MODE_NORM, 91 PLL_MODE_DEEP, 92 PLL_DSMPD_SHIFT = 3, 93 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, 94 PLL_INTEGER_MODE = 1, 95 96 /* PMUCRU_CLKSEL_CON0 */ 97 PMU_PCLK_DIV_CON_MASK = 0x1f, 98 PMU_PCLK_DIV_CON_SHIFT = 0, 99 100 /* PMUCRU_CLKSEL_CON1 */ 101 SPI3_PLL_SEL_SHIFT = 7, 102 SPI3_PLL_SEL_MASK = 1 << SPI3_PLL_SEL_SHIFT, 103 SPI3_PLL_SEL_24M = 0, 104 SPI3_PLL_SEL_PPLL = 1, 105 SPI3_DIV_CON_SHIFT = 0x0, 106 SPI3_DIV_CON_MASK = 0x7f, 107 108 /* PMUCRU_CLKSEL_CON2 */ 109 I2C_DIV_CON_MASK = 0x7f, 110 CLK_I2C8_DIV_CON_SHIFT = 8, 111 CLK_I2C0_DIV_CON_SHIFT = 0, 112 113 /* PMUCRU_CLKSEL_CON3 */ 114 CLK_I2C4_DIV_CON_SHIFT = 0, 115 116 /* CLKSEL_CON0 */ 117 ACLKM_CORE_L_DIV_CON_SHIFT = 8, 118 ACLKM_CORE_L_DIV_CON_MASK = 0x1f << ACLKM_CORE_L_DIV_CON_SHIFT, 119 CLK_CORE_L_PLL_SEL_SHIFT = 6, 120 CLK_CORE_L_PLL_SEL_MASK = 3 << CLK_CORE_L_PLL_SEL_SHIFT, 121 CLK_CORE_L_PLL_SEL_ALPLL = 0x0, 122 CLK_CORE_L_PLL_SEL_ABPLL = 0x1, 123 CLK_CORE_L_PLL_SEL_DPLL = 0x10, 124 CLK_CORE_L_PLL_SEL_GPLL = 0x11, 125 CLK_CORE_L_DIV_MASK = 0x1f, 126 CLK_CORE_L_DIV_SHIFT = 0, 127 128 /* CLKSEL_CON1 */ 129 PCLK_DBG_L_DIV_SHIFT = 0x8, 130 PCLK_DBG_L_DIV_MASK = 0x1f << PCLK_DBG_L_DIV_SHIFT, 131 ATCLK_CORE_L_DIV_SHIFT = 0, 132 ATCLK_CORE_L_DIV_MASK = 0x1f << ATCLK_CORE_L_DIV_SHIFT, 133 134 /* CLKSEL_CON14 */ 135 PCLK_PERIHP_DIV_CON_SHIFT = 12, 136 PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT, 137 HCLK_PERIHP_DIV_CON_SHIFT = 8, 138 HCLK_PERIHP_DIV_CON_MASK = 3 << HCLK_PERIHP_DIV_CON_SHIFT, 139 ACLK_PERIHP_PLL_SEL_SHIFT = 7, 140 ACLK_PERIHP_PLL_SEL_MASK = 1 << ACLK_PERIHP_PLL_SEL_SHIFT, 141 ACLK_PERIHP_PLL_SEL_CPLL = 0, 142 ACLK_PERIHP_PLL_SEL_GPLL = 1, 143 ACLK_PERIHP_DIV_CON_SHIFT = 0, 144 ACLK_PERIHP_DIV_CON_MASK = 0x1f, 145 146 /* CLKSEL_CON21 */ 147 ACLK_EMMC_PLL_SEL_SHIFT = 7, 148 ACLK_EMMC_PLL_SEL_MASK = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT, 149 ACLK_EMMC_PLL_SEL_GPLL = 0x1, 150 ACLK_EMMC_DIV_CON_SHIFT = 0, 151 ACLK_EMMC_DIV_CON_MASK = 0x1f, 152 153 /* CLKSEL_CON22 */ 154 CLK_EMMC_PLL_SHIFT = 8, 155 CLK_EMMC_PLL_MASK = 0x7 << CLK_EMMC_PLL_SHIFT, 156 CLK_EMMC_PLL_SEL_GPLL = 0x1, 157 CLK_EMMC_PLL_SEL_24M = 0x5, 158 CLK_EMMC_DIV_CON_SHIFT = 0, 159 CLK_EMMC_DIV_CON_MASK = 0x7f << CLK_EMMC_DIV_CON_SHIFT, 160 161 /* CLKSEL_CON23 */ 162 PCLK_PERILP0_DIV_CON_SHIFT = 12, 163 PCLK_PERILP0_DIV_CON_MASK = 0x7 << PCLK_PERILP0_DIV_CON_SHIFT, 164 HCLK_PERILP0_DIV_CON_SHIFT = 8, 165 HCLK_PERILP0_DIV_CON_MASK = 3 << HCLK_PERILP0_DIV_CON_SHIFT, 166 ACLK_PERILP0_PLL_SEL_SHIFT = 7, 167 ACLK_PERILP0_PLL_SEL_MASK = 1 << ACLK_PERILP0_PLL_SEL_SHIFT, 168 ACLK_PERILP0_PLL_SEL_CPLL = 0, 169 ACLK_PERILP0_PLL_SEL_GPLL = 1, 170 ACLK_PERILP0_DIV_CON_SHIFT = 0, 171 ACLK_PERILP0_DIV_CON_MASK = 0x1f, 172 173 /* CLKSEL_CON25 */ 174 PCLK_PERILP1_DIV_CON_SHIFT = 8, 175 PCLK_PERILP1_DIV_CON_MASK = 0x7 << PCLK_PERILP1_DIV_CON_SHIFT, 176 HCLK_PERILP1_PLL_SEL_SHIFT = 7, 177 HCLK_PERILP1_PLL_SEL_MASK = 1 << HCLK_PERILP1_PLL_SEL_SHIFT, 178 HCLK_PERILP1_PLL_SEL_CPLL = 0, 179 HCLK_PERILP1_PLL_SEL_GPLL = 1, 180 HCLK_PERILP1_DIV_CON_SHIFT = 0, 181 HCLK_PERILP1_DIV_CON_MASK = 0x1f, 182 183 /* CLKSEL_CON26 */ 184 CLK_SARADC_DIV_CON_SHIFT = 8, 185 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8), 186 CLK_SARADC_DIV_CON_WIDTH = 8, 187 188 /* CLKSEL_CON27 */ 189 CLK_TSADC_SEL_X24M = 0x0, 190 CLK_TSADC_SEL_SHIFT = 15, 191 CLK_TSADC_SEL_MASK = 1 << CLK_TSADC_SEL_SHIFT, 192 CLK_TSADC_DIV_CON_SHIFT = 0, 193 CLK_TSADC_DIV_CON_MASK = 0x3ff, 194 195 /* CLKSEL_CON47 & CLKSEL_CON48 */ 196 ACLK_VOP_PLL_SEL_SHIFT = 6, 197 ACLK_VOP_PLL_SEL_MASK = 0x3 << ACLK_VOP_PLL_SEL_SHIFT, 198 ACLK_VOP_PLL_SEL_CPLL = 0x1, 199 ACLK_VOP_DIV_CON_SHIFT = 0, 200 ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT, 201 202 /* CLKSEL_CON49 & CLKSEL_CON50 */ 203 DCLK_VOP_DCLK_SEL_SHIFT = 11, 204 DCLK_VOP_DCLK_SEL_MASK = 1 << DCLK_VOP_DCLK_SEL_SHIFT, 205 DCLK_VOP_DCLK_SEL_DIVOUT = 0, 206 DCLK_VOP_PLL_SEL_SHIFT = 8, 207 DCLK_VOP_PLL_SEL_MASK = 3 << DCLK_VOP_PLL_SEL_SHIFT, 208 DCLK_VOP_PLL_SEL_VPLL = 0, 209 DCLK_VOP_DIV_CON_MASK = 0xff, 210 DCLK_VOP_DIV_CON_SHIFT = 0, 211 212 /* CLKSEL_CON58 */ 213 CLK_SPI_PLL_SEL_WIDTH = 1, 214 CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1), 215 CLK_SPI_PLL_SEL_CPLL = 0, 216 CLK_SPI_PLL_SEL_GPLL = 1, 217 CLK_SPI_PLL_DIV_CON_WIDTH = 7, 218 CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1), 219 220 CLK_SPI5_PLL_DIV_CON_SHIFT = 8, 221 CLK_SPI5_PLL_SEL_SHIFT = 15, 222 223 /* CLKSEL_CON59 */ 224 CLK_SPI1_PLL_SEL_SHIFT = 15, 225 CLK_SPI1_PLL_DIV_CON_SHIFT = 8, 226 CLK_SPI0_PLL_SEL_SHIFT = 7, 227 CLK_SPI0_PLL_DIV_CON_SHIFT = 0, 228 229 /* CLKSEL_CON60 */ 230 CLK_SPI4_PLL_SEL_SHIFT = 15, 231 CLK_SPI4_PLL_DIV_CON_SHIFT = 8, 232 CLK_SPI2_PLL_SEL_SHIFT = 7, 233 CLK_SPI2_PLL_DIV_CON_SHIFT = 0, 234 235 /* CLKSEL_CON61 */ 236 CLK_I2C_PLL_SEL_MASK = 1, 237 CLK_I2C_PLL_SEL_CPLL = 0, 238 CLK_I2C_PLL_SEL_GPLL = 1, 239 CLK_I2C5_PLL_SEL_SHIFT = 15, 240 CLK_I2C5_DIV_CON_SHIFT = 8, 241 CLK_I2C1_PLL_SEL_SHIFT = 7, 242 CLK_I2C1_DIV_CON_SHIFT = 0, 243 244 /* CLKSEL_CON62 */ 245 CLK_I2C6_PLL_SEL_SHIFT = 15, 246 CLK_I2C6_DIV_CON_SHIFT = 8, 247 CLK_I2C2_PLL_SEL_SHIFT = 7, 248 CLK_I2C2_DIV_CON_SHIFT = 0, 249 250 /* CLKSEL_CON63 */ 251 CLK_I2C7_PLL_SEL_SHIFT = 15, 252 CLK_I2C7_DIV_CON_SHIFT = 8, 253 CLK_I2C3_PLL_SEL_SHIFT = 7, 254 CLK_I2C3_DIV_CON_SHIFT = 0, 255 256 /* CRU_SOFTRST_CON4 */ 257 RESETN_DDR0_REQ_SHIFT = 8, 258 RESETN_DDR0_REQ_MASK = 1 << RESETN_DDR0_REQ_SHIFT, 259 RESETN_DDRPHY0_REQ_SHIFT = 9, 260 RESETN_DDRPHY0_REQ_MASK = 1 << RESETN_DDRPHY0_REQ_SHIFT, 261 RESETN_DDR1_REQ_SHIFT = 12, 262 RESETN_DDR1_REQ_MASK = 1 << RESETN_DDR1_REQ_SHIFT, 263 RESETN_DDRPHY1_REQ_SHIFT = 13, 264 RESETN_DDRPHY1_REQ_MASK = 1 << RESETN_DDRPHY1_REQ_SHIFT, 265 }; 266 267 #define VCO_MAX_KHZ (3200 * (MHz / KHz)) 268 #define VCO_MIN_KHZ (800 * (MHz / KHz)) 269 #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz)) 270 #define OUTPUT_MIN_KHZ (16 * (MHz / KHz)) 271 272 /* 273 * the div restructions of pll in integer mode, these are defined in 274 * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0 275 */ 276 #define PLL_DIV_MIN 16 277 #define PLL_DIV_MAX 3200 278 279 /* 280 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63): 281 * Formulas also embedded within the Fractional PLL Verilog model: 282 * If DSMPD = 1 (DSM is disabled, "integer mode") 283 * FOUTVCO = FREF / REFDIV * FBDIV 284 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 285 * Where: 286 * FOUTVCO = Fractional PLL non-divided output frequency 287 * FOUTPOSTDIV = Fractional PLL divided output frequency 288 * (output of second post divider) 289 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input) 290 * REFDIV = Fractional PLL input reference clock divider 291 * FBDIV = Integer value programmed into feedback divide 292 * 293 */ 294 static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div) 295 { 296 /* All 8 PLLs have same VCO and output frequency range restrictions. */ 297 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; 298 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; 299 300 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, " 301 "postdiv2=%d, vco=%u khz, output=%u khz\n", 302 pll_con, div->fbdiv, div->refdiv, div->postdiv1, 303 div->postdiv2, vco_khz, output_khz); 304 assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ && 305 output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ && 306 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); 307 308 /* 309 * When power on or changing PLL setting, 310 * we must force PLL into slow mode to ensure output stable clock. 311 */ 312 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, 313 PLL_MODE_SLOW << PLL_MODE_SHIFT); 314 315 /* use integer mode */ 316 rk_clrsetreg(&pll_con[3], PLL_DSMPD_MASK, 317 PLL_INTEGER_MODE << PLL_DSMPD_SHIFT); 318 319 rk_clrsetreg(&pll_con[0], PLL_FBDIV_MASK, 320 div->fbdiv << PLL_FBDIV_SHIFT); 321 rk_clrsetreg(&pll_con[1], 322 PLL_POSTDIV2_MASK | PLL_POSTDIV1_MASK | 323 PLL_REFDIV_MASK | PLL_REFDIV_SHIFT, 324 (div->postdiv2 << PLL_POSTDIV2_SHIFT) | 325 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | 326 (div->refdiv << PLL_REFDIV_SHIFT)); 327 328 /* waiting for pll lock */ 329 while (!(readl(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT))) 330 udelay(1); 331 332 /* pll enter normal mode */ 333 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, 334 PLL_MODE_NORM << PLL_MODE_SHIFT); 335 } 336 337 static int pll_para_config(u32 freq_hz, struct pll_div *div) 338 { 339 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; 340 u32 postdiv1, postdiv2 = 1; 341 u32 fref_khz; 342 u32 diff_khz, best_diff_khz; 343 const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16; 344 const u32 max_postdiv1 = 7, max_postdiv2 = 7; 345 u32 vco_khz; 346 u32 freq_khz = freq_hz / KHz; 347 348 if (!freq_hz) { 349 printf("%s: the frequency can't be 0 Hz\n", __func__); 350 return -1; 351 } 352 353 postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz); 354 if (postdiv1 > max_postdiv1) { 355 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); 356 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); 357 } 358 359 vco_khz = freq_khz * postdiv1 * postdiv2; 360 361 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || 362 postdiv2 > max_postdiv2) { 363 printf("%s: Cannot find out a supported VCO" 364 " for Frequency (%uHz).\n", __func__, freq_hz); 365 return -1; 366 } 367 368 div->postdiv1 = postdiv1; 369 div->postdiv2 = postdiv2; 370 371 best_diff_khz = vco_khz; 372 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { 373 fref_khz = ref_khz / refdiv; 374 375 fbdiv = vco_khz / fref_khz; 376 if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv)) 377 continue; 378 diff_khz = vco_khz - fbdiv * fref_khz; 379 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) { 380 fbdiv++; 381 diff_khz = fref_khz - diff_khz; 382 } 383 384 if (diff_khz >= best_diff_khz) 385 continue; 386 387 best_diff_khz = diff_khz; 388 div->refdiv = refdiv; 389 div->fbdiv = fbdiv; 390 } 391 392 if (best_diff_khz > 4 * (MHz/KHz)) { 393 printf("%s: Failed to match output frequency %u, " 394 "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz, 395 best_diff_khz * KHz); 396 return -1; 397 } 398 return 0; 399 } 400 401 #ifdef CONFIG_SPL_BUILD 402 static void rkclk_init(struct rk3399_cru *cru) 403 { 404 u32 aclk_div; 405 u32 hclk_div; 406 u32 pclk_div; 407 408 rk3399_configure_cpu(cru, APLL_L_600_MHZ); 409 /* 410 * some cru registers changed by bootrom, we'd better reset them to 411 * reset/default values described in TRM to avoid confusion in kernel. 412 * Please consider these three lines as a fix of bootrom bug. 413 */ 414 rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101); 415 rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f); 416 rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003); 417 418 /* configure gpll cpll */ 419 rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg); 420 rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg); 421 422 /* configure perihp aclk, hclk, pclk */ 423 aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1; 424 assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); 425 426 hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1; 427 assert((hclk_div + 1) * PERIHP_HCLK_HZ == 428 PERIHP_ACLK_HZ && (hclk_div < 0x4)); 429 430 pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1; 431 assert((pclk_div + 1) * PERIHP_PCLK_HZ == 432 PERIHP_ACLK_HZ && (pclk_div < 0x7)); 433 434 rk_clrsetreg(&cru->clksel_con[14], 435 PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK | 436 ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK, 437 pclk_div << PCLK_PERIHP_DIV_CON_SHIFT | 438 hclk_div << HCLK_PERIHP_DIV_CON_SHIFT | 439 ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT | 440 aclk_div << ACLK_PERIHP_DIV_CON_SHIFT); 441 442 /* configure perilp0 aclk, hclk, pclk */ 443 aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1; 444 assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); 445 446 hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1; 447 assert((hclk_div + 1) * PERILP0_HCLK_HZ == 448 PERILP0_ACLK_HZ && (hclk_div < 0x4)); 449 450 pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1; 451 assert((pclk_div + 1) * PERILP0_PCLK_HZ == 452 PERILP0_ACLK_HZ && (pclk_div < 0x7)); 453 454 rk_clrsetreg(&cru->clksel_con[23], 455 PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK | 456 ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK, 457 pclk_div << PCLK_PERILP0_DIV_CON_SHIFT | 458 hclk_div << HCLK_PERILP0_DIV_CON_SHIFT | 459 ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT | 460 aclk_div << ACLK_PERILP0_DIV_CON_SHIFT); 461 462 /* perilp1 hclk select gpll as source */ 463 hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1; 464 assert((hclk_div + 1) * PERILP1_HCLK_HZ == 465 GPLL_HZ && (hclk_div < 0x1f)); 466 467 pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1; 468 assert((pclk_div + 1) * PERILP1_HCLK_HZ == 469 PERILP1_HCLK_HZ && (hclk_div < 0x7)); 470 471 rk_clrsetreg(&cru->clksel_con[25], 472 PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK | 473 HCLK_PERILP1_PLL_SEL_MASK, 474 pclk_div << PCLK_PERILP1_DIV_CON_SHIFT | 475 hclk_div << HCLK_PERILP1_DIV_CON_SHIFT | 476 HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT); 477 } 478 #endif 479 480 void rk3399_configure_cpu(struct rk3399_cru *cru, 481 enum apll_l_frequencies apll_l_freq) 482 { 483 u32 aclkm_div; 484 u32 pclk_dbg_div; 485 u32 atclk_div; 486 487 rkclk_set_pll(&cru->apll_l_con[0], apll_l_cfgs[apll_l_freq]); 488 489 aclkm_div = APLL_HZ / ACLKM_CORE_HZ - 1; 490 assert((aclkm_div + 1) * ACLKM_CORE_HZ == APLL_HZ && 491 aclkm_div < 0x1f); 492 493 pclk_dbg_div = APLL_HZ / PCLK_DBG_HZ - 1; 494 assert((pclk_dbg_div + 1) * PCLK_DBG_HZ == APLL_HZ && 495 pclk_dbg_div < 0x1f); 496 497 atclk_div = APLL_HZ / ATCLK_CORE_HZ - 1; 498 assert((atclk_div + 1) * ATCLK_CORE_HZ == APLL_HZ && 499 atclk_div < 0x1f); 500 501 rk_clrsetreg(&cru->clksel_con[0], 502 ACLKM_CORE_L_DIV_CON_MASK | CLK_CORE_L_PLL_SEL_MASK | 503 CLK_CORE_L_DIV_MASK, 504 aclkm_div << ACLKM_CORE_L_DIV_CON_SHIFT | 505 CLK_CORE_L_PLL_SEL_ALPLL << CLK_CORE_L_PLL_SEL_SHIFT | 506 0 << CLK_CORE_L_DIV_SHIFT); 507 508 rk_clrsetreg(&cru->clksel_con[1], 509 PCLK_DBG_L_DIV_MASK | ATCLK_CORE_L_DIV_MASK, 510 pclk_dbg_div << PCLK_DBG_L_DIV_SHIFT | 511 atclk_div << ATCLK_CORE_L_DIV_SHIFT); 512 } 513 #define I2C_CLK_REG_MASK(bus) \ 514 (I2C_DIV_CON_MASK << \ 515 CLK_I2C ##bus## _DIV_CON_SHIFT | \ 516 CLK_I2C_PLL_SEL_MASK << \ 517 CLK_I2C ##bus## _PLL_SEL_SHIFT) 518 519 #define I2C_CLK_REG_VALUE(bus, clk_div) \ 520 ((clk_div - 1) << \ 521 CLK_I2C ##bus## _DIV_CON_SHIFT | \ 522 CLK_I2C_PLL_SEL_GPLL << \ 523 CLK_I2C ##bus## _PLL_SEL_SHIFT) 524 525 #define I2C_CLK_DIV_VALUE(con, bus) \ 526 (con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \ 527 I2C_DIV_CON_MASK; 528 529 #define I2C_PMUCLK_REG_MASK(bus) \ 530 (I2C_DIV_CON_MASK << \ 531 CLK_I2C ##bus## _DIV_CON_SHIFT) 532 533 #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \ 534 ((clk_div - 1) << \ 535 CLK_I2C ##bus## _DIV_CON_SHIFT) 536 537 static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id) 538 { 539 u32 div, con; 540 541 switch (clk_id) { 542 case SCLK_I2C1: 543 con = readl(&cru->clksel_con[61]); 544 div = I2C_CLK_DIV_VALUE(con, 1); 545 break; 546 case SCLK_I2C2: 547 con = readl(&cru->clksel_con[62]); 548 div = I2C_CLK_DIV_VALUE(con, 2); 549 break; 550 case SCLK_I2C3: 551 con = readl(&cru->clksel_con[63]); 552 div = I2C_CLK_DIV_VALUE(con, 3); 553 break; 554 case SCLK_I2C5: 555 con = readl(&cru->clksel_con[61]); 556 div = I2C_CLK_DIV_VALUE(con, 5); 557 break; 558 case SCLK_I2C6: 559 con = readl(&cru->clksel_con[62]); 560 div = I2C_CLK_DIV_VALUE(con, 6); 561 break; 562 case SCLK_I2C7: 563 con = readl(&cru->clksel_con[63]); 564 div = I2C_CLK_DIV_VALUE(con, 7); 565 break; 566 default: 567 printf("do not support this i2c bus\n"); 568 return -EINVAL; 569 } 570 571 return DIV_TO_RATE(GPLL_HZ, div); 572 } 573 574 static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) 575 { 576 int src_clk_div; 577 578 /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/ 579 src_clk_div = GPLL_HZ / hz; 580 assert(src_clk_div - 1 < 127); 581 582 switch (clk_id) { 583 case SCLK_I2C1: 584 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(1), 585 I2C_CLK_REG_VALUE(1, src_clk_div)); 586 break; 587 case SCLK_I2C2: 588 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(2), 589 I2C_CLK_REG_VALUE(2, src_clk_div)); 590 break; 591 case SCLK_I2C3: 592 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(3), 593 I2C_CLK_REG_VALUE(3, src_clk_div)); 594 break; 595 case SCLK_I2C5: 596 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(5), 597 I2C_CLK_REG_VALUE(5, src_clk_div)); 598 break; 599 case SCLK_I2C6: 600 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(6), 601 I2C_CLK_REG_VALUE(6, src_clk_div)); 602 break; 603 case SCLK_I2C7: 604 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(7), 605 I2C_CLK_REG_VALUE(7, src_clk_div)); 606 break; 607 default: 608 printf("do not support this i2c bus\n"); 609 return -EINVAL; 610 } 611 612 return rk3399_i2c_get_clk(cru, clk_id); 613 } 614 615 /* 616 * RK3399 SPI clocks have a common divider-width (7 bits) and a single bit 617 * to select either CPLL or GPLL as the clock-parent. The location within 618 * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable. 619 */ 620 621 struct spi_clkreg { 622 uint8_t reg; /* CLKSEL_CON[reg] register in CRU */ 623 uint8_t div_shift; 624 uint8_t sel_shift; 625 }; 626 627 /* 628 * The entries are numbered relative to their offset from SCLK_SPI0. 629 * 630 * Note that SCLK_SPI3 (which is configured via PMUCRU and requires different 631 * logic is not supported). 632 */ 633 static const struct spi_clkreg spi_clkregs[] = { 634 [0] = { .reg = 59, 635 .div_shift = CLK_SPI0_PLL_DIV_CON_SHIFT, 636 .sel_shift = CLK_SPI0_PLL_SEL_SHIFT, }, 637 [1] = { .reg = 59, 638 .div_shift = CLK_SPI1_PLL_DIV_CON_SHIFT, 639 .sel_shift = CLK_SPI1_PLL_SEL_SHIFT, }, 640 [2] = { .reg = 60, 641 .div_shift = CLK_SPI2_PLL_DIV_CON_SHIFT, 642 .sel_shift = CLK_SPI2_PLL_SEL_SHIFT, }, 643 [3] = { .reg = 60, 644 .div_shift = CLK_SPI4_PLL_DIV_CON_SHIFT, 645 .sel_shift = CLK_SPI4_PLL_SEL_SHIFT, }, 646 [4] = { .reg = 58, 647 .div_shift = CLK_SPI5_PLL_DIV_CON_SHIFT, 648 .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, }, 649 }; 650 651 static inline u32 extract_bits(u32 val, unsigned width, unsigned shift) 652 { 653 return (val >> shift) & ((1 << width) - 1); 654 } 655 656 static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id) 657 { 658 const struct spi_clkreg *spiclk = NULL; 659 u32 div, val; 660 661 switch (clk_id) { 662 case SCLK_SPI0 ... SCLK_SPI5: 663 spiclk = &spi_clkregs[clk_id - SCLK_SPI0]; 664 break; 665 666 default: 667 error("%s: SPI clk-id %ld not supported\n", __func__, clk_id); 668 return -EINVAL; 669 } 670 671 val = readl(&cru->clksel_con[spiclk->reg]); 672 div = extract_bits(val, CLK_SPI_PLL_DIV_CON_WIDTH, spiclk->div_shift); 673 674 return DIV_TO_RATE(GPLL_HZ, div); 675 } 676 677 static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) 678 { 679 const struct spi_clkreg *spiclk = NULL; 680 int src_clk_div; 681 682 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; 683 assert(src_clk_div < 128); 684 685 switch (clk_id) { 686 case SCLK_SPI1 ... SCLK_SPI5: 687 spiclk = &spi_clkregs[clk_id - SCLK_SPI0]; 688 break; 689 690 default: 691 error("%s: SPI clk-id %ld not supported\n", __func__, clk_id); 692 return -EINVAL; 693 } 694 695 rk_clrsetreg(&cru->clksel_con[spiclk->reg], 696 ((CLK_SPI_PLL_DIV_CON_MASK << spiclk->div_shift) | 697 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)), 698 ((src_clk_div << spiclk->div_shift) | 699 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift))); 700 701 return rk3399_spi_get_clk(cru, clk_id); 702 } 703 704 static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz) 705 { 706 struct pll_div vpll_config = {0}; 707 int aclk_vop = 198*MHz; 708 void *aclkreg_addr, *dclkreg_addr; 709 u32 div; 710 711 switch (clk_id) { 712 case DCLK_VOP0: 713 aclkreg_addr = &cru->clksel_con[47]; 714 dclkreg_addr = &cru->clksel_con[49]; 715 break; 716 case DCLK_VOP1: 717 aclkreg_addr = &cru->clksel_con[48]; 718 dclkreg_addr = &cru->clksel_con[50]; 719 break; 720 default: 721 return -EINVAL; 722 } 723 /* vop aclk source clk: cpll */ 724 div = CPLL_HZ / aclk_vop; 725 assert(div - 1 < 32); 726 727 rk_clrsetreg(aclkreg_addr, 728 ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK, 729 ACLK_VOP_PLL_SEL_CPLL << ACLK_VOP_PLL_SEL_SHIFT | 730 (div - 1) << ACLK_VOP_DIV_CON_SHIFT); 731 732 /* vop dclk source from vpll, and equals to vpll(means div == 1) */ 733 if (pll_para_config(hz, &vpll_config)) 734 return -1; 735 736 rkclk_set_pll(&cru->vpll_con[0], &vpll_config); 737 738 rk_clrsetreg(dclkreg_addr, 739 DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_PLL_SEL_MASK| 740 DCLK_VOP_DIV_CON_MASK, 741 DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT | 742 DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT | 743 (1 - 1) << DCLK_VOP_DIV_CON_SHIFT); 744 745 return hz; 746 } 747 748 static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id) 749 { 750 u32 div, con; 751 752 switch (clk_id) { 753 case HCLK_SDMMC: 754 case SCLK_SDMMC: 755 con = readl(&cru->clksel_con[16]); 756 /* dwmmc controller have internal div 2 */ 757 div = 2; 758 break; 759 case SCLK_EMMC: 760 con = readl(&cru->clksel_con[21]); 761 div = 1; 762 break; 763 default: 764 return -EINVAL; 765 } 766 767 div *= (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT; 768 if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT 769 == CLK_EMMC_PLL_SEL_24M) 770 return DIV_TO_RATE(OSC_HZ, div); 771 else 772 return DIV_TO_RATE(GPLL_HZ, div); 773 } 774 775 static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru, 776 ulong clk_id, ulong set_rate) 777 { 778 int src_clk_div; 779 int aclk_emmc = 198*MHz; 780 781 switch (clk_id) { 782 case HCLK_SDMMC: 783 case SCLK_SDMMC: 784 /* Select clk_sdmmc source from GPLL by default */ 785 /* mmc clock defaulg div 2 internal, provide double in cru */ 786 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate); 787 788 if (src_clk_div > 128) { 789 /* use 24MHz source for 400KHz clock */ 790 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); 791 assert(src_clk_div - 1 < 128); 792 rk_clrsetreg(&cru->clksel_con[16], 793 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 794 CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT | 795 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 796 } else { 797 rk_clrsetreg(&cru->clksel_con[16], 798 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 799 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | 800 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 801 } 802 break; 803 case SCLK_EMMC: 804 /* Select aclk_emmc source from GPLL */ 805 src_clk_div = DIV_ROUND_UP(GPLL_HZ , aclk_emmc); 806 assert(src_clk_div - 1 < 32); 807 808 rk_clrsetreg(&cru->clksel_con[21], 809 ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK, 810 ACLK_EMMC_PLL_SEL_GPLL << ACLK_EMMC_PLL_SEL_SHIFT | 811 (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT); 812 813 /* Select clk_emmc source from GPLL too */ 814 src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate); 815 assert(src_clk_div - 1 < 128); 816 817 rk_clrsetreg(&cru->clksel_con[22], 818 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 819 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | 820 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 821 break; 822 default: 823 return -EINVAL; 824 } 825 return rk3399_mmc_get_clk(cru, clk_id); 826 } 827 828 #define PMUSGRF_DDR_RGN_CON16 0xff330040 829 static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru, 830 ulong set_rate) 831 { 832 struct pll_div dpll_cfg; 833 834 /* IC ECO bug, need to set this register */ 835 writel(0xc000c000, PMUSGRF_DDR_RGN_CON16); 836 837 /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */ 838 switch (set_rate) { 839 case 200*MHz: 840 dpll_cfg = (struct pll_div) 841 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1}; 842 break; 843 case 300*MHz: 844 dpll_cfg = (struct pll_div) 845 {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1}; 846 break; 847 case 666*MHz: 848 dpll_cfg = (struct pll_div) 849 {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1}; 850 break; 851 case 800*MHz: 852 dpll_cfg = (struct pll_div) 853 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}; 854 break; 855 case 933*MHz: 856 dpll_cfg = (struct pll_div) 857 {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1}; 858 break; 859 default: 860 error("Unsupported SDRAM frequency!,%ld\n", set_rate); 861 } 862 rkclk_set_pll(&cru->dpll_con[0], &dpll_cfg); 863 864 return set_rate; 865 } 866 867 static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru) 868 { 869 u32 div, val; 870 871 val = readl(&cru->clksel_con[26]); 872 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT, 873 CLK_SARADC_DIV_CON_WIDTH); 874 875 return DIV_TO_RATE(OSC_HZ, div); 876 } 877 878 static ulong rk3399_saradc_set_clk(struct rk3399_cru *cru, uint hz) 879 { 880 int src_clk_div; 881 882 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; 883 assert(src_clk_div < 128); 884 885 rk_clrsetreg(&cru->clksel_con[26], 886 CLK_SARADC_DIV_CON_MASK, 887 src_clk_div << CLK_SARADC_DIV_CON_SHIFT); 888 889 return rk3399_saradc_get_clk(cru); 890 } 891 892 static ulong rk3399_clk_get_rate(struct clk *clk) 893 { 894 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 895 ulong rate = 0; 896 897 switch (clk->id) { 898 case 0 ... 63: 899 return 0; 900 case HCLK_SDMMC: 901 case SCLK_SDMMC: 902 case SCLK_EMMC: 903 rate = rk3399_mmc_get_clk(priv->cru, clk->id); 904 break; 905 case SCLK_I2C1: 906 case SCLK_I2C2: 907 case SCLK_I2C3: 908 case SCLK_I2C5: 909 case SCLK_I2C6: 910 case SCLK_I2C7: 911 rate = rk3399_i2c_get_clk(priv->cru, clk->id); 912 break; 913 case SCLK_SPI0...SCLK_SPI5: 914 rate = rk3399_spi_get_clk(priv->cru, clk->id); 915 break; 916 case SCLK_UART0: 917 case SCLK_UART2: 918 return 24000000; 919 break; 920 case PCLK_HDMI_CTRL: 921 break; 922 case DCLK_VOP0: 923 case DCLK_VOP1: 924 break; 925 case PCLK_EFUSE1024NS: 926 break; 927 case SCLK_SARADC: 928 rate = rk3399_saradc_get_clk(priv->cru); 929 break; 930 default: 931 return -ENOENT; 932 } 933 934 return rate; 935 } 936 937 static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) 938 { 939 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 940 ulong ret = 0; 941 942 switch (clk->id) { 943 case 0 ... 63: 944 return 0; 945 case HCLK_SDMMC: 946 case SCLK_SDMMC: 947 case SCLK_EMMC: 948 ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate); 949 break; 950 case SCLK_MAC: 951 /* nothing to do, as this is an external clock */ 952 ret = rate; 953 break; 954 case SCLK_I2C1: 955 case SCLK_I2C2: 956 case SCLK_I2C3: 957 case SCLK_I2C5: 958 case SCLK_I2C6: 959 case SCLK_I2C7: 960 ret = rk3399_i2c_set_clk(priv->cru, clk->id, rate); 961 break; 962 case SCLK_SPI0...SCLK_SPI5: 963 ret = rk3399_spi_set_clk(priv->cru, clk->id, rate); 964 break; 965 case PCLK_HDMI_CTRL: 966 case PCLK_VIO_GRF: 967 /* the PCLK gates for video are enabled by default */ 968 break; 969 case DCLK_VOP0: 970 case DCLK_VOP1: 971 ret = rk3399_vop_set_clk(priv->cru, clk->id, rate); 972 break; 973 case SCLK_DDRCLK: 974 ret = rk3399_ddr_set_clk(priv->cru, rate); 975 break; 976 case PCLK_EFUSE1024NS: 977 break; 978 case SCLK_SARADC: 979 ret = rk3399_saradc_set_clk(priv->cru, rate); 980 break; 981 default: 982 return -ENOENT; 983 } 984 985 return ret; 986 } 987 988 static struct clk_ops rk3399_clk_ops = { 989 .get_rate = rk3399_clk_get_rate, 990 .set_rate = rk3399_clk_set_rate, 991 }; 992 993 static int rk3399_clk_probe(struct udevice *dev) 994 { 995 #ifdef CONFIG_SPL_BUILD 996 struct rk3399_clk_priv *priv = dev_get_priv(dev); 997 998 #if CONFIG_IS_ENABLED(OF_PLATDATA) 999 struct rk3399_clk_plat *plat = dev_get_platdata(dev); 1000 1001 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); 1002 #endif 1003 rkclk_init(priv->cru); 1004 #endif 1005 return 0; 1006 } 1007 1008 static int rk3399_clk_ofdata_to_platdata(struct udevice *dev) 1009 { 1010 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 1011 struct rk3399_clk_priv *priv = dev_get_priv(dev); 1012 1013 priv->cru = (struct rk3399_cru *)devfdt_get_addr(dev); 1014 #endif 1015 return 0; 1016 } 1017 1018 static int rk3399_clk_bind(struct udevice *dev) 1019 { 1020 int ret; 1021 struct udevice *sys_child, *sf_child; 1022 struct sysreset_reg *priv; 1023 struct softreset_reg *sf_priv; 1024 1025 /* The reset driver does not have a device node, so bind it here */ 1026 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", 1027 &sys_child); 1028 if (ret) { 1029 debug("Warning: No sysreset driver: ret=%d\n", ret); 1030 } else { 1031 priv = malloc(sizeof(struct sysreset_reg)); 1032 priv->glb_srst_fst_value = offsetof(struct rk3399_cru, 1033 glb_srst_fst_value); 1034 priv->glb_srst_snd_value = offsetof(struct rk3399_cru, 1035 glb_srst_snd_value); 1036 sys_child->priv = priv; 1037 } 1038 1039 ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset", 1040 dev_ofnode(dev), &sf_child); 1041 if (ret) { 1042 debug("Warning: No rockchip reset driver: ret=%d\n", ret); 1043 } else { 1044 sf_priv = malloc(sizeof(struct softreset_reg)); 1045 sf_priv->sf_reset_offset = offsetof(struct rk3399_cru, 1046 softrst_con[0]); 1047 sf_priv->sf_reset_num = 21; 1048 sf_child->priv = sf_priv; 1049 } 1050 1051 return 0; 1052 } 1053 1054 static const struct udevice_id rk3399_clk_ids[] = { 1055 { .compatible = "rockchip,rk3399-cru" }, 1056 { } 1057 }; 1058 1059 U_BOOT_DRIVER(clk_rk3399) = { 1060 .name = "rockchip_rk3399_cru", 1061 .id = UCLASS_CLK, 1062 .of_match = rk3399_clk_ids, 1063 .priv_auto_alloc_size = sizeof(struct rk3399_clk_priv), 1064 .ofdata_to_platdata = rk3399_clk_ofdata_to_platdata, 1065 .ops = &rk3399_clk_ops, 1066 .bind = rk3399_clk_bind, 1067 .probe = rk3399_clk_probe, 1068 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1069 .platdata_auto_alloc_size = sizeof(struct rk3399_clk_plat), 1070 #endif 1071 }; 1072 1073 static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id) 1074 { 1075 u32 div, con; 1076 1077 switch (clk_id) { 1078 case SCLK_I2C0_PMU: 1079 con = readl(&pmucru->pmucru_clksel[2]); 1080 div = I2C_CLK_DIV_VALUE(con, 0); 1081 break; 1082 case SCLK_I2C4_PMU: 1083 con = readl(&pmucru->pmucru_clksel[3]); 1084 div = I2C_CLK_DIV_VALUE(con, 4); 1085 break; 1086 case SCLK_I2C8_PMU: 1087 con = readl(&pmucru->pmucru_clksel[2]); 1088 div = I2C_CLK_DIV_VALUE(con, 8); 1089 break; 1090 default: 1091 printf("do not support this i2c bus\n"); 1092 return -EINVAL; 1093 } 1094 1095 return DIV_TO_RATE(PPLL_HZ, div); 1096 } 1097 1098 static ulong rk3399_i2c_set_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id, 1099 uint hz) 1100 { 1101 int src_clk_div; 1102 1103 src_clk_div = PPLL_HZ / hz; 1104 assert(src_clk_div - 1 < 127); 1105 1106 switch (clk_id) { 1107 case SCLK_I2C0_PMU: 1108 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(0), 1109 I2C_PMUCLK_REG_VALUE(0, src_clk_div)); 1110 break; 1111 case SCLK_I2C4_PMU: 1112 rk_clrsetreg(&pmucru->pmucru_clksel[3], I2C_PMUCLK_REG_MASK(4), 1113 I2C_PMUCLK_REG_VALUE(4, src_clk_div)); 1114 break; 1115 case SCLK_I2C8_PMU: 1116 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(8), 1117 I2C_PMUCLK_REG_VALUE(8, src_clk_div)); 1118 break; 1119 default: 1120 printf("do not support this i2c bus\n"); 1121 return -EINVAL; 1122 } 1123 1124 return DIV_TO_RATE(PPLL_HZ, src_clk_div); 1125 } 1126 1127 static ulong rk3399_pwm_get_clk(struct rk3399_pmucru *pmucru) 1128 { 1129 u32 div, con; 1130 1131 /* PWM closk rate is same as pclk_pmu */ 1132 con = readl(&pmucru->pmucru_clksel[0]); 1133 div = con & PMU_PCLK_DIV_CON_MASK; 1134 1135 return DIV_TO_RATE(PPLL_HZ, div); 1136 } 1137 1138 static ulong rk3399_pmuclk_get_rate(struct clk *clk) 1139 { 1140 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev); 1141 ulong rate = 0; 1142 1143 switch (clk->id) { 1144 case PCLK_RKPWM_PMU: 1145 rate = rk3399_pwm_get_clk(priv->pmucru); 1146 break; 1147 case SCLK_I2C0_PMU: 1148 case SCLK_I2C4_PMU: 1149 case SCLK_I2C8_PMU: 1150 rate = rk3399_i2c_get_pmuclk(priv->pmucru, clk->id); 1151 break; 1152 default: 1153 return -ENOENT; 1154 } 1155 1156 return rate; 1157 } 1158 1159 static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate) 1160 { 1161 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev); 1162 ulong ret = 0; 1163 1164 switch (clk->id) { 1165 case SCLK_I2C0_PMU: 1166 case SCLK_I2C4_PMU: 1167 case SCLK_I2C8_PMU: 1168 ret = rk3399_i2c_set_pmuclk(priv->pmucru, clk->id, rate); 1169 break; 1170 default: 1171 return -ENOENT; 1172 } 1173 1174 return ret; 1175 } 1176 1177 static struct clk_ops rk3399_pmuclk_ops = { 1178 .get_rate = rk3399_pmuclk_get_rate, 1179 .set_rate = rk3399_pmuclk_set_rate, 1180 }; 1181 1182 #ifndef CONFIG_SPL_BUILD 1183 static void pmuclk_init(struct rk3399_pmucru *pmucru) 1184 { 1185 u32 pclk_div; 1186 1187 /* configure pmu pll(ppll) */ 1188 rkclk_set_pll(&pmucru->ppll_con[0], &ppll_init_cfg); 1189 1190 /* configure pmu pclk */ 1191 pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1; 1192 rk_clrsetreg(&pmucru->pmucru_clksel[0], 1193 PMU_PCLK_DIV_CON_MASK, 1194 pclk_div << PMU_PCLK_DIV_CON_SHIFT); 1195 } 1196 #endif 1197 1198 static int rk3399_pmuclk_probe(struct udevice *dev) 1199 { 1200 #if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_SPL_BUILD) 1201 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); 1202 #endif 1203 1204 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1205 struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev); 1206 1207 priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); 1208 #endif 1209 1210 #ifndef CONFIG_SPL_BUILD 1211 pmuclk_init(priv->pmucru); 1212 #endif 1213 return 0; 1214 } 1215 1216 static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev) 1217 { 1218 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 1219 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); 1220 1221 priv->pmucru = (struct rk3399_pmucru *)devfdt_get_addr(dev); 1222 #endif 1223 return 0; 1224 } 1225 1226 static int rk3399_pmuclk_bind(struct udevice *dev) 1227 { 1228 int ret = 0; 1229 struct udevice *sf_child; 1230 struct softreset_reg *sf_priv = malloc(sizeof(struct softreset_reg)); 1231 1232 ret = device_bind_driver_to_node(dev, "rockchip_reset", 1233 "reset", dev_ofnode(dev), 1234 &sf_child); 1235 if (ret) 1236 debug("Warning: No rockchip reset driver: ret=%d\n", ret); 1237 1238 sf_priv->sf_reset_offset = offsetof(struct rk3399_pmucru, 1239 pmucru_softrst_con[0]); 1240 sf_priv->sf_reset_num = 2; 1241 sf_child->priv = sf_priv; 1242 1243 return ret; 1244 } 1245 1246 static const struct udevice_id rk3399_pmuclk_ids[] = { 1247 { .compatible = "rockchip,rk3399-pmucru" }, 1248 { } 1249 }; 1250 1251 U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = { 1252 .name = "rockchip_rk3399_pmucru", 1253 .id = UCLASS_CLK, 1254 .of_match = rk3399_pmuclk_ids, 1255 .priv_auto_alloc_size = sizeof(struct rk3399_pmuclk_priv), 1256 .ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata, 1257 .ops = &rk3399_pmuclk_ops, 1258 .probe = rk3399_pmuclk_probe, 1259 .bind = rk3399_pmuclk_bind, 1260 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1261 .platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat), 1262 #endif 1263 }; 1264