1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <bitfield.h> 9 #include <clk-uclass.h> 10 #include <dm.h> 11 #include <dt-structs.h> 12 #include <errno.h> 13 #include <mapmem.h> 14 #include <syscon.h> 15 #include <asm/io.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/cru_rk3288.h> 18 #include <asm/arch/grf_rk3288.h> 19 #include <asm/arch/hardware.h> 20 #include <dt-bindings/clock/rk3288-cru.h> 21 #include <dm/device-internal.h> 22 #include <dm/lists.h> 23 #include <dm/uclass-internal.h> 24 #include <linux/log2.h> 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 struct rk3288_clk_plat { 29 #if CONFIG_IS_ENABLED(OF_PLATDATA) 30 struct dtd_rockchip_rk3288_cru dtd; 31 #endif 32 }; 33 34 struct pll_div { 35 ulong rate; 36 u32 nr; 37 u32 nf; 38 u32 no; 39 u32 nb; 40 }; 41 42 #define RK3288_PLL_RATE(_rate, _nr, _nf, _no, _nb) \ 43 { \ 44 .rate = _rate##U, \ 45 .nr = _nr, \ 46 .nf = _nf, \ 47 .no = _no, \ 48 .nb = _nb, \ 49 } 50 51 static struct pll_div rk3288_pll_rates[] = { 52 /* _mhz, _nr, _nf, _no, _nb */ 53 RK3288_PLL_RATE(1188000000, 1, 99, 2, 16), 54 RK3288_PLL_RATE(594000000, 1, 99, 4, 16), 55 RK3288_PLL_RATE(297000000, 1, 99, 8, 16), 56 }; 57 58 #ifndef CONFIG_SPL_BUILD 59 #define RK3288_CLK_DUMP(_id, _name, _iscru) \ 60 { \ 61 .id = _id, \ 62 .name = _name, \ 63 .is_cru = _iscru, \ 64 } 65 66 static const struct rk3288_clk_info clks_dump[] = { 67 RK3288_CLK_DUMP(PLL_APLL, "apll", true), 68 RK3288_CLK_DUMP(PLL_DPLL, "dpll", true), 69 RK3288_CLK_DUMP(PLL_CPLL, "cpll", true), 70 RK3288_CLK_DUMP(PLL_GPLL, "gpll", true), 71 RK3288_CLK_DUMP(PLL_NPLL, "npll", true), 72 RK3288_CLK_DUMP(ACLK_CPU, "aclk_bus", true), 73 }; 74 #endif 75 76 enum { 77 VCO_MAX_HZ = 2200U * 1000000, 78 VCO_MIN_HZ = 440 * 1000000, 79 OUTPUT_MAX_HZ = 2200U * 1000000, 80 OUTPUT_MIN_HZ = 27500000, 81 FREF_MAX_HZ = 2200U * 1000000, 82 FREF_MIN_HZ = 269 * 1000, 83 }; 84 85 enum { 86 /* PLL CON0 */ 87 PLL_OD_MASK = 0x0f, 88 89 /* PLL CON1 */ 90 PLL_NF_MASK = 0x1fff, 91 92 /* PLL CON2 */ 93 PLL_BWADJ_MASK = 0x0fff, 94 95 /* PLL CON3 */ 96 PLL_RESET_SHIFT = 5, 97 98 /* CLKSEL0 */ 99 CORE_SEL_PLL_SHIFT = 15, 100 CORE_SEL_PLL_MASK = 1 << CORE_SEL_PLL_SHIFT, 101 A17_DIV_SHIFT = 8, 102 A17_DIV_MASK = 0x1f << A17_DIV_SHIFT, 103 MP_DIV_SHIFT = 4, 104 MP_DIV_MASK = 0xf << MP_DIV_SHIFT, 105 M0_DIV_SHIFT = 0, 106 M0_DIV_MASK = 0xf << M0_DIV_SHIFT, 107 108 /* CLKSEL1: pd bus clk pll sel: codec or general */ 109 PD_BUS_SEL_PLL_SHIFT = 15, 110 PD_BUS_SEL_PLL_MASK = 1 << PD_BUS_SEL_PLL_SHIFT, 111 PD_BUS_SEL_CPLL = 0, 112 PD_BUS_SEL_GPLL, 113 114 /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */ 115 PD_BUS_PCLK_DIV_SHIFT = 12, 116 PD_BUS_PCLK_DIV_MASK = 7 << PD_BUS_PCLK_DIV_SHIFT, 117 118 /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */ 119 PD_BUS_HCLK_DIV_SHIFT = 8, 120 PD_BUS_HCLK_DIV_MASK = 3 << PD_BUS_HCLK_DIV_SHIFT, 121 122 /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */ 123 PD_BUS_ACLK_DIV0_SHIFT = 3, 124 PD_BUS_ACLK_DIV0_MASK = 0x1f << PD_BUS_ACLK_DIV0_SHIFT, 125 PD_BUS_ACLK_DIV1_SHIFT = 0, 126 PD_BUS_ACLK_DIV1_MASK = 0x7 << PD_BUS_ACLK_DIV1_SHIFT, 127 128 /* CLKSEL2: tsadc */ 129 CLK_TSADC_DIV_CON_SHIFT = 0, 130 CLK_TSADC_DIV_CON_MASK = GENMASK(5, 0), 131 CLK_TSADC_DIV_CON_WIDTH = 6, 132 133 /* 134 * CLKSEL10 135 * peripheral bus pclk div: 136 * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1 137 */ 138 PERI_SEL_PLL_SHIFT = 15, 139 PERI_SEL_PLL_MASK = 1 << PERI_SEL_PLL_SHIFT, 140 PERI_SEL_CPLL = 0, 141 PERI_SEL_GPLL, 142 143 PERI_PCLK_DIV_SHIFT = 12, 144 PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT, 145 146 /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */ 147 PERI_HCLK_DIV_SHIFT = 8, 148 PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, 149 150 /* 151 * peripheral bus aclk div: 152 * aclk_periph = periph_clk_src / (peri_aclk_div_con + 1) 153 */ 154 PERI_ACLK_DIV_SHIFT = 0, 155 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, 156 157 /* 158 * CLKSEL24 159 * saradc_div_con: 160 * clk_saradc=24MHz/(saradc_div_con+1) 161 */ 162 CLK_SARADC_DIV_CON_SHIFT = 8, 163 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8), 164 CLK_SARADC_DIV_CON_WIDTH = 8, 165 166 /* CLKSEL26 */ 167 CLK_CRYPTO_DIV_CON_SHIFT = 6, 168 CLK_CRYPTO_DIV_CON_MASK = GENMASK(7, 6), 169 170 /* CLKSEL33 */ 171 PCLK_ALIVE_DIV_CON_SHIFT = 8, 172 PCLK_ALIVE_DIV_CON_MASK = 0x1f << PCLK_ALIVE_DIV_CON_SHIFT, 173 174 /* CLKSEL39 */ 175 ACLK_HEVC_SEL_PLL_SHIFT = 14, 176 ACLK_HEVC_SEL_PLL_MASK = 0x3 << ACLK_HEVC_SEL_PLL_SHIFT, 177 ACLK_HEVC_SEL_CPLL = 0, 178 ACLK_HEVC_SEL_GPLL, 179 ACLK_HEVC_DIV_CON_SHIFT = 8, 180 ACLK_HEVC_DIV_CON_MASK = 0x1f << ACLK_HEVC_DIV_CON_SHIFT, 181 182 /* CLKSEL42 */ 183 CLK_HEVC_CORE_SEL_PLL_SHIFT = 14, 184 CLK_HEVC_CORE_SEL_PLL_MASK = 0x3 << CLK_HEVC_CORE_SEL_PLL_SHIFT, 185 CLK_HEVC_CORE_SEL_CPLL = 0, 186 CLK_HEVC_CORE_SEL_GPLL, 187 CLK_HEVC_CORE_DIV_CON_SHIFT = 8, 188 CLK_HEVC_CORE_DIV_CON_MASK = 0x1f << CLK_HEVC_CORE_DIV_CON_SHIFT, 189 CLK_HEVC_CABAC_SEL_PLL_SHIFT = 6, 190 CLK_HEVC_CABAC_SEL_PLL_MASK = 0x3 << CLK_HEVC_CABAC_SEL_PLL_SHIFT, 191 CLK_HEVC_CABAC_SEL_CPLL = 0, 192 CLK_HEVC_CABAC_SEL_GPLL, 193 CLK_HEVC_CABAC_DIV_CON_SHIFT = 0, 194 CLK_HEVC_CABAC_DIV_CON_MASK = 0x1f << CLK_HEVC_CABAC_DIV_CON_SHIFT, 195 196 SOCSTS_DPLL_LOCK = 1 << 5, 197 SOCSTS_APLL_LOCK = 1 << 6, 198 SOCSTS_CPLL_LOCK = 1 << 7, 199 SOCSTS_GPLL_LOCK = 1 << 8, 200 SOCSTS_NPLL_LOCK = 1 << 9, 201 }; 202 203 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 204 205 #define PLL_DIVISORS(hz, _nr, _no) {\ 206 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\ 207 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\ 208 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\ 209 "divisors on line " __stringify(__LINE__)); 210 211 /* Keep divisors as low as possible to reduce jitter and power usage */ 212 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1); 213 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 4); 214 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2); 215 216 struct pll_div *rkclk_get_pll_config(ulong freq_hz) 217 { 218 unsigned int rate_count = ARRAY_SIZE(rk3288_pll_rates); 219 int i; 220 221 for (i = 0; i < rate_count; i++) { 222 if (freq_hz == rk3288_pll_rates[i].rate) 223 return &rk3288_pll_rates[i]; 224 } 225 return NULL; 226 } 227 228 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id, 229 const struct pll_div *div) 230 { 231 int pll_id = rk_pll_id(clk_id); 232 struct rk3288_pll *pll = &cru->pll[pll_id]; 233 /* All PLLs have same VCO and output frequency range restrictions. */ 234 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; 235 uint output_hz = vco_hz / div->no; 236 237 debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n", 238 (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz); 239 240 /* enter reset */ 241 rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT); 242 243 rk_clrsetreg(&pll->con0, CLKR_MASK | PLL_OD_MASK, 244 ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1)); 245 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); 246 247 /* adjust pll bw for better clock jitter */ 248 if (div->nb) 249 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, div->nb - 1); 250 else 251 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); 252 253 udelay(10); 254 255 /* return from reset */ 256 rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT); 257 258 return 0; 259 } 260 261 /* Get pll rate by id */ 262 static u32 rkclk_pll_get_rate(struct rk3288_cru *cru, 263 enum rk_clk_id clk_id) 264 { 265 u32 nr, no, nf; 266 u32 con; 267 int pll_id = rk_pll_id(clk_id); 268 struct rk3288_pll *pll = &cru->pll[pll_id]; 269 static u8 clk_shift[CLK_COUNT] = { 270 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, 271 GPLL_MODE_SHIFT, NPLL_MODE_SHIFT 272 }; 273 uint shift; 274 275 con = readl(&cru->cru_mode_con); 276 shift = clk_shift[clk_id]; 277 switch ((con >> shift) & CRU_MODE_MASK) { 278 case APLL_MODE_SLOW: 279 return OSC_HZ; 280 case APLL_MODE_NORMAL: 281 /* normal mode */ 282 con = readl(&pll->con0); 283 no = ((con & CLKOD_MASK) >> CLKOD_SHIFT) + 1; 284 nr = ((con & CLKR_MASK) >> CLKR_SHIFT) + 1; 285 con = readl(&pll->con1); 286 nf = ((con & CLKF_MASK) >> CLKF_SHIFT) + 1; 287 288 return (24 * nf / (nr * no)) * 1000000; 289 case APLL_MODE_DEEP: 290 default: 291 return 32768; 292 } 293 } 294 295 static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf, 296 unsigned int hz) 297 { 298 static const struct pll_div dpll_cfg[] = { 299 {.nf = 25, .nr = 2, .no = 1}, 300 {.nf = 400, .nr = 9, .no = 2}, 301 {.nf = 500, .nr = 9, .no = 2}, 302 {.nf = 100, .nr = 3, .no = 1}, 303 }; 304 int cfg; 305 306 switch (hz) { 307 case 300000000: 308 cfg = 0; 309 break; 310 case 533000000: /* actually 533.3P MHz */ 311 cfg = 1; 312 break; 313 case 666000000: /* actually 666.6P MHz */ 314 cfg = 2; 315 break; 316 case 800000000: 317 cfg = 3; 318 break; 319 default: 320 debug("Unsupported SDRAM frequency"); 321 return -EINVAL; 322 } 323 324 /* pll enter slow-mode */ 325 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, 326 DPLL_MODE_SLOW << DPLL_MODE_SHIFT); 327 328 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]); 329 330 /* wait for pll lock */ 331 while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK)) 332 udelay(1); 333 334 /* PLL enter normal-mode */ 335 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, 336 DPLL_MODE_NORMAL << DPLL_MODE_SHIFT); 337 338 return 0; 339 } 340 341 #ifndef CONFIG_SPL_BUILD 342 #define VCO_MAX_KHZ 2200000 343 #define VCO_MIN_KHZ 440000 344 #define FREF_MAX_KHZ 2200000 345 #define FREF_MIN_KHZ 269 346 #define PLL_LIMIT_FREQ 594000000 347 348 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div) 349 { 350 struct pll_div *best_div = NULL; 351 uint ref_khz = OSC_HZ / 1000, nr, nf = 0; 352 uint fref_khz; 353 uint diff_khz, best_diff_khz; 354 const uint max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4; 355 uint vco_khz; 356 uint no = 1; 357 uint freq_khz = freq_hz / 1000; 358 359 if (!freq_hz) { 360 printf("%s: the frequency can not be 0 Hz\n", __func__); 361 return -EINVAL; 362 } 363 364 no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz); 365 if (ext_div) { 366 *ext_div = DIV_ROUND_UP(PLL_LIMIT_FREQ, freq_hz); 367 no = DIV_ROUND_UP(no, *ext_div); 368 } 369 370 best_div = rkclk_get_pll_config(freq_hz * (*ext_div)); 371 if (best_div) { 372 div->nr = best_div->nr; 373 div->nf = best_div->nf; 374 div->no = best_div->no; 375 div->nb = best_div->nb; 376 return 0; 377 } 378 379 /* only even divisors (and 1) are supported */ 380 if (no > 1) 381 no = DIV_ROUND_UP(no, 2) * 2; 382 383 vco_khz = freq_khz * no; 384 if (ext_div) 385 vco_khz *= *ext_div; 386 387 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) { 388 printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n", 389 __func__, freq_hz); 390 return -1; 391 } 392 393 div->no = no; 394 395 best_diff_khz = vco_khz; 396 for (nr = 1; nr < max_nr && best_diff_khz; nr++) { 397 fref_khz = ref_khz / nr; 398 if (fref_khz < FREF_MIN_KHZ) 399 break; 400 if (fref_khz > FREF_MAX_KHZ) 401 continue; 402 403 nf = vco_khz / fref_khz; 404 if (nf >= max_nf) 405 continue; 406 diff_khz = vco_khz - nf * fref_khz; 407 if (nf + 1 < max_nf && diff_khz > fref_khz / 2) { 408 nf++; 409 diff_khz = fref_khz - diff_khz; 410 } 411 412 if (diff_khz >= best_diff_khz) 413 continue; 414 415 best_diff_khz = diff_khz; 416 div->nr = nr; 417 div->nf = nf; 418 } 419 420 if (best_diff_khz > 4 * 1000) { 421 printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n", 422 __func__, freq_hz, best_diff_khz * 1000); 423 return -EINVAL; 424 } 425 426 return 0; 427 } 428 429 static int rockchip_mac_set_clk(struct rk3288_cru *cru, uint freq) 430 { 431 ulong ret; 432 433 /* 434 * The gmac clock can be derived either from an external clock 435 * or can be generated from internally by a divider from SCLK_MAC. 436 */ 437 if (readl(&cru->cru_clksel_con[21]) & RMII_EXTCLK_MASK) { 438 /* An external clock will always generate the right rate... */ 439 ret = freq; 440 } else { 441 u32 con = readl(&cru->cru_clksel_con[21]); 442 ulong pll_rate; 443 u8 div; 444 445 if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) == 446 EMAC_PLL_SELECT_GENERAL) 447 pll_rate = GPLL_HZ; 448 else if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) == 449 EMAC_PLL_SELECT_CODEC) 450 pll_rate = CPLL_HZ; 451 else 452 pll_rate = NPLL_HZ; 453 454 div = DIV_ROUND_UP(pll_rate, freq) - 1; 455 if (div <= 0x1f) 456 rk_clrsetreg(&cru->cru_clksel_con[21], MAC_DIV_CON_MASK, 457 div << MAC_DIV_CON_SHIFT); 458 else 459 debug("Unsupported div for gmac:%d\n", div); 460 461 return DIV_TO_RATE(pll_rate, div); 462 } 463 464 return ret; 465 } 466 467 static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf, 468 int periph, unsigned int rate_hz) 469 { 470 struct pll_div cpll_config = {0}; 471 u32 lcdc_div, parent; 472 int ret; 473 unsigned int gpll_rate, npll_rate; 474 475 gpll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); 476 npll_rate = rkclk_pll_get_rate(cru, CLK_NEW); 477 478 /* vop dclk source clk: cpll,dclk_div: 1 */ 479 switch (periph) { 480 case DCLK_VOP0: 481 ret = (readl(&cru->cru_clksel_con[27]) & DCLK_VOP0_PLL_MASK) >> 482 DCLK_VOP0_PLL_SHIFT; 483 if (ret == DCLK_VOP0_SELECT_CPLL) { 484 ret = pll_para_config(rate_hz, &cpll_config, &lcdc_div); 485 if (ret) 486 return ret; 487 488 rk_clrsetreg(&cru->cru_mode_con, CPLL_MODE_MASK, 489 CPLL_MODE_SLOW << CPLL_MODE_SHIFT); 490 rkclk_set_pll(cru, CLK_CODEC, &cpll_config); 491 492 /* waiting for pll lock */ 493 while (1) { 494 if (readl(&grf->soc_status[1]) & 495 SOCSTS_CPLL_LOCK) 496 break; 497 udelay(1); 498 } 499 500 rk_clrsetreg(&cru->cru_mode_con, CPLL_MODE_MASK, 501 CPLL_MODE_NORMAL << CPLL_MODE_SHIFT); 502 parent = DCLK_VOP0_SELECT_CPLL; 503 } else if (ret == DCLK_VOP0_SELECT_GPLL) { 504 parent = DCLK_VOP0_SELECT_GPLL; 505 lcdc_div = DIV_ROUND_UP(gpll_rate, 506 rate_hz); 507 } else { 508 parent = DCLK_VOP0_SELECT_NPLL; 509 lcdc_div = DIV_ROUND_UP(npll_rate, 510 rate_hz); 511 } 512 rk_clrsetreg(&cru->cru_clksel_con[27], 513 DCLK_VOP0_DIV_MASK | DCLK_VOP0_PLL_MASK, 514 ((lcdc_div - 1) << DCLK_VOP0_DIV_SHIFT) | 515 (parent << DCLK_VOP0_PLL_SHIFT)); 516 break; 517 case DCLK_VOP1: 518 ret = (readl(&cru->cru_clksel_con[29]) & DCLK_VOP1_PLL_MASK) >> 519 DCLK_VOP1_PLL_SHIFT; 520 if (ret == DCLK_VOP1_SELECT_CPLL) { 521 ret = pll_para_config(rate_hz, &cpll_config, &lcdc_div); 522 if (ret) 523 return ret; 524 525 rk_clrsetreg(&cru->cru_mode_con, CPLL_MODE_MASK, 526 CPLL_MODE_SLOW << CPLL_MODE_SHIFT); 527 rkclk_set_pll(cru, CLK_CODEC, &cpll_config); 528 529 /* waiting for pll lock */ 530 while (1) { 531 if (readl(&grf->soc_status[1]) & 532 SOCSTS_CPLL_LOCK) 533 break; 534 udelay(1); 535 } 536 537 rk_clrsetreg(&cru->cru_mode_con, CPLL_MODE_MASK, 538 CPLL_MODE_NORMAL << CPLL_MODE_SHIFT); 539 540 parent = DCLK_VOP1_SELECT_CPLL; 541 } else if (ret == DCLK_VOP1_SELECT_GPLL) { 542 parent = DCLK_VOP1_SELECT_GPLL; 543 lcdc_div = DIV_ROUND_UP(gpll_rate, 544 rate_hz); 545 } else { 546 parent = DCLK_VOP1_SELECT_NPLL; 547 lcdc_div = DIV_ROUND_UP(npll_rate, 548 rate_hz); 549 } 550 rk_clrsetreg(&cru->cru_clksel_con[29], 551 DCLK_VOP1_DIV_MASK | DCLK_VOP1_PLL_MASK, 552 ((lcdc_div - 1) << DCLK_VOP1_DIV_SHIFT) | 553 (parent << DCLK_VOP1_PLL_SHIFT)); 554 break; 555 case ACLK_VIO0: 556 lcdc_div = DIV_ROUND_UP(gpll_rate, rate_hz); 557 rk_clrsetreg(&cru->cru_clksel_con[31], 558 ACLK_VIO0_PLL_MASK | ACLK_VIO0_DIV_MASK, 559 ACLK_VIO_SELECT_GPLL << ACLK_VIO0_PLL_SHIFT | 560 (lcdc_div - 1) << ACLK_VIO0_DIV_SHIFT); 561 break; 562 case ACLK_VIO1: 563 lcdc_div = DIV_ROUND_UP(gpll_rate, rate_hz); 564 rk_clrsetreg(&cru->cru_clksel_con[31], 565 ACLK_VIO1_PLL_MASK | ACLK_VIO1_DIV_MASK, 566 ACLK_VIO_SELECT_GPLL << ACLK_VIO1_PLL_SHIFT | 567 (lcdc_div - 1) << ACLK_VIO1_DIV_SHIFT); 568 569 lcdc_div = DIV_ROUND_UP(rate_hz, HCLK_VIO_HZ); 570 rk_clrsetreg(&cru->cru_clksel_con[28], 571 HCLK_VIO_DIV_MASK, 572 (lcdc_div - 1) << HCLK_VIO_DIV_SHIFT); 573 break; 574 } 575 576 return 0; 577 } 578 #endif /* CONFIG_SPL_BUILD */ 579 580 static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) 581 { 582 u32 aclk_div; 583 u32 hclk_div; 584 u32 pclk_div; 585 586 /* pll enter slow-mode */ 587 rk_clrsetreg(&cru->cru_mode_con, 588 GPLL_MODE_MASK | CPLL_MODE_MASK, 589 GPLL_MODE_SLOW << GPLL_MODE_SHIFT | 590 CPLL_MODE_SLOW << CPLL_MODE_SHIFT); 591 592 /* init pll */ 593 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); 594 rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg); 595 596 /* waiting for pll lock */ 597 while ((readl(&grf->soc_status[1]) & 598 (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) != 599 (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) 600 udelay(1); 601 602 /* 603 * pd_bus clock pll source selection and 604 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 605 */ 606 aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1; 607 assert((aclk_div + 1) * PD_BUS_ACLK_HZ <= GPLL_HZ && aclk_div <= 0x1f); 608 hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1; 609 assert((hclk_div + 1) * PD_BUS_HCLK_HZ <= 610 PD_BUS_ACLK_HZ && (hclk_div <= 0x3) && (hclk_div != 0x2)); 611 612 pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1; 613 assert((pclk_div + 1) * PD_BUS_PCLK_HZ <= 614 PD_BUS_ACLK_HZ && pclk_div <= 0x7); 615 616 rk_clrsetreg(&cru->cru_clksel_con[1], 617 PD_BUS_PCLK_DIV_MASK | PD_BUS_HCLK_DIV_MASK | 618 PD_BUS_ACLK_DIV0_MASK | PD_BUS_ACLK_DIV1_MASK, 619 pclk_div << PD_BUS_PCLK_DIV_SHIFT | 620 hclk_div << PD_BUS_HCLK_DIV_SHIFT | 621 aclk_div << PD_BUS_ACLK_DIV0_SHIFT | 622 0 << 0); 623 624 /* 625 * peri clock pll source selection and 626 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 627 */ 628 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; 629 assert((aclk_div + 1) * PERI_ACLK_HZ <= GPLL_HZ && aclk_div <= 0x1f); 630 631 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); 632 assert((1 << hclk_div) * PERI_HCLK_HZ <= 633 PERI_ACLK_HZ && (hclk_div <= 0x2)); 634 635 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); 636 assert((1 << pclk_div) * PERI_PCLK_HZ <= 637 PERI_ACLK_HZ && (pclk_div <= 0x3)); 638 639 rk_clrsetreg(&cru->cru_clksel_con[10], 640 PERI_PCLK_DIV_MASK | PERI_HCLK_DIV_MASK | 641 PERI_ACLK_DIV_MASK, 642 PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT | 643 pclk_div << PERI_PCLK_DIV_SHIFT | 644 hclk_div << PERI_HCLK_DIV_SHIFT | 645 aclk_div << PERI_ACLK_DIV_SHIFT); 646 647 rk_clrsetreg(&cru->cru_clksel_con[39], 648 ACLK_HEVC_SEL_PLL_MASK | ACLK_HEVC_DIV_CON_MASK, 649 ACLK_HEVC_SEL_CPLL << ACLK_HEVC_SEL_PLL_SHIFT | 650 4 << ACLK_HEVC_DIV_CON_SHIFT); 651 rk_clrsetreg(&cru->cru_clksel_con[42], 652 CLK_HEVC_CORE_SEL_PLL_MASK | CLK_HEVC_CORE_DIV_CON_MASK | 653 CLK_HEVC_CORE_SEL_PLL_MASK | CLK_HEVC_CORE_DIV_CON_MASK, 654 CLK_HEVC_CORE_SEL_CPLL << CLK_HEVC_CORE_SEL_PLL_SHIFT | 655 CLK_HEVC_CABAC_SEL_CPLL << CLK_HEVC_CABAC_DIV_CON_SHIFT | 656 4 << CLK_HEVC_CORE_DIV_CON_SHIFT | 657 4 << CLK_HEVC_CABAC_DIV_CON_SHIFT); 658 659 /* PLL enter normal-mode */ 660 rk_clrsetreg(&cru->cru_mode_con, 661 GPLL_MODE_MASK | CPLL_MODE_MASK, 662 GPLL_MODE_NORMAL << GPLL_MODE_SHIFT | 663 CPLL_MODE_NORMAL << CPLL_MODE_SHIFT); 664 } 665 666 void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf) 667 { 668 /* pll enter slow-mode */ 669 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, 670 APLL_MODE_SLOW << APLL_MODE_SHIFT); 671 672 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); 673 674 /* waiting for pll lock */ 675 while (!(readl(&grf->soc_status[1]) & SOCSTS_APLL_LOCK)) 676 udelay(1); 677 678 /* 679 * core clock pll source selection and 680 * set up dependent divisors for MPAXI/M0AXI and ARM clocks. 681 * core clock select apll, apll clk = 1800MHz 682 * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz 683 */ 684 rk_clrsetreg(&cru->cru_clksel_con[0], 685 CORE_SEL_PLL_MASK | A17_DIV_MASK | MP_DIV_MASK | 686 M0_DIV_MASK, 687 0 << A17_DIV_SHIFT | 688 3 << MP_DIV_SHIFT | 689 1 << M0_DIV_SHIFT); 690 691 /* 692 * set up dependent divisors for L2RAM/ATCLK and PCLK clocks. 693 * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz 694 */ 695 rk_clrsetreg(&cru->cru_clksel_con[37], 696 CLK_L2RAM_DIV_MASK | ATCLK_CORE_DIV_CON_MASK | 697 PCLK_CORE_DBG_DIV_MASK, 698 1 << CLK_L2RAM_DIV_SHIFT | 699 3 << ATCLK_CORE_DIV_CON_SHIFT | 700 3 << PCLK_CORE_DBG_DIV_SHIFT); 701 702 /* PLL enter normal-mode */ 703 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, 704 APLL_MODE_NORMAL << APLL_MODE_SHIFT); 705 } 706 707 static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate, 708 int periph) 709 { 710 uint src_rate; 711 uint div, mux; 712 u32 con; 713 714 switch (periph) { 715 case HCLK_EMMC: 716 case SCLK_EMMC: 717 case SCLK_EMMC_SAMPLE: 718 con = readl(&cru->cru_clksel_con[12]); 719 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; 720 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; 721 break; 722 case HCLK_SDMMC: 723 case SCLK_SDMMC: 724 con = readl(&cru->cru_clksel_con[11]); 725 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT; 726 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT; 727 break; 728 case HCLK_SDIO0: 729 case SCLK_SDIO0: 730 con = readl(&cru->cru_clksel_con[12]); 731 mux = (con & SDIO0_PLL_MASK) >> SDIO0_PLL_SHIFT; 732 div = (con & SDIO0_DIV_MASK) >> SDIO0_DIV_SHIFT; 733 break; 734 default: 735 return -EINVAL; 736 } 737 738 src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate; 739 return DIV_TO_RATE(src_rate, div) / 2; 740 } 741 742 static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate, 743 int periph, uint freq) 744 { 745 int src_clk_div; 746 int mux; 747 748 debug("%s: gclk_rate=%u\n", __func__, gclk_rate); 749 /* mmc clock default div 2 internal, need provide double in cru */ 750 src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq); 751 752 if (src_clk_div > 0x3f) { 753 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); 754 assert(src_clk_div < 0x40); 755 mux = EMMC_PLL_SELECT_24MHZ; 756 assert((int)EMMC_PLL_SELECT_24MHZ == 757 (int)MMC0_PLL_SELECT_24MHZ); 758 } else { 759 mux = EMMC_PLL_SELECT_GENERAL; 760 assert((int)EMMC_PLL_SELECT_GENERAL == 761 (int)MMC0_PLL_SELECT_GENERAL); 762 } 763 switch (periph) { 764 case HCLK_EMMC: 765 case SCLK_EMMC: 766 rk_clrsetreg(&cru->cru_clksel_con[12], 767 EMMC_PLL_MASK | EMMC_DIV_MASK, 768 mux << EMMC_PLL_SHIFT | 769 (src_clk_div - 1) << EMMC_DIV_SHIFT); 770 break; 771 case HCLK_SDMMC: 772 case SCLK_SDMMC: 773 rk_clrsetreg(&cru->cru_clksel_con[11], 774 MMC0_PLL_MASK | MMC0_DIV_MASK, 775 mux << MMC0_PLL_SHIFT | 776 (src_clk_div - 1) << MMC0_DIV_SHIFT); 777 break; 778 case HCLK_SDIO0: 779 case SCLK_SDIO0: 780 rk_clrsetreg(&cru->cru_clksel_con[12], 781 SDIO0_PLL_MASK | SDIO0_DIV_MASK, 782 mux << SDIO0_PLL_SHIFT | 783 (src_clk_div - 1) << SDIO0_DIV_SHIFT); 784 break; 785 default: 786 return -EINVAL; 787 } 788 789 return rockchip_mmc_get_clk(cru, gclk_rate, periph); 790 } 791 792 static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate, 793 int periph) 794 { 795 uint div, mux; 796 u32 con; 797 798 switch (periph) { 799 case SCLK_SPI0: 800 con = readl(&cru->cru_clksel_con[25]); 801 mux = (con & SPI0_PLL_MASK) >> SPI0_PLL_SHIFT; 802 div = (con & SPI0_DIV_MASK) >> SPI0_DIV_SHIFT; 803 break; 804 case SCLK_SPI1: 805 con = readl(&cru->cru_clksel_con[25]); 806 mux = (con & SPI1_PLL_MASK) >> SPI1_PLL_SHIFT; 807 div = (con & SPI1_DIV_MASK) >> SPI1_DIV_SHIFT; 808 break; 809 case SCLK_SPI2: 810 con = readl(&cru->cru_clksel_con[39]); 811 mux = (con & SPI2_PLL_MASK) >> SPI2_PLL_SHIFT; 812 div = (con & SPI2_DIV_MASK) >> SPI2_DIV_SHIFT; 813 break; 814 default: 815 return -EINVAL; 816 } 817 assert(mux == SPI0_PLL_SELECT_GENERAL); 818 819 return DIV_TO_RATE(gclk_rate, div); 820 } 821 822 static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate, 823 int periph, uint freq) 824 { 825 int src_clk_div; 826 827 debug("%s: clk_general_rate=%u\n", __func__, gclk_rate); 828 src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1; 829 assert(src_clk_div < 128); 830 switch (periph) { 831 case SCLK_SPI0: 832 rk_clrsetreg(&cru->cru_clksel_con[25], 833 SPI0_PLL_MASK | SPI0_DIV_MASK, 834 SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT | 835 src_clk_div << SPI0_DIV_SHIFT); 836 break; 837 case SCLK_SPI1: 838 rk_clrsetreg(&cru->cru_clksel_con[25], 839 SPI1_PLL_MASK | SPI1_DIV_MASK, 840 SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT | 841 src_clk_div << SPI1_DIV_SHIFT); 842 break; 843 case SCLK_SPI2: 844 rk_clrsetreg(&cru->cru_clksel_con[39], 845 SPI2_PLL_MASK | SPI2_DIV_MASK, 846 SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT | 847 src_clk_div << SPI2_DIV_SHIFT); 848 break; 849 default: 850 return -EINVAL; 851 } 852 853 return rockchip_spi_get_clk(cru, gclk_rate, periph); 854 } 855 856 static ulong rockchip_aclk_peri_get_clk(struct rk3288_cru *cru) 857 { 858 uint div, mux; 859 u32 con; 860 ulong rate, parent_rate; 861 862 con = readl(&cru->cru_clksel_con[10]); 863 mux = (con & PERI_SEL_PLL_MASK) >> PERI_SEL_PLL_SHIFT; 864 div = (con & PERI_ACLK_DIV_MASK) >> PERI_ACLK_DIV_SHIFT; 865 if (mux) 866 parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); 867 else 868 parent_rate = rkclk_pll_get_rate(cru, CLK_CODEC); 869 rate = DIV_TO_RATE(parent_rate, div); 870 871 return rate; 872 } 873 874 static ulong rockchip_aclk_cpu_get_clk(struct rk3288_cru *cru) 875 { 876 uint div, mux; 877 u32 con; 878 ulong rate, parent_rate; 879 880 con = readl(&cru->cru_clksel_con[1]); 881 mux = (con & PD_BUS_SEL_PLL_MASK) >> PD_BUS_SEL_PLL_SHIFT; 882 div = (con & PD_BUS_ACLK_DIV0_MASK) >> PD_BUS_ACLK_DIV0_SHIFT; 883 if (mux) 884 parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); 885 else 886 parent_rate = rkclk_pll_get_rate(cru, CLK_CODEC); 887 parent_rate = DIV_TO_RATE(parent_rate, div); 888 889 div = (con & PD_BUS_ACLK_DIV1_MASK) >> PD_BUS_ACLK_DIV1_SHIFT; 890 rate = DIV_TO_RATE(parent_rate, div); 891 892 return rate; 893 } 894 895 static ulong rockchip_pclk_peri_get_clk(struct rk3288_cru *cru) 896 { 897 uint div; 898 u32 con; 899 ulong rate, parent_rate; 900 901 parent_rate = rockchip_aclk_peri_get_clk(cru); 902 con = readl(&cru->cru_clksel_con[10]); 903 div = (con & PERI_PCLK_DIV_MASK) >> PERI_PCLK_DIV_SHIFT; 904 rate = parent_rate / (1 << div); 905 906 return rate; 907 } 908 909 static ulong rockchip_pclk_cpu_get_clk(struct rk3288_cru *cru) 910 { 911 uint div; 912 u32 con; 913 ulong rate, parent_rate; 914 915 parent_rate = rockchip_aclk_cpu_get_clk(cru); 916 con = readl(&cru->cru_clksel_con[1]); 917 div = (con & PD_BUS_PCLK_DIV_MASK) >> PD_BUS_PCLK_DIV_SHIFT; 918 rate = DIV_TO_RATE(parent_rate, div); 919 920 return rate; 921 } 922 923 static ulong rockchip_i2c_get_clk(struct rk3288_cru *cru, int periph) 924 { 925 switch (periph) { 926 case PCLK_I2C0: 927 case PCLK_I2C2: 928 return rockchip_pclk_cpu_get_clk(cru); 929 case PCLK_I2C1: 930 case PCLK_I2C3: 931 case PCLK_I2C4: 932 case PCLK_I2C5: 933 return rockchip_pclk_peri_get_clk(cru); 934 default: 935 return -EINVAL; 936 } 937 } 938 939 static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru) 940 { 941 u32 div, val; 942 943 val = readl(&cru->cru_clksel_con[24]); 944 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT, 945 CLK_SARADC_DIV_CON_WIDTH); 946 947 return DIV_TO_RATE(OSC_HZ, div); 948 } 949 950 static ulong rockchip_saradc_set_clk(struct rk3288_cru *cru, uint hz) 951 { 952 int src_clk_div; 953 954 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; 955 assert(src_clk_div < 128); 956 957 rk_clrsetreg(&cru->cru_clksel_con[24], 958 CLK_SARADC_DIV_CON_MASK, 959 src_clk_div << CLK_SARADC_DIV_CON_SHIFT); 960 961 return rockchip_saradc_get_clk(cru); 962 } 963 964 static ulong rockchip_tsadc_get_clk(struct rk3288_cru *cru) 965 { 966 u32 div, val; 967 968 val = readl(&cru->cru_clksel_con[2]); 969 div = bitfield_extract(val, CLK_TSADC_DIV_CON_SHIFT, 970 CLK_TSADC_DIV_CON_WIDTH); 971 972 return DIV_TO_RATE(32768, div); 973 } 974 975 static ulong rockchip_tsadc_set_clk(struct rk3288_cru *cru, uint hz) 976 { 977 int src_clk_div; 978 979 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; 980 assert(src_clk_div < 128); 981 982 rk_clrsetreg(&cru->cru_clksel_con[2], 983 CLK_TSADC_DIV_CON_MASK, 984 src_clk_div << CLK_TSADC_DIV_CON_SHIFT); 985 986 return rockchip_tsadc_get_clk(cru); 987 } 988 989 #ifndef CONFIG_SPL_BUILD 990 991 static ulong rockchip_crypto_get_clk(struct rk3288_cru *cru) 992 { 993 u32 div, val; 994 995 val = readl(&cru->cru_clksel_con[26]); 996 div = (val & CLK_CRYPTO_DIV_CON_MASK) >> CLK_CRYPTO_DIV_CON_SHIFT; 997 998 return DIV_TO_RATE(rockchip_aclk_cpu_get_clk(cru), div); 999 } 1000 1001 static ulong rockchip_crypto_set_clk(struct rk3288_cru *cru, uint hz) 1002 { 1003 int src_clk_div; 1004 uint p_rate; 1005 1006 p_rate = rockchip_aclk_cpu_get_clk(cru); 1007 src_clk_div = DIV_ROUND_UP(p_rate, hz) - 1; 1008 assert(src_clk_div < 3); 1009 1010 rk_clrsetreg(&cru->cru_clksel_con[26], 1011 CLK_CRYPTO_DIV_CON_MASK, 1012 src_clk_div << CLK_CRYPTO_DIV_CON_SHIFT); 1013 1014 return rockchip_crypto_get_clk(cru); 1015 } 1016 1017 static ulong rk3288_alive_get_clk(struct rk3288_cru *cru, uint gclk_rate) 1018 { 1019 u32 div, con, parent; 1020 1021 con = readl(&cru->cru_clksel_con[33]); 1022 div = (con & PCLK_ALIVE_DIV_CON_MASK) >> 1023 PCLK_ALIVE_DIV_CON_SHIFT; 1024 parent = gclk_rate; 1025 return DIV_TO_RATE(parent, div); 1026 } 1027 #endif 1028 1029 static ulong rk3288_clk_get_rate(struct clk *clk) 1030 { 1031 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); 1032 ulong new_rate, gclk_rate; 1033 1034 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); 1035 switch (clk->id) { 1036 case 0 ... 63: 1037 new_rate = rkclk_pll_get_rate(priv->cru, clk->id); 1038 break; 1039 case HCLK_EMMC: 1040 case HCLK_SDMMC: 1041 case HCLK_SDIO0: 1042 case SCLK_EMMC: 1043 case SCLK_EMMC_SAMPLE: 1044 case SCLK_SDMMC: 1045 case SCLK_SDMMC_SAMPLE: 1046 case SCLK_SDIO0: 1047 new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id); 1048 break; 1049 case SCLK_SPI0: 1050 case SCLK_SPI1: 1051 case SCLK_SPI2: 1052 new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, clk->id); 1053 break; 1054 case PCLK_I2C0: 1055 case PCLK_I2C1: 1056 case PCLK_I2C2: 1057 case PCLK_I2C3: 1058 case PCLK_I2C4: 1059 case PCLK_I2C5: 1060 new_rate = rockchip_i2c_get_clk(priv->cru, clk->id); 1061 break; 1062 case PCLK_PWM: 1063 return PD_BUS_PCLK_HZ; 1064 case SCLK_SARADC: 1065 new_rate = rockchip_saradc_get_clk(priv->cru); 1066 break; 1067 case SCLK_TSADC: 1068 new_rate = rockchip_tsadc_get_clk(priv->cru); 1069 break; 1070 case ACLK_CPU: 1071 new_rate = rockchip_aclk_cpu_get_clk(priv->cru); 1072 break; 1073 case ACLK_PERI: 1074 new_rate = rockchip_aclk_peri_get_clk(priv->cru); 1075 break; 1076 case PCLK_CPU: 1077 new_rate = rockchip_pclk_cpu_get_clk(priv->cru); 1078 break; 1079 case PCLK_PERI: 1080 new_rate = rockchip_pclk_peri_get_clk(priv->cru); 1081 break; 1082 #ifndef CONFIG_SPL_BUILD 1083 case SCLK_CRYPTO: 1084 new_rate = rockchip_crypto_get_clk(priv->cru); 1085 break; 1086 case PCLK_WDT: 1087 new_rate = rk3288_alive_get_clk(priv->cru, gclk_rate); 1088 break; 1089 #endif 1090 default: 1091 return -ENOENT; 1092 } 1093 1094 return new_rate; 1095 } 1096 1097 static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate) 1098 { 1099 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); 1100 struct rk3288_cru *cru = priv->cru; 1101 ulong new_rate, gclk_rate; 1102 1103 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); 1104 switch (clk->id) { 1105 case PLL_APLL: 1106 /* We only support a fixed rate here */ 1107 if (rate != 1800000000) 1108 return -EINVAL; 1109 rk3288_clk_configure_cpu(priv->cru, priv->grf); 1110 new_rate = rate; 1111 break; 1112 case CLK_DDR: 1113 new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate); 1114 break; 1115 case HCLK_EMMC: 1116 case HCLK_SDMMC: 1117 case HCLK_SDIO0: 1118 case SCLK_EMMC: 1119 case SCLK_SDMMC: 1120 case SCLK_SDIO0: 1121 new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate); 1122 break; 1123 case SCLK_SPI0: 1124 case SCLK_SPI1: 1125 case SCLK_SPI2: 1126 new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate); 1127 break; 1128 #ifndef CONFIG_SPL_BUILD 1129 case SCLK_MAC: 1130 new_rate = rockchip_mac_set_clk(priv->cru, rate); 1131 break; 1132 case DCLK_VOP0: 1133 case DCLK_VOP1: 1134 case ACLK_VIO0: 1135 case ACLK_VIO1: 1136 new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate); 1137 break; 1138 case SCLK_EDP_24M: 1139 /* clk_edp_24M source: 24M */ 1140 rk_setreg(&cru->cru_clksel_con[28], 1 << 15); 1141 1142 /* rst edp */ 1143 rk_setreg(&cru->cru_clksel_con[6], 1 << 15); 1144 udelay(1); 1145 rk_clrreg(&cru->cru_clksel_con[6], 1 << 15); 1146 new_rate = rate; 1147 break; 1148 case PCLK_HDMI_CTRL: 1149 /* enable pclk hdmi ctrl */ 1150 rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9); 1151 1152 /* software reset hdmi */ 1153 rk_setreg(&cru->cru_clkgate_con[7], 1 << 9); 1154 udelay(1); 1155 rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9); 1156 new_rate = rate; 1157 break; 1158 case SCLK_CRYPTO: 1159 new_rate = rockchip_crypto_set_clk(priv->cru, rate); 1160 break; 1161 #endif 1162 case SCLK_SARADC: 1163 new_rate = rockchip_saradc_set_clk(priv->cru, rate); 1164 break; 1165 case SCLK_TSADC: 1166 new_rate = rockchip_tsadc_set_clk(priv->cru, rate); 1167 break; 1168 case PLL_GPLL: 1169 case PLL_CPLL: 1170 case PLL_NPLL: 1171 case ACLK_CPU: 1172 case HCLK_CPU: 1173 case PCLK_CPU: 1174 case ACLK_PERI: 1175 case HCLK_PERI: 1176 case PCLK_PERI: 1177 case SCLK_UART0: 1178 return 0; 1179 default: 1180 return -ENOENT; 1181 } 1182 1183 return new_rate; 1184 } 1185 1186 #define ROCKCHIP_MMC_DELAY_SEL BIT(10) 1187 #define ROCKCHIP_MMC_DEGREE_MASK 0x3 1188 #define ROCKCHIP_MMC_DELAYNUM_OFFSET 2 1189 #define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET) 1190 1191 #define PSECS_PER_SEC 1000000000000LL 1192 /* 1193 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to 1194 * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg. 1195 */ 1196 #define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60 1197 1198 int rockchip_mmc_get_phase(struct clk *clk) 1199 { 1200 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); 1201 struct rk3288_cru *cru = priv->cru; 1202 u32 raw_value, delay_num; 1203 u16 degrees = 0; 1204 ulong rate; 1205 1206 rate = rk3288_clk_get_rate(clk); 1207 1208 if (rate < 0) 1209 return rate; 1210 1211 if (clk->id == SCLK_EMMC_SAMPLE) 1212 raw_value = readl(&cru->cru_emmc_con[1]); 1213 else 1214 raw_value = readl(&cru->cru_sdmmc_con[1]); 1215 1216 degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90; 1217 1218 if (raw_value & ROCKCHIP_MMC_DELAY_SEL) { 1219 /* degrees/delaynum * 10000 */ 1220 unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) * 1221 36 * (rate / 1000000); 1222 1223 delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK); 1224 delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET; 1225 degrees += DIV_ROUND_CLOSEST(delay_num * factor, 10000); 1226 } 1227 1228 return degrees % 360; 1229 } 1230 1231 int rockchip_mmc_set_phase(struct clk *clk, u32 degrees) 1232 { 1233 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); 1234 struct rk3288_cru *cru = priv->cru; 1235 u8 nineties, remainder, delay_num; 1236 u32 raw_value, delay; 1237 ulong rate; 1238 1239 rate = rk3288_clk_get_rate(clk); 1240 1241 if (rate < 0) 1242 return rate; 1243 1244 nineties = degrees / 90; 1245 remainder = (degrees % 90); 1246 1247 /* 1248 * Convert to delay; do a little extra work to make sure we 1249 * don't overflow 32-bit / 64-bit numbers. 1250 */ 1251 delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */ 1252 delay *= remainder; 1253 delay = DIV_ROUND_CLOSEST(delay, (rate / 1000) * 36 * 1254 (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10)); 1255 1256 delay_num = (u8)min_t(u32, delay, 255); 1257 1258 raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0; 1259 raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET; 1260 raw_value |= nineties; 1261 1262 if (clk->id == SCLK_EMMC_SAMPLE) 1263 writel(raw_value | 0xffff0000, &cru->cru_emmc_con[1]); 1264 else 1265 writel(raw_value | 0xffff0000, &cru->cru_sdmmc_con[1]); 1266 1267 debug("mmc set_phase(%d) delay_nums=%u reg=%#x actual_degrees=%d\n", 1268 degrees, delay_num, raw_value, rockchip_mmc_get_phase(clk)); 1269 1270 return 0; 1271 } 1272 1273 static int rk3288_clk_get_phase(struct clk *clk) 1274 { 1275 int ret; 1276 1277 switch (clk->id) { 1278 case SCLK_EMMC_SAMPLE: 1279 case SCLK_SDMMC_SAMPLE: 1280 ret = rockchip_mmc_get_phase(clk); 1281 break; 1282 default: 1283 return -ENOENT; 1284 } 1285 1286 return ret; 1287 } 1288 1289 static int rk3288_clk_set_phase(struct clk *clk, int degrees) 1290 { 1291 int ret; 1292 1293 switch (clk->id) { 1294 case SCLK_EMMC_SAMPLE: 1295 case SCLK_SDMMC_SAMPLE: 1296 ret = rockchip_mmc_set_phase(clk, degrees); 1297 break; 1298 default: 1299 return -ENOENT; 1300 } 1301 1302 return ret; 1303 } 1304 1305 static int __maybe_unused rk3288_gmac_set_parent(struct clk *clk, struct clk *parent) 1306 { 1307 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); 1308 struct rk3288_cru *cru = priv->cru; 1309 const char *clock_output_name; 1310 int ret; 1311 1312 /* 1313 * If the requested parent is in the same clock-controller and 1314 * the id is SCLK_MAC_PLL ("mac_pll_src"), switch to the internal 1315 * clock. 1316 */ 1317 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_PLL)) { 1318 debug("%s: switching GAMC to SCLK_MAC_PLL\n", __func__); 1319 rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, 0); 1320 return 0; 1321 } 1322 1323 /* 1324 * Otherwise, we need to check the clock-output-names of the 1325 * requested parent to see if the requested id is "ext_gmac". 1326 */ 1327 ret = dev_read_string_index(parent->dev, "clock-output-names", 1328 parent->id, &clock_output_name); 1329 if (ret < 0) 1330 return -ENODATA; 1331 1332 /* If this is "ext_gmac", switch to the external clock input */ 1333 if (!strcmp(clock_output_name, "ext_gmac")) { 1334 debug("%s: switching GMAC to external clock\n", __func__); 1335 rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, 1336 RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT); 1337 return 0; 1338 } 1339 1340 return -EINVAL; 1341 } 1342 1343 static int __maybe_unused rk3288_vop_set_parent(struct clk *clk, 1344 struct clk *parent) 1345 { 1346 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); 1347 struct rk3288_cru *cru = priv->cru; 1348 int parent_sel; 1349 1350 switch (parent->id) { 1351 case PLL_CPLL: 1352 parent_sel = 0; 1353 break; 1354 case PLL_GPLL: 1355 parent_sel = 1; 1356 break; 1357 case PLL_NPLL: 1358 parent_sel = 2; 1359 break; 1360 default: 1361 parent_sel = 0; 1362 break; 1363 } 1364 1365 switch (clk->id) { 1366 case DCLK_VOP0: 1367 rk_clrsetreg(&cru->cru_clksel_con[27], 1368 DCLK_VOP0_PLL_MASK, parent_sel << 0); 1369 break; 1370 case DCLK_VOP1: 1371 rk_clrsetreg(&cru->cru_clksel_con[29], 1372 DCLK_VOP1_PLL_MASK, parent_sel << 6); 1373 break; 1374 default: 1375 return -EINVAL; 1376 } 1377 1378 return 0; 1379 } 1380 1381 static int __maybe_unused rk3288_clk_set_parent(struct clk *clk, struct clk *parent) 1382 { 1383 switch (clk->id) { 1384 case SCLK_MAC: 1385 return rk3288_gmac_set_parent(clk, parent); 1386 case DCLK_VOP0: 1387 case DCLK_VOP1: 1388 return rk3288_vop_set_parent(clk, parent); 1389 case SCLK_USBPHY480M_SRC: 1390 return 0; 1391 } 1392 1393 debug("%s: unsupported clk %ld\n", __func__, clk->id); 1394 return -ENOENT; 1395 } 1396 1397 static struct clk_ops rk3288_clk_ops = { 1398 .get_rate = rk3288_clk_get_rate, 1399 .set_rate = rk3288_clk_set_rate, 1400 .get_phase = rk3288_clk_get_phase, 1401 .set_phase = rk3288_clk_set_phase, 1402 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 1403 .set_parent = rk3288_clk_set_parent, 1404 #endif 1405 }; 1406 1407 static int rk3288_clk_ofdata_to_platdata(struct udevice *dev) 1408 { 1409 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 1410 struct rk3288_clk_priv *priv = dev_get_priv(dev); 1411 1412 priv->cru = dev_read_addr_ptr(dev); 1413 #endif 1414 1415 return 0; 1416 } 1417 1418 static int rk3288_clk_probe(struct udevice *dev) 1419 { 1420 struct rk3288_clk_priv *priv = dev_get_priv(dev); 1421 bool init_clocks = false; 1422 int ret; 1423 1424 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1425 if (IS_ERR(priv->grf)) 1426 return PTR_ERR(priv->grf); 1427 #ifdef CONFIG_SPL_BUILD 1428 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1429 struct rk3288_clk_plat *plat = dev_get_platdata(dev); 1430 1431 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); 1432 #endif 1433 init_clocks = true; 1434 #endif 1435 if (!(gd->flags & GD_FLG_RELOC)) { 1436 u32 reg; 1437 1438 /* 1439 * Init clocks in U-Boot proper if the NPLL is runnning. This 1440 * indicates that a previous boot loader set up the clocks, so 1441 * we need to redo it. U-Boot's SPL does not set this clock. 1442 * Or if the CPLL is not init, we need to redo the clk_init. 1443 */ 1444 reg = readl(&priv->cru->cru_mode_con); 1445 if ((((reg & NPLL_MODE_MASK) >> NPLL_MODE_SHIFT) == 1446 NPLL_MODE_NORMAL) || 1447 !(reg & CPLL_MODE_MASK)) 1448 init_clocks = true; 1449 } 1450 1451 priv->sync_kernel = false; 1452 if (!priv->armclk_enter_hz) 1453 priv->armclk_enter_hz = rkclk_pll_get_rate(priv->cru, 1454 CLK_ARM); 1455 1456 if (init_clocks) { 1457 rkclk_init(priv->cru, priv->grf); 1458 if (!priv->armclk_init_hz) 1459 priv->armclk_init_hz = rkclk_pll_get_rate(priv->cru, 1460 CLK_ARM); 1461 } else { 1462 if (!priv->armclk_init_hz) 1463 priv->armclk_init_hz = priv->armclk_enter_hz; 1464 } 1465 1466 ret = clk_set_defaults(dev); 1467 if (ret) 1468 debug("%s clk_set_defaults failed %d\n", __func__, ret); 1469 else 1470 priv->sync_kernel = true; 1471 1472 return 0; 1473 } 1474 1475 static int rk3288_clk_bind(struct udevice *dev) 1476 { 1477 int ret; 1478 struct udevice *sys_child, *sf_child; 1479 struct sysreset_reg *priv; 1480 struct softreset_reg *sf_priv; 1481 1482 /* The reset driver does not have a device node, so bind it here */ 1483 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", 1484 &sys_child); 1485 if (ret) { 1486 debug("Warning: No sysreset driver: ret=%d\n", ret); 1487 } else { 1488 priv = malloc(sizeof(struct sysreset_reg)); 1489 priv->glb_srst_fst_value = offsetof(struct rk3288_cru, 1490 cru_glb_srst_fst_value); 1491 priv->glb_srst_snd_value = offsetof(struct rk3288_cru, 1492 cru_glb_srst_snd_value); 1493 sys_child->priv = priv; 1494 } 1495 1496 ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset", 1497 dev_ofnode(dev), &sf_child); 1498 if (ret) { 1499 debug("Warning: No rockchip reset driver: ret=%d\n", ret); 1500 } else { 1501 sf_priv = malloc(sizeof(struct softreset_reg)); 1502 sf_priv->sf_reset_offset = offsetof(struct rk3288_cru, 1503 cru_softrst_con[0]); 1504 sf_priv->sf_reset_num = 12; 1505 sf_child->priv = sf_priv; 1506 } 1507 1508 return 0; 1509 } 1510 1511 static const struct udevice_id rk3288_clk_ids[] = { 1512 { .compatible = "rockchip,rk3288-cru" }, 1513 { } 1514 }; 1515 1516 U_BOOT_DRIVER(rockchip_rk3288_cru) = { 1517 .name = "rockchip_rk3288_cru", 1518 .id = UCLASS_CLK, 1519 .of_match = rk3288_clk_ids, 1520 .priv_auto_alloc_size = sizeof(struct rk3288_clk_priv), 1521 .platdata_auto_alloc_size = sizeof(struct rk3288_clk_plat), 1522 .ops = &rk3288_clk_ops, 1523 .bind = rk3288_clk_bind, 1524 .ofdata_to_platdata = rk3288_clk_ofdata_to_platdata, 1525 .probe = rk3288_clk_probe, 1526 }; 1527 1528 #ifndef CONFIG_SPL_BUILD 1529 /** 1530 * soc_clk_dump() - Print clock frequencies 1531 * Returns zero on success 1532 * 1533 * Implementation for the clk dump command. 1534 */ 1535 int soc_clk_dump(void) 1536 { 1537 struct udevice *cru_dev; 1538 struct rk3288_clk_priv *priv; 1539 const struct rk3288_clk_info *clk_dump; 1540 struct clk clk; 1541 unsigned long clk_count = ARRAY_SIZE(clks_dump); 1542 unsigned long rate; 1543 int i, ret; 1544 1545 ret = uclass_get_device_by_driver(UCLASS_CLK, 1546 DM_GET_DRIVER(rockchip_rk3288_cru), 1547 &cru_dev); 1548 if (ret) { 1549 printf("%s failed to get cru device\n", __func__); 1550 return ret; 1551 } 1552 1553 priv = dev_get_priv(cru_dev); 1554 printf("CLK: (%s. arm: enter %lu KHz, init %lu KHz, kernel %lu%s)\n", 1555 priv->sync_kernel ? "sync kernel" : "uboot", 1556 priv->armclk_enter_hz / 1000, 1557 priv->armclk_init_hz / 1000, 1558 priv->set_armclk_rate ? priv->armclk_hz / 1000 : 0, 1559 priv->set_armclk_rate ? " KHz" : "N/A"); 1560 for (i = 0; i < clk_count; i++) { 1561 clk_dump = &clks_dump[i]; 1562 if (clk_dump->name) { 1563 clk.id = clk_dump->id; 1564 if (clk_dump->is_cru) 1565 ret = clk_request(cru_dev, &clk); 1566 if (ret < 0) 1567 return ret; 1568 1569 rate = clk_get_rate(&clk); 1570 clk_free(&clk); 1571 if (i == 0) { 1572 if (rate < 0) 1573 printf(" %s %s\n", clk_dump->name, 1574 "unknown"); 1575 else 1576 printf(" %s %lu KHz\n", clk_dump->name, 1577 rate / 1000); 1578 } else { 1579 if (rate < 0) 1580 printf(" %s %s\n", clk_dump->name, 1581 "unknown"); 1582 else 1583 printf(" %s %lu KHz\n", clk_dump->name, 1584 rate / 1000); 1585 } 1586 } 1587 } 1588 1589 return 0; 1590 } 1591 #endif 1592 1593