1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <bitfield.h> 9 #include <clk-uclass.h> 10 #include <dm.h> 11 #include <dt-structs.h> 12 #include <errno.h> 13 #include <mapmem.h> 14 #include <syscon.h> 15 #include <asm/io.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/cru_rk3288.h> 18 #include <asm/arch/grf_rk3288.h> 19 #include <asm/arch/hardware.h> 20 #include <dt-bindings/clock/rk3288-cru.h> 21 #include <dm/device-internal.h> 22 #include <dm/lists.h> 23 #include <dm/uclass-internal.h> 24 #include <linux/log2.h> 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 struct rk3288_clk_plat { 29 #if CONFIG_IS_ENABLED(OF_PLATDATA) 30 struct dtd_rockchip_rk3288_cru dtd; 31 #endif 32 }; 33 34 struct pll_div { 35 u32 nr; 36 u32 nf; 37 u32 no; 38 }; 39 40 enum { 41 VCO_MAX_HZ = 2200U * 1000000, 42 VCO_MIN_HZ = 440 * 1000000, 43 OUTPUT_MAX_HZ = 2200U * 1000000, 44 OUTPUT_MIN_HZ = 27500000, 45 FREF_MAX_HZ = 2200U * 1000000, 46 FREF_MIN_HZ = 269 * 1000, 47 }; 48 49 enum { 50 /* PLL CON0 */ 51 PLL_OD_MASK = 0x0f, 52 53 /* PLL CON1 */ 54 PLL_NF_MASK = 0x1fff, 55 56 /* PLL CON2 */ 57 PLL_BWADJ_MASK = 0x0fff, 58 59 /* PLL CON3 */ 60 PLL_RESET_SHIFT = 5, 61 62 /* CLKSEL0 */ 63 CORE_SEL_PLL_SHIFT = 15, 64 CORE_SEL_PLL_MASK = 1 << CORE_SEL_PLL_SHIFT, 65 A17_DIV_SHIFT = 8, 66 A17_DIV_MASK = 0x1f << A17_DIV_SHIFT, 67 MP_DIV_SHIFT = 4, 68 MP_DIV_MASK = 0xf << MP_DIV_SHIFT, 69 M0_DIV_SHIFT = 0, 70 M0_DIV_MASK = 0xf << M0_DIV_SHIFT, 71 72 /* CLKSEL1: pd bus clk pll sel: codec or general */ 73 PD_BUS_SEL_PLL_MASK = 15, 74 PD_BUS_SEL_CPLL = 0, 75 PD_BUS_SEL_GPLL, 76 77 /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */ 78 PD_BUS_PCLK_DIV_SHIFT = 12, 79 PD_BUS_PCLK_DIV_MASK = 7 << PD_BUS_PCLK_DIV_SHIFT, 80 81 /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */ 82 PD_BUS_HCLK_DIV_SHIFT = 8, 83 PD_BUS_HCLK_DIV_MASK = 3 << PD_BUS_HCLK_DIV_SHIFT, 84 85 /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */ 86 PD_BUS_ACLK_DIV0_SHIFT = 3, 87 PD_BUS_ACLK_DIV0_MASK = 0x1f << PD_BUS_ACLK_DIV0_SHIFT, 88 PD_BUS_ACLK_DIV1_SHIFT = 0, 89 PD_BUS_ACLK_DIV1_MASK = 0x7 << PD_BUS_ACLK_DIV1_SHIFT, 90 91 /* 92 * CLKSEL10 93 * peripheral bus pclk div: 94 * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1 95 */ 96 PERI_SEL_PLL_SHIFT = 15, 97 PERI_SEL_PLL_MASK = 1 << PERI_SEL_PLL_SHIFT, 98 PERI_SEL_CPLL = 0, 99 PERI_SEL_GPLL, 100 101 PERI_PCLK_DIV_SHIFT = 12, 102 PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT, 103 104 /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */ 105 PERI_HCLK_DIV_SHIFT = 8, 106 PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, 107 108 /* 109 * peripheral bus aclk div: 110 * aclk_periph = periph_clk_src / (peri_aclk_div_con + 1) 111 */ 112 PERI_ACLK_DIV_SHIFT = 0, 113 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, 114 115 /* 116 * CLKSEL24 117 * saradc_div_con: 118 * clk_saradc=24MHz/(saradc_div_con+1) 119 */ 120 CLK_SARADC_DIV_CON_SHIFT = 8, 121 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8), 122 CLK_SARADC_DIV_CON_WIDTH = 8, 123 124 SOCSTS_DPLL_LOCK = 1 << 5, 125 SOCSTS_APLL_LOCK = 1 << 6, 126 SOCSTS_CPLL_LOCK = 1 << 7, 127 SOCSTS_GPLL_LOCK = 1 << 8, 128 SOCSTS_NPLL_LOCK = 1 << 9, 129 }; 130 131 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 132 133 #define PLL_DIVISORS(hz, _nr, _no) {\ 134 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\ 135 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\ 136 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\ 137 "divisors on line " __stringify(__LINE__)); 138 139 /* Keep divisors as low as possible to reduce jitter and power usage */ 140 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1); 141 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2); 142 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2); 143 144 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id, 145 const struct pll_div *div) 146 { 147 int pll_id = rk_pll_id(clk_id); 148 struct rk3288_pll *pll = &cru->pll[pll_id]; 149 /* All PLLs have same VCO and output frequency range restrictions. */ 150 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; 151 uint output_hz = vco_hz / div->no; 152 153 debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n", 154 (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz); 155 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && 156 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ && 157 (div->no == 1 || !(div->no % 2))); 158 159 /* enter reset */ 160 rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT); 161 162 rk_clrsetreg(&pll->con0, CLKR_MASK | PLL_OD_MASK, 163 ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1)); 164 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); 165 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); 166 167 udelay(10); 168 169 /* return from reset */ 170 rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT); 171 172 return 0; 173 } 174 175 static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf, 176 unsigned int hz) 177 { 178 static const struct pll_div dpll_cfg[] = { 179 {.nf = 25, .nr = 2, .no = 1}, 180 {.nf = 400, .nr = 9, .no = 2}, 181 {.nf = 500, .nr = 9, .no = 2}, 182 {.nf = 100, .nr = 3, .no = 1}, 183 }; 184 int cfg; 185 186 switch (hz) { 187 case 300000000: 188 cfg = 0; 189 break; 190 case 533000000: /* actually 533.3P MHz */ 191 cfg = 1; 192 break; 193 case 666000000: /* actually 666.6P MHz */ 194 cfg = 2; 195 break; 196 case 800000000: 197 cfg = 3; 198 break; 199 default: 200 debug("Unsupported SDRAM frequency"); 201 return -EINVAL; 202 } 203 204 /* pll enter slow-mode */ 205 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, 206 DPLL_MODE_SLOW << DPLL_MODE_SHIFT); 207 208 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]); 209 210 /* wait for pll lock */ 211 while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK)) 212 udelay(1); 213 214 /* PLL enter normal-mode */ 215 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, 216 DPLL_MODE_NORMAL << DPLL_MODE_SHIFT); 217 218 return 0; 219 } 220 221 #ifndef CONFIG_SPL_BUILD 222 #define VCO_MAX_KHZ 2200000 223 #define VCO_MIN_KHZ 440000 224 #define FREF_MAX_KHZ 2200000 225 #define FREF_MIN_KHZ 269 226 #define PLL_LIMIT_FREQ 600000000 227 228 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div) 229 { 230 uint ref_khz = OSC_HZ / 1000, nr, nf = 0; 231 uint fref_khz; 232 uint diff_khz, best_diff_khz; 233 const uint max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4; 234 uint vco_khz; 235 uint no = 1; 236 uint freq_khz = freq_hz / 1000; 237 238 if (!freq_hz) { 239 printf("%s: the frequency can not be 0 Hz\n", __func__); 240 return -EINVAL; 241 } 242 243 no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz); 244 if (ext_div) { 245 *ext_div = DIV_ROUND_UP(PLL_LIMIT_FREQ, freq_hz); 246 no = DIV_ROUND_UP(no, *ext_div); 247 } 248 249 /* only even divisors (and 1) are supported */ 250 if (no > 1) 251 no = DIV_ROUND_UP(no, 2) * 2; 252 253 vco_khz = freq_khz * no; 254 if (ext_div) 255 vco_khz *= *ext_div; 256 257 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) { 258 printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n", 259 __func__, freq_hz); 260 return -1; 261 } 262 263 div->no = no; 264 265 best_diff_khz = vco_khz; 266 for (nr = 1; nr < max_nr && best_diff_khz; nr++) { 267 fref_khz = ref_khz / nr; 268 if (fref_khz < FREF_MIN_KHZ) 269 break; 270 if (fref_khz > FREF_MAX_KHZ) 271 continue; 272 273 nf = vco_khz / fref_khz; 274 if (nf >= max_nf) 275 continue; 276 diff_khz = vco_khz - nf * fref_khz; 277 if (nf + 1 < max_nf && diff_khz > fref_khz / 2) { 278 nf++; 279 diff_khz = fref_khz - diff_khz; 280 } 281 282 if (diff_khz >= best_diff_khz) 283 continue; 284 285 best_diff_khz = diff_khz; 286 div->nr = nr; 287 div->nf = nf; 288 } 289 290 if (best_diff_khz > 4 * 1000) { 291 printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n", 292 __func__, freq_hz, best_diff_khz * 1000); 293 return -EINVAL; 294 } 295 296 return 0; 297 } 298 299 static int rockchip_mac_set_clk(struct rk3288_cru *cru, uint freq) 300 { 301 ulong ret; 302 303 /* 304 * The gmac clock can be derived either from an external clock 305 * or can be generated from internally by a divider from SCLK_MAC. 306 */ 307 if (readl(&cru->cru_clksel_con[21]) & RMII_EXTCLK_MASK) { 308 /* An external clock will always generate the right rate... */ 309 ret = freq; 310 } else { 311 u32 con = readl(&cru->cru_clksel_con[21]); 312 ulong pll_rate; 313 u8 div; 314 315 if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) == 316 EMAC_PLL_SELECT_GENERAL) 317 pll_rate = GPLL_HZ; 318 else if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) == 319 EMAC_PLL_SELECT_CODEC) 320 pll_rate = CPLL_HZ; 321 else 322 pll_rate = NPLL_HZ; 323 324 div = DIV_ROUND_UP(pll_rate, freq) - 1; 325 if (div <= 0x1f) 326 rk_clrsetreg(&cru->cru_clksel_con[21], MAC_DIV_CON_MASK, 327 div << MAC_DIV_CON_SHIFT); 328 else 329 debug("Unsupported div for gmac:%d\n", div); 330 331 return DIV_TO_RATE(pll_rate, div); 332 } 333 334 return ret; 335 } 336 337 static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf, 338 int periph, unsigned int rate_hz) 339 { 340 struct pll_div npll_config = {0}; 341 u32 lcdc_div; 342 int ret; 343 344 ret = pll_para_config(rate_hz, &npll_config, &lcdc_div); 345 if (ret) 346 return ret; 347 348 rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK, 349 NPLL_MODE_SLOW << NPLL_MODE_SHIFT); 350 rkclk_set_pll(cru, CLK_NEW, &npll_config); 351 352 /* waiting for pll lock */ 353 while (1) { 354 if (readl(&grf->soc_status[1]) & SOCSTS_NPLL_LOCK) 355 break; 356 udelay(1); 357 } 358 359 rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK, 360 NPLL_MODE_NORMAL << NPLL_MODE_SHIFT); 361 362 /* vop dclk source clk: npll,dclk_div: 1 */ 363 switch (periph) { 364 case DCLK_VOP0: 365 rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0, 366 (lcdc_div - 1) << 8 | 2 << 0); 367 break; 368 case DCLK_VOP1: 369 rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6, 370 (lcdc_div - 1) << 8 | 2 << 6); 371 break; 372 } 373 374 return 0; 375 } 376 #endif /* CONFIG_SPL_BUILD */ 377 378 static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) 379 { 380 u32 aclk_div; 381 u32 hclk_div; 382 u32 pclk_div; 383 384 /* pll enter slow-mode */ 385 rk_clrsetreg(&cru->cru_mode_con, 386 GPLL_MODE_MASK | CPLL_MODE_MASK, 387 GPLL_MODE_SLOW << GPLL_MODE_SHIFT | 388 CPLL_MODE_SLOW << CPLL_MODE_SHIFT); 389 390 /* init pll */ 391 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); 392 rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg); 393 394 /* waiting for pll lock */ 395 while ((readl(&grf->soc_status[1]) & 396 (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) != 397 (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) 398 udelay(1); 399 400 /* 401 * pd_bus clock pll source selection and 402 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 403 */ 404 aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1; 405 assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); 406 hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1; 407 assert((hclk_div + 1) * PD_BUS_HCLK_HZ == 408 PD_BUS_ACLK_HZ && (hclk_div <= 0x3) && (hclk_div != 0x2)); 409 410 pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1; 411 assert((pclk_div + 1) * PD_BUS_PCLK_HZ == 412 PD_BUS_ACLK_HZ && pclk_div <= 0x7); 413 414 rk_clrsetreg(&cru->cru_clksel_con[1], 415 PD_BUS_PCLK_DIV_MASK | PD_BUS_HCLK_DIV_MASK | 416 PD_BUS_ACLK_DIV0_MASK | PD_BUS_ACLK_DIV1_MASK, 417 pclk_div << PD_BUS_PCLK_DIV_SHIFT | 418 hclk_div << PD_BUS_HCLK_DIV_SHIFT | 419 aclk_div << PD_BUS_ACLK_DIV0_SHIFT | 420 0 << 0); 421 422 /* 423 * peri clock pll source selection and 424 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 425 */ 426 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; 427 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); 428 429 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); 430 assert((1 << hclk_div) * PERI_HCLK_HZ == 431 PERI_ACLK_HZ && (hclk_div <= 0x2)); 432 433 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); 434 assert((1 << pclk_div) * PERI_PCLK_HZ == 435 PERI_ACLK_HZ && (pclk_div <= 0x3)); 436 437 rk_clrsetreg(&cru->cru_clksel_con[10], 438 PERI_PCLK_DIV_MASK | PERI_HCLK_DIV_MASK | 439 PERI_ACLK_DIV_MASK, 440 PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT | 441 pclk_div << PERI_PCLK_DIV_SHIFT | 442 hclk_div << PERI_HCLK_DIV_SHIFT | 443 aclk_div << PERI_ACLK_DIV_SHIFT); 444 445 /* PLL enter normal-mode */ 446 rk_clrsetreg(&cru->cru_mode_con, 447 GPLL_MODE_MASK | CPLL_MODE_MASK, 448 GPLL_MODE_NORMAL << GPLL_MODE_SHIFT | 449 CPLL_MODE_NORMAL << CPLL_MODE_SHIFT); 450 } 451 452 void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf) 453 { 454 /* pll enter slow-mode */ 455 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, 456 APLL_MODE_SLOW << APLL_MODE_SHIFT); 457 458 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); 459 460 /* waiting for pll lock */ 461 while (!(readl(&grf->soc_status[1]) & SOCSTS_APLL_LOCK)) 462 udelay(1); 463 464 /* 465 * core clock pll source selection and 466 * set up dependent divisors for MPAXI/M0AXI and ARM clocks. 467 * core clock select apll, apll clk = 1800MHz 468 * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz 469 */ 470 rk_clrsetreg(&cru->cru_clksel_con[0], 471 CORE_SEL_PLL_MASK | A17_DIV_MASK | MP_DIV_MASK | 472 M0_DIV_MASK, 473 0 << A17_DIV_SHIFT | 474 3 << MP_DIV_SHIFT | 475 1 << M0_DIV_SHIFT); 476 477 /* 478 * set up dependent divisors for L2RAM/ATCLK and PCLK clocks. 479 * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz 480 */ 481 rk_clrsetreg(&cru->cru_clksel_con[37], 482 CLK_L2RAM_DIV_MASK | ATCLK_CORE_DIV_CON_MASK | 483 PCLK_CORE_DBG_DIV_MASK, 484 1 << CLK_L2RAM_DIV_SHIFT | 485 3 << ATCLK_CORE_DIV_CON_SHIFT | 486 3 << PCLK_CORE_DBG_DIV_SHIFT); 487 488 /* PLL enter normal-mode */ 489 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, 490 APLL_MODE_NORMAL << APLL_MODE_SHIFT); 491 } 492 493 /* Get pll rate by id */ 494 static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru, 495 enum rk_clk_id clk_id) 496 { 497 uint32_t nr, no, nf; 498 uint32_t con; 499 int pll_id = rk_pll_id(clk_id); 500 struct rk3288_pll *pll = &cru->pll[pll_id]; 501 static u8 clk_shift[CLK_COUNT] = { 502 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, 503 GPLL_MODE_SHIFT, NPLL_MODE_SHIFT 504 }; 505 uint shift; 506 507 con = readl(&cru->cru_mode_con); 508 shift = clk_shift[clk_id]; 509 switch ((con >> shift) & CRU_MODE_MASK) { 510 case APLL_MODE_SLOW: 511 return OSC_HZ; 512 case APLL_MODE_NORMAL: 513 /* normal mode */ 514 con = readl(&pll->con0); 515 no = ((con & CLKOD_MASK) >> CLKOD_SHIFT) + 1; 516 nr = ((con & CLKR_MASK) >> CLKR_SHIFT) + 1; 517 con = readl(&pll->con1); 518 nf = ((con & CLKF_MASK) >> CLKF_SHIFT) + 1; 519 520 return (24 * nf / (nr * no)) * 1000000; 521 case APLL_MODE_DEEP: 522 default: 523 return 32768; 524 } 525 } 526 527 static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate, 528 int periph) 529 { 530 uint src_rate; 531 uint div, mux; 532 u32 con; 533 534 switch (periph) { 535 case HCLK_EMMC: 536 case SCLK_EMMC: 537 case SCLK_EMMC_SAMPLE: 538 con = readl(&cru->cru_clksel_con[12]); 539 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; 540 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; 541 break; 542 case HCLK_SDMMC: 543 case SCLK_SDMMC: 544 con = readl(&cru->cru_clksel_con[11]); 545 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT; 546 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT; 547 break; 548 case HCLK_SDIO0: 549 case SCLK_SDIO0: 550 con = readl(&cru->cru_clksel_con[12]); 551 mux = (con & SDIO0_PLL_MASK) >> SDIO0_PLL_SHIFT; 552 div = (con & SDIO0_DIV_MASK) >> SDIO0_DIV_SHIFT; 553 break; 554 default: 555 return -EINVAL; 556 } 557 558 src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate; 559 return DIV_TO_RATE(src_rate, div) / 2; 560 } 561 562 static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate, 563 int periph, uint freq) 564 { 565 int src_clk_div; 566 int mux; 567 568 debug("%s: gclk_rate=%u\n", __func__, gclk_rate); 569 /* mmc clock default div 2 internal, need provide double in cru */ 570 src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq); 571 572 if (src_clk_div > 0x3f) { 573 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); 574 assert(src_clk_div < 0x40); 575 mux = EMMC_PLL_SELECT_24MHZ; 576 assert((int)EMMC_PLL_SELECT_24MHZ == 577 (int)MMC0_PLL_SELECT_24MHZ); 578 } else { 579 mux = EMMC_PLL_SELECT_GENERAL; 580 assert((int)EMMC_PLL_SELECT_GENERAL == 581 (int)MMC0_PLL_SELECT_GENERAL); 582 } 583 switch (periph) { 584 case HCLK_EMMC: 585 case SCLK_EMMC: 586 rk_clrsetreg(&cru->cru_clksel_con[12], 587 EMMC_PLL_MASK | EMMC_DIV_MASK, 588 mux << EMMC_PLL_SHIFT | 589 (src_clk_div - 1) << EMMC_DIV_SHIFT); 590 break; 591 case HCLK_SDMMC: 592 case SCLK_SDMMC: 593 rk_clrsetreg(&cru->cru_clksel_con[11], 594 MMC0_PLL_MASK | MMC0_DIV_MASK, 595 mux << MMC0_PLL_SHIFT | 596 (src_clk_div - 1) << MMC0_DIV_SHIFT); 597 break; 598 case HCLK_SDIO0: 599 case SCLK_SDIO0: 600 rk_clrsetreg(&cru->cru_clksel_con[12], 601 SDIO0_PLL_MASK | SDIO0_DIV_MASK, 602 mux << SDIO0_PLL_SHIFT | 603 (src_clk_div - 1) << SDIO0_DIV_SHIFT); 604 break; 605 default: 606 return -EINVAL; 607 } 608 609 return rockchip_mmc_get_clk(cru, gclk_rate, periph); 610 } 611 612 static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate, 613 int periph) 614 { 615 uint div, mux; 616 u32 con; 617 618 switch (periph) { 619 case SCLK_SPI0: 620 con = readl(&cru->cru_clksel_con[25]); 621 mux = (con & SPI0_PLL_MASK) >> SPI0_PLL_SHIFT; 622 div = (con & SPI0_DIV_MASK) >> SPI0_DIV_SHIFT; 623 break; 624 case SCLK_SPI1: 625 con = readl(&cru->cru_clksel_con[25]); 626 mux = (con & SPI1_PLL_MASK) >> SPI1_PLL_SHIFT; 627 div = (con & SPI1_DIV_MASK) >> SPI1_DIV_SHIFT; 628 break; 629 case SCLK_SPI2: 630 con = readl(&cru->cru_clksel_con[39]); 631 mux = (con & SPI2_PLL_MASK) >> SPI2_PLL_SHIFT; 632 div = (con & SPI2_DIV_MASK) >> SPI2_DIV_SHIFT; 633 break; 634 default: 635 return -EINVAL; 636 } 637 assert(mux == SPI0_PLL_SELECT_GENERAL); 638 639 return DIV_TO_RATE(gclk_rate, div); 640 } 641 642 static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate, 643 int periph, uint freq) 644 { 645 int src_clk_div; 646 647 debug("%s: clk_general_rate=%u\n", __func__, gclk_rate); 648 src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1; 649 assert(src_clk_div < 128); 650 switch (periph) { 651 case SCLK_SPI0: 652 rk_clrsetreg(&cru->cru_clksel_con[25], 653 SPI0_PLL_MASK | SPI0_DIV_MASK, 654 SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT | 655 src_clk_div << SPI0_DIV_SHIFT); 656 break; 657 case SCLK_SPI1: 658 rk_clrsetreg(&cru->cru_clksel_con[25], 659 SPI1_PLL_MASK | SPI1_DIV_MASK, 660 SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT | 661 src_clk_div << SPI1_DIV_SHIFT); 662 break; 663 case SCLK_SPI2: 664 rk_clrsetreg(&cru->cru_clksel_con[39], 665 SPI2_PLL_MASK | SPI2_DIV_MASK, 666 SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT | 667 src_clk_div << SPI2_DIV_SHIFT); 668 break; 669 default: 670 return -EINVAL; 671 } 672 673 return rockchip_spi_get_clk(cru, gclk_rate, periph); 674 } 675 676 static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru) 677 { 678 u32 div, val; 679 680 val = readl(&cru->cru_clksel_con[24]); 681 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT, 682 CLK_SARADC_DIV_CON_WIDTH); 683 684 return DIV_TO_RATE(OSC_HZ, div); 685 } 686 687 static ulong rockchip_saradc_set_clk(struct rk3288_cru *cru, uint hz) 688 { 689 int src_clk_div; 690 691 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; 692 assert(src_clk_div < 128); 693 694 rk_clrsetreg(&cru->cru_clksel_con[24], 695 CLK_SARADC_DIV_CON_MASK, 696 src_clk_div << CLK_SARADC_DIV_CON_SHIFT); 697 698 return rockchip_saradc_get_clk(cru); 699 } 700 701 static ulong rk3288_clk_get_rate(struct clk *clk) 702 { 703 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); 704 ulong new_rate, gclk_rate; 705 706 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); 707 switch (clk->id) { 708 case 0 ... 63: 709 new_rate = rkclk_pll_get_rate(priv->cru, clk->id); 710 break; 711 case HCLK_EMMC: 712 case HCLK_SDMMC: 713 case HCLK_SDIO0: 714 case SCLK_EMMC: 715 case SCLK_EMMC_SAMPLE: 716 case SCLK_SDMMC: 717 case SCLK_SDMMC_SAMPLE: 718 case SCLK_SDIO0: 719 new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id); 720 break; 721 case SCLK_SPI0: 722 case SCLK_SPI1: 723 case SCLK_SPI2: 724 new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, clk->id); 725 break; 726 case PCLK_I2C0: 727 case PCLK_I2C1: 728 case PCLK_I2C2: 729 case PCLK_I2C3: 730 case PCLK_I2C4: 731 case PCLK_I2C5: 732 return gclk_rate; 733 case PCLK_PWM: 734 return PD_BUS_PCLK_HZ; 735 case SCLK_SARADC: 736 new_rate = rockchip_saradc_get_clk(priv->cru); 737 break; 738 default: 739 return -ENOENT; 740 } 741 742 return new_rate; 743 } 744 745 static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate) 746 { 747 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); 748 struct rk3288_cru *cru = priv->cru; 749 ulong new_rate, gclk_rate; 750 751 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); 752 switch (clk->id) { 753 case PLL_APLL: 754 /* We only support a fixed rate here */ 755 if (rate != 1800000000) 756 return -EINVAL; 757 rk3288_clk_configure_cpu(priv->cru, priv->grf); 758 new_rate = rate; 759 break; 760 case CLK_DDR: 761 new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate); 762 break; 763 case HCLK_EMMC: 764 case HCLK_SDMMC: 765 case HCLK_SDIO0: 766 case SCLK_EMMC: 767 case SCLK_SDMMC: 768 case SCLK_SDIO0: 769 new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate); 770 break; 771 case SCLK_SPI0: 772 case SCLK_SPI1: 773 case SCLK_SPI2: 774 new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate); 775 break; 776 #ifndef CONFIG_SPL_BUILD 777 case SCLK_MAC: 778 new_rate = rockchip_mac_set_clk(priv->cru, rate); 779 break; 780 case DCLK_VOP0: 781 case DCLK_VOP1: 782 new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate); 783 break; 784 case SCLK_EDP_24M: 785 /* clk_edp_24M source: 24M */ 786 rk_setreg(&cru->cru_clksel_con[28], 1 << 15); 787 788 /* rst edp */ 789 rk_setreg(&cru->cru_clksel_con[6], 1 << 15); 790 udelay(1); 791 rk_clrreg(&cru->cru_clksel_con[6], 1 << 15); 792 new_rate = rate; 793 break; 794 case ACLK_VOP0: 795 case ACLK_VOP1: { 796 u32 div; 797 798 /* vop aclk source clk: cpll */ 799 div = CPLL_HZ / rate; 800 assert((div - 1 < 64) && (div * rate == CPLL_HZ)); 801 802 switch (clk->id) { 803 case ACLK_VOP0: 804 rk_clrsetreg(&cru->cru_clksel_con[31], 805 3 << 6 | 0x1f << 0, 806 0 << 6 | (div - 1) << 0); 807 break; 808 case ACLK_VOP1: 809 rk_clrsetreg(&cru->cru_clksel_con[31], 810 3 << 14 | 0x1f << 8, 811 0 << 14 | (div - 1) << 8); 812 break; 813 } 814 new_rate = rate; 815 break; 816 } 817 case PCLK_HDMI_CTRL: 818 /* enable pclk hdmi ctrl */ 819 rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9); 820 821 /* software reset hdmi */ 822 rk_setreg(&cru->cru_clkgate_con[7], 1 << 9); 823 udelay(1); 824 rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9); 825 new_rate = rate; 826 break; 827 #endif 828 case SCLK_SARADC: 829 new_rate = rockchip_saradc_set_clk(priv->cru, rate); 830 break; 831 case PLL_GPLL: 832 case PLL_CPLL: 833 case PLL_NPLL: 834 case ACLK_CPU: 835 case HCLK_CPU: 836 case PCLK_CPU: 837 case ACLK_PERI: 838 case HCLK_PERI: 839 case PCLK_PERI: 840 case SCLK_UART0: 841 return 0; 842 default: 843 return -ENOENT; 844 } 845 846 return new_rate; 847 } 848 849 #define ROCKCHIP_MMC_DELAY_SEL BIT(10) 850 #define ROCKCHIP_MMC_DEGREE_MASK 0x3 851 #define ROCKCHIP_MMC_DELAYNUM_OFFSET 2 852 #define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET) 853 854 #define PSECS_PER_SEC 1000000000000LL 855 /* 856 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to 857 * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg. 858 */ 859 #define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60 860 861 int rockchip_mmc_get_phase(struct clk *clk) 862 { 863 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); 864 struct rk3288_cru *cru = priv->cru; 865 u32 raw_value, delay_num; 866 u16 degrees = 0; 867 ulong rate; 868 869 rate = rk3288_clk_get_rate(clk); 870 871 if (rate < 0) 872 return rate; 873 874 if (clk->id == SCLK_EMMC_SAMPLE) 875 raw_value = readl(&cru->cru_emmc_con[1]); 876 else 877 raw_value = readl(&cru->cru_sdmmc_con[1]); 878 879 degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90; 880 881 if (raw_value & ROCKCHIP_MMC_DELAY_SEL) { 882 /* degrees/delaynum * 10000 */ 883 unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) * 884 36 * (rate / 1000000); 885 886 delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK); 887 delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET; 888 degrees += DIV_ROUND_CLOSEST(delay_num * factor, 10000); 889 } 890 891 return degrees % 360; 892 } 893 894 int rockchip_mmc_set_phase(struct clk *clk, u32 degrees) 895 { 896 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); 897 struct rk3288_cru *cru = priv->cru; 898 u8 nineties, remainder, delay_num; 899 u32 raw_value, delay; 900 ulong rate; 901 902 rate = rk3288_clk_get_rate(clk); 903 904 if (rate < 0) 905 return rate; 906 907 nineties = degrees / 90; 908 remainder = (degrees % 90); 909 910 /* 911 * Convert to delay; do a little extra work to make sure we 912 * don't overflow 32-bit / 64-bit numbers. 913 */ 914 delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */ 915 delay *= remainder; 916 delay = DIV_ROUND_CLOSEST(delay, (rate / 1000) * 36 * 917 (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10)); 918 919 delay_num = (u8)min_t(u32, delay, 255); 920 921 raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0; 922 raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET; 923 raw_value |= nineties; 924 925 if (clk->id == SCLK_EMMC_SAMPLE) 926 writel(raw_value | 0xffff0000, &cru->cru_emmc_con[1]); 927 else 928 writel(raw_value | 0xffff0000, &cru->cru_sdmmc_con[1]); 929 930 debug("mmc set_phase(%d) delay_nums=%u reg=%#x actual_degrees=%d\n", 931 degrees, delay_num, raw_value, rockchip_mmc_get_phase(clk)); 932 933 return 0; 934 } 935 936 static int rk3288_clk_get_phase(struct clk *clk) 937 { 938 int ret; 939 940 switch (clk->id) { 941 case SCLK_EMMC_SAMPLE: 942 case SCLK_SDMMC_SAMPLE: 943 ret = rockchip_mmc_get_phase(clk); 944 break; 945 default: 946 return -ENOENT; 947 } 948 949 return ret; 950 } 951 952 static int rk3288_clk_set_phase(struct clk *clk, int degrees) 953 { 954 int ret; 955 956 switch (clk->id) { 957 case SCLK_EMMC_SAMPLE: 958 case SCLK_SDMMC_SAMPLE: 959 ret = rockchip_mmc_set_phase(clk, degrees); 960 break; 961 default: 962 return -ENOENT; 963 } 964 965 return ret; 966 } 967 968 static int __maybe_unused rk3288_gmac_set_parent(struct clk *clk, struct clk *parent) 969 { 970 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); 971 struct rk3288_cru *cru = priv->cru; 972 const char *clock_output_name; 973 int ret; 974 975 /* 976 * If the requested parent is in the same clock-controller and 977 * the id is SCLK_MAC_PLL ("mac_pll_src"), switch to the internal 978 * clock. 979 */ 980 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_PLL)) { 981 debug("%s: switching GAMC to SCLK_MAC_PLL\n", __func__); 982 rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, 0); 983 return 0; 984 } 985 986 /* 987 * Otherwise, we need to check the clock-output-names of the 988 * requested parent to see if the requested id is "ext_gmac". 989 */ 990 ret = dev_read_string_index(parent->dev, "clock-output-names", 991 parent->id, &clock_output_name); 992 if (ret < 0) 993 return -ENODATA; 994 995 /* If this is "ext_gmac", switch to the external clock input */ 996 if (!strcmp(clock_output_name, "ext_gmac")) { 997 debug("%s: switching GMAC to external clock\n", __func__); 998 rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, 999 RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT); 1000 return 0; 1001 } 1002 1003 return -EINVAL; 1004 } 1005 1006 static int __maybe_unused rk3288_clk_set_parent(struct clk *clk, struct clk *parent) 1007 { 1008 switch (clk->id) { 1009 case SCLK_MAC: 1010 return rk3288_gmac_set_parent(clk, parent); 1011 case SCLK_USBPHY480M_SRC: 1012 return 0; 1013 } 1014 1015 debug("%s: unsupported clk %ld\n", __func__, clk->id); 1016 return -ENOENT; 1017 } 1018 1019 static struct clk_ops rk3288_clk_ops = { 1020 .get_rate = rk3288_clk_get_rate, 1021 .set_rate = rk3288_clk_set_rate, 1022 .get_phase = rk3288_clk_get_phase, 1023 .set_phase = rk3288_clk_set_phase, 1024 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 1025 .set_parent = rk3288_clk_set_parent, 1026 #endif 1027 }; 1028 1029 static int rk3288_clk_ofdata_to_platdata(struct udevice *dev) 1030 { 1031 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 1032 struct rk3288_clk_priv *priv = dev_get_priv(dev); 1033 1034 priv->cru = dev_read_addr_ptr(dev); 1035 #endif 1036 1037 return 0; 1038 } 1039 1040 static int rk3288_clk_probe(struct udevice *dev) 1041 { 1042 struct rk3288_clk_priv *priv = dev_get_priv(dev); 1043 bool init_clocks = false; 1044 1045 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1046 if (IS_ERR(priv->grf)) 1047 return PTR_ERR(priv->grf); 1048 #ifdef CONFIG_SPL_BUILD 1049 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1050 struct rk3288_clk_plat *plat = dev_get_platdata(dev); 1051 1052 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); 1053 #endif 1054 init_clocks = true; 1055 #endif 1056 if (!(gd->flags & GD_FLG_RELOC)) { 1057 u32 reg; 1058 1059 /* 1060 * Init clocks in U-Boot proper if the NPLL is runnning. This 1061 * indicates that a previous boot loader set up the clocks, so 1062 * we need to redo it. U-Boot's SPL does not set this clock. 1063 * Or if the CPLL is not init, we need to redo the clk_init. 1064 */ 1065 reg = readl(&priv->cru->cru_mode_con); 1066 if ((((reg & NPLL_MODE_MASK) >> NPLL_MODE_SHIFT) == 1067 NPLL_MODE_NORMAL) || 1068 !(reg & CPLL_MODE_MASK)) 1069 init_clocks = true; 1070 } 1071 1072 if (init_clocks) 1073 rkclk_init(priv->cru, priv->grf); 1074 1075 return 0; 1076 } 1077 1078 static int rk3288_clk_bind(struct udevice *dev) 1079 { 1080 int ret; 1081 struct udevice *sys_child, *sf_child; 1082 struct sysreset_reg *priv; 1083 struct softreset_reg *sf_priv; 1084 1085 /* The reset driver does not have a device node, so bind it here */ 1086 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", 1087 &sys_child); 1088 if (ret) { 1089 debug("Warning: No sysreset driver: ret=%d\n", ret); 1090 } else { 1091 priv = malloc(sizeof(struct sysreset_reg)); 1092 priv->glb_srst_fst_value = offsetof(struct rk3288_cru, 1093 cru_glb_srst_fst_value); 1094 priv->glb_srst_snd_value = offsetof(struct rk3288_cru, 1095 cru_glb_srst_snd_value); 1096 sys_child->priv = priv; 1097 } 1098 1099 ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset", 1100 dev_ofnode(dev), &sf_child); 1101 if (ret) { 1102 debug("Warning: No rockchip reset driver: ret=%d\n", ret); 1103 } else { 1104 sf_priv = malloc(sizeof(struct softreset_reg)); 1105 sf_priv->sf_reset_offset = offsetof(struct rk3288_cru, 1106 cru_softrst_con[0]); 1107 sf_priv->sf_reset_num = 12; 1108 sf_child->priv = sf_priv; 1109 } 1110 1111 return 0; 1112 } 1113 1114 static const struct udevice_id rk3288_clk_ids[] = { 1115 { .compatible = "rockchip,rk3288-cru" }, 1116 { } 1117 }; 1118 1119 U_BOOT_DRIVER(rockchip_rk3288_cru) = { 1120 .name = "rockchip_rk3288_cru", 1121 .id = UCLASS_CLK, 1122 .of_match = rk3288_clk_ids, 1123 .priv_auto_alloc_size = sizeof(struct rk3288_clk_priv), 1124 .platdata_auto_alloc_size = sizeof(struct rk3288_clk_plat), 1125 .ops = &rk3288_clk_ops, 1126 .bind = rk3288_clk_bind, 1127 .ofdata_to_platdata = rk3288_clk_ofdata_to_platdata, 1128 .probe = rk3288_clk_probe, 1129 }; 1130