1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <bitfield.h> 9 #include <clk-uclass.h> 10 #include <dm.h> 11 #include <dt-structs.h> 12 #include <errno.h> 13 #include <mapmem.h> 14 #include <syscon.h> 15 #include <asm/io.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/cru_rk3288.h> 18 #include <asm/arch/grf_rk3288.h> 19 #include <asm/arch/hardware.h> 20 #include <dt-bindings/clock/rk3288-cru.h> 21 #include <dm/device-internal.h> 22 #include <dm/lists.h> 23 #include <dm/uclass-internal.h> 24 #include <linux/log2.h> 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 struct rk3288_clk_plat { 29 #if CONFIG_IS_ENABLED(OF_PLATDATA) 30 struct dtd_rockchip_rk3288_cru dtd; 31 #endif 32 }; 33 34 struct pll_div { 35 u32 nr; 36 u32 nf; 37 u32 no; 38 }; 39 40 enum { 41 VCO_MAX_HZ = 2200U * 1000000, 42 VCO_MIN_HZ = 440 * 1000000, 43 OUTPUT_MAX_HZ = 2200U * 1000000, 44 OUTPUT_MIN_HZ = 27500000, 45 FREF_MAX_HZ = 2200U * 1000000, 46 FREF_MIN_HZ = 269 * 1000, 47 }; 48 49 enum { 50 /* PLL CON0 */ 51 PLL_OD_MASK = 0x0f, 52 53 /* PLL CON1 */ 54 PLL_NF_MASK = 0x1fff, 55 56 /* PLL CON2 */ 57 PLL_BWADJ_MASK = 0x0fff, 58 59 /* PLL CON3 */ 60 PLL_RESET_SHIFT = 5, 61 62 /* CLKSEL0 */ 63 CORE_SEL_PLL_SHIFT = 15, 64 CORE_SEL_PLL_MASK = 1 << CORE_SEL_PLL_SHIFT, 65 A17_DIV_SHIFT = 8, 66 A17_DIV_MASK = 0x1f << A17_DIV_SHIFT, 67 MP_DIV_SHIFT = 4, 68 MP_DIV_MASK = 0xf << MP_DIV_SHIFT, 69 M0_DIV_SHIFT = 0, 70 M0_DIV_MASK = 0xf << M0_DIV_SHIFT, 71 72 /* CLKSEL1: pd bus clk pll sel: codec or general */ 73 PD_BUS_SEL_PLL_MASK = 15, 74 PD_BUS_SEL_CPLL = 0, 75 PD_BUS_SEL_GPLL, 76 77 /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */ 78 PD_BUS_PCLK_DIV_SHIFT = 12, 79 PD_BUS_PCLK_DIV_MASK = 7 << PD_BUS_PCLK_DIV_SHIFT, 80 81 /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */ 82 PD_BUS_HCLK_DIV_SHIFT = 8, 83 PD_BUS_HCLK_DIV_MASK = 3 << PD_BUS_HCLK_DIV_SHIFT, 84 85 /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */ 86 PD_BUS_ACLK_DIV0_SHIFT = 3, 87 PD_BUS_ACLK_DIV0_MASK = 0x1f << PD_BUS_ACLK_DIV0_SHIFT, 88 PD_BUS_ACLK_DIV1_SHIFT = 0, 89 PD_BUS_ACLK_DIV1_MASK = 0x7 << PD_BUS_ACLK_DIV1_SHIFT, 90 91 /* CLKSEL2: tsadc */ 92 CLK_TSADC_DIV_CON_SHIFT = 0, 93 CLK_TSADC_DIV_CON_MASK = GENMASK(5, 0), 94 CLK_TSADC_DIV_CON_WIDTH = 6, 95 96 /* 97 * CLKSEL10 98 * peripheral bus pclk div: 99 * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1 100 */ 101 PERI_SEL_PLL_SHIFT = 15, 102 PERI_SEL_PLL_MASK = 1 << PERI_SEL_PLL_SHIFT, 103 PERI_SEL_CPLL = 0, 104 PERI_SEL_GPLL, 105 106 PERI_PCLK_DIV_SHIFT = 12, 107 PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT, 108 109 /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */ 110 PERI_HCLK_DIV_SHIFT = 8, 111 PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, 112 113 /* 114 * peripheral bus aclk div: 115 * aclk_periph = periph_clk_src / (peri_aclk_div_con + 1) 116 */ 117 PERI_ACLK_DIV_SHIFT = 0, 118 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, 119 120 /* 121 * CLKSEL24 122 * saradc_div_con: 123 * clk_saradc=24MHz/(saradc_div_con+1) 124 */ 125 CLK_SARADC_DIV_CON_SHIFT = 8, 126 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8), 127 CLK_SARADC_DIV_CON_WIDTH = 8, 128 129 SOCSTS_DPLL_LOCK = 1 << 5, 130 SOCSTS_APLL_LOCK = 1 << 6, 131 SOCSTS_CPLL_LOCK = 1 << 7, 132 SOCSTS_GPLL_LOCK = 1 << 8, 133 SOCSTS_NPLL_LOCK = 1 << 9, 134 }; 135 136 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 137 138 #define PLL_DIVISORS(hz, _nr, _no) {\ 139 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\ 140 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\ 141 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\ 142 "divisors on line " __stringify(__LINE__)); 143 144 /* Keep divisors as low as possible to reduce jitter and power usage */ 145 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1); 146 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2); 147 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2); 148 149 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id, 150 const struct pll_div *div) 151 { 152 int pll_id = rk_pll_id(clk_id); 153 struct rk3288_pll *pll = &cru->pll[pll_id]; 154 /* All PLLs have same VCO and output frequency range restrictions. */ 155 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; 156 uint output_hz = vco_hz / div->no; 157 158 debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n", 159 (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz); 160 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && 161 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ && 162 (div->no == 1 || !(div->no % 2))); 163 164 /* enter reset */ 165 rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT); 166 167 rk_clrsetreg(&pll->con0, CLKR_MASK | PLL_OD_MASK, 168 ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1)); 169 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); 170 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); 171 172 udelay(10); 173 174 /* return from reset */ 175 rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT); 176 177 return 0; 178 } 179 180 static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf, 181 unsigned int hz) 182 { 183 static const struct pll_div dpll_cfg[] = { 184 {.nf = 25, .nr = 2, .no = 1}, 185 {.nf = 400, .nr = 9, .no = 2}, 186 {.nf = 500, .nr = 9, .no = 2}, 187 {.nf = 100, .nr = 3, .no = 1}, 188 }; 189 int cfg; 190 191 switch (hz) { 192 case 300000000: 193 cfg = 0; 194 break; 195 case 533000000: /* actually 533.3P MHz */ 196 cfg = 1; 197 break; 198 case 666000000: /* actually 666.6P MHz */ 199 cfg = 2; 200 break; 201 case 800000000: 202 cfg = 3; 203 break; 204 default: 205 debug("Unsupported SDRAM frequency"); 206 return -EINVAL; 207 } 208 209 /* pll enter slow-mode */ 210 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, 211 DPLL_MODE_SLOW << DPLL_MODE_SHIFT); 212 213 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]); 214 215 /* wait for pll lock */ 216 while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK)) 217 udelay(1); 218 219 /* PLL enter normal-mode */ 220 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, 221 DPLL_MODE_NORMAL << DPLL_MODE_SHIFT); 222 223 return 0; 224 } 225 226 #ifndef CONFIG_SPL_BUILD 227 #define VCO_MAX_KHZ 2200000 228 #define VCO_MIN_KHZ 440000 229 #define FREF_MAX_KHZ 2200000 230 #define FREF_MIN_KHZ 269 231 #define PLL_LIMIT_FREQ 600000000 232 233 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div) 234 { 235 uint ref_khz = OSC_HZ / 1000, nr, nf = 0; 236 uint fref_khz; 237 uint diff_khz, best_diff_khz; 238 const uint max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4; 239 uint vco_khz; 240 uint no = 1; 241 uint freq_khz = freq_hz / 1000; 242 243 if (!freq_hz) { 244 printf("%s: the frequency can not be 0 Hz\n", __func__); 245 return -EINVAL; 246 } 247 248 no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz); 249 if (ext_div) { 250 *ext_div = DIV_ROUND_UP(PLL_LIMIT_FREQ, freq_hz); 251 no = DIV_ROUND_UP(no, *ext_div); 252 } 253 254 /* only even divisors (and 1) are supported */ 255 if (no > 1) 256 no = DIV_ROUND_UP(no, 2) * 2; 257 258 vco_khz = freq_khz * no; 259 if (ext_div) 260 vco_khz *= *ext_div; 261 262 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) { 263 printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n", 264 __func__, freq_hz); 265 return -1; 266 } 267 268 div->no = no; 269 270 best_diff_khz = vco_khz; 271 for (nr = 1; nr < max_nr && best_diff_khz; nr++) { 272 fref_khz = ref_khz / nr; 273 if (fref_khz < FREF_MIN_KHZ) 274 break; 275 if (fref_khz > FREF_MAX_KHZ) 276 continue; 277 278 nf = vco_khz / fref_khz; 279 if (nf >= max_nf) 280 continue; 281 diff_khz = vco_khz - nf * fref_khz; 282 if (nf + 1 < max_nf && diff_khz > fref_khz / 2) { 283 nf++; 284 diff_khz = fref_khz - diff_khz; 285 } 286 287 if (diff_khz >= best_diff_khz) 288 continue; 289 290 best_diff_khz = diff_khz; 291 div->nr = nr; 292 div->nf = nf; 293 } 294 295 if (best_diff_khz > 4 * 1000) { 296 printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n", 297 __func__, freq_hz, best_diff_khz * 1000); 298 return -EINVAL; 299 } 300 301 return 0; 302 } 303 304 static int rockchip_mac_set_clk(struct rk3288_cru *cru, uint freq) 305 { 306 ulong ret; 307 308 /* 309 * The gmac clock can be derived either from an external clock 310 * or can be generated from internally by a divider from SCLK_MAC. 311 */ 312 if (readl(&cru->cru_clksel_con[21]) & RMII_EXTCLK_MASK) { 313 /* An external clock will always generate the right rate... */ 314 ret = freq; 315 } else { 316 u32 con = readl(&cru->cru_clksel_con[21]); 317 ulong pll_rate; 318 u8 div; 319 320 if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) == 321 EMAC_PLL_SELECT_GENERAL) 322 pll_rate = GPLL_HZ; 323 else if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) == 324 EMAC_PLL_SELECT_CODEC) 325 pll_rate = CPLL_HZ; 326 else 327 pll_rate = NPLL_HZ; 328 329 div = DIV_ROUND_UP(pll_rate, freq) - 1; 330 if (div <= 0x1f) 331 rk_clrsetreg(&cru->cru_clksel_con[21], MAC_DIV_CON_MASK, 332 div << MAC_DIV_CON_SHIFT); 333 else 334 debug("Unsupported div for gmac:%d\n", div); 335 336 return DIV_TO_RATE(pll_rate, div); 337 } 338 339 return ret; 340 } 341 342 static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf, 343 int periph, unsigned int rate_hz) 344 { 345 struct pll_div npll_config = {0}; 346 u32 lcdc_div; 347 int ret; 348 349 ret = pll_para_config(rate_hz, &npll_config, &lcdc_div); 350 if (ret) 351 return ret; 352 353 rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK, 354 NPLL_MODE_SLOW << NPLL_MODE_SHIFT); 355 rkclk_set_pll(cru, CLK_NEW, &npll_config); 356 357 /* waiting for pll lock */ 358 while (1) { 359 if (readl(&grf->soc_status[1]) & SOCSTS_NPLL_LOCK) 360 break; 361 udelay(1); 362 } 363 364 rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK, 365 NPLL_MODE_NORMAL << NPLL_MODE_SHIFT); 366 367 /* vop dclk source clk: npll,dclk_div: 1 */ 368 switch (periph) { 369 case DCLK_VOP0: 370 rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0, 371 (lcdc_div - 1) << 8 | 2 << 0); 372 break; 373 case DCLK_VOP1: 374 rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6, 375 (lcdc_div - 1) << 8 | 2 << 6); 376 break; 377 } 378 379 return 0; 380 } 381 #endif /* CONFIG_SPL_BUILD */ 382 383 static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) 384 { 385 u32 aclk_div; 386 u32 hclk_div; 387 u32 pclk_div; 388 389 /* pll enter slow-mode */ 390 rk_clrsetreg(&cru->cru_mode_con, 391 GPLL_MODE_MASK | CPLL_MODE_MASK, 392 GPLL_MODE_SLOW << GPLL_MODE_SHIFT | 393 CPLL_MODE_SLOW << CPLL_MODE_SHIFT); 394 395 /* init pll */ 396 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); 397 rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg); 398 399 /* waiting for pll lock */ 400 while ((readl(&grf->soc_status[1]) & 401 (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) != 402 (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) 403 udelay(1); 404 405 /* 406 * pd_bus clock pll source selection and 407 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 408 */ 409 aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1; 410 assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); 411 hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1; 412 assert((hclk_div + 1) * PD_BUS_HCLK_HZ == 413 PD_BUS_ACLK_HZ && (hclk_div <= 0x3) && (hclk_div != 0x2)); 414 415 pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1; 416 assert((pclk_div + 1) * PD_BUS_PCLK_HZ == 417 PD_BUS_ACLK_HZ && pclk_div <= 0x7); 418 419 rk_clrsetreg(&cru->cru_clksel_con[1], 420 PD_BUS_PCLK_DIV_MASK | PD_BUS_HCLK_DIV_MASK | 421 PD_BUS_ACLK_DIV0_MASK | PD_BUS_ACLK_DIV1_MASK, 422 pclk_div << PD_BUS_PCLK_DIV_SHIFT | 423 hclk_div << PD_BUS_HCLK_DIV_SHIFT | 424 aclk_div << PD_BUS_ACLK_DIV0_SHIFT | 425 0 << 0); 426 427 /* 428 * peri clock pll source selection and 429 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 430 */ 431 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; 432 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); 433 434 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); 435 assert((1 << hclk_div) * PERI_HCLK_HZ == 436 PERI_ACLK_HZ && (hclk_div <= 0x2)); 437 438 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); 439 assert((1 << pclk_div) * PERI_PCLK_HZ == 440 PERI_ACLK_HZ && (pclk_div <= 0x3)); 441 442 rk_clrsetreg(&cru->cru_clksel_con[10], 443 PERI_PCLK_DIV_MASK | PERI_HCLK_DIV_MASK | 444 PERI_ACLK_DIV_MASK, 445 PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT | 446 pclk_div << PERI_PCLK_DIV_SHIFT | 447 hclk_div << PERI_HCLK_DIV_SHIFT | 448 aclk_div << PERI_ACLK_DIV_SHIFT); 449 450 /* PLL enter normal-mode */ 451 rk_clrsetreg(&cru->cru_mode_con, 452 GPLL_MODE_MASK | CPLL_MODE_MASK, 453 GPLL_MODE_NORMAL << GPLL_MODE_SHIFT | 454 CPLL_MODE_NORMAL << CPLL_MODE_SHIFT); 455 } 456 457 void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf) 458 { 459 /* pll enter slow-mode */ 460 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, 461 APLL_MODE_SLOW << APLL_MODE_SHIFT); 462 463 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); 464 465 /* waiting for pll lock */ 466 while (!(readl(&grf->soc_status[1]) & SOCSTS_APLL_LOCK)) 467 udelay(1); 468 469 /* 470 * core clock pll source selection and 471 * set up dependent divisors for MPAXI/M0AXI and ARM clocks. 472 * core clock select apll, apll clk = 1800MHz 473 * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz 474 */ 475 rk_clrsetreg(&cru->cru_clksel_con[0], 476 CORE_SEL_PLL_MASK | A17_DIV_MASK | MP_DIV_MASK | 477 M0_DIV_MASK, 478 0 << A17_DIV_SHIFT | 479 3 << MP_DIV_SHIFT | 480 1 << M0_DIV_SHIFT); 481 482 /* 483 * set up dependent divisors for L2RAM/ATCLK and PCLK clocks. 484 * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz 485 */ 486 rk_clrsetreg(&cru->cru_clksel_con[37], 487 CLK_L2RAM_DIV_MASK | ATCLK_CORE_DIV_CON_MASK | 488 PCLK_CORE_DBG_DIV_MASK, 489 1 << CLK_L2RAM_DIV_SHIFT | 490 3 << ATCLK_CORE_DIV_CON_SHIFT | 491 3 << PCLK_CORE_DBG_DIV_SHIFT); 492 493 /* PLL enter normal-mode */ 494 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, 495 APLL_MODE_NORMAL << APLL_MODE_SHIFT); 496 } 497 498 /* Get pll rate by id */ 499 static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru, 500 enum rk_clk_id clk_id) 501 { 502 uint32_t nr, no, nf; 503 uint32_t con; 504 int pll_id = rk_pll_id(clk_id); 505 struct rk3288_pll *pll = &cru->pll[pll_id]; 506 static u8 clk_shift[CLK_COUNT] = { 507 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, 508 GPLL_MODE_SHIFT, NPLL_MODE_SHIFT 509 }; 510 uint shift; 511 512 con = readl(&cru->cru_mode_con); 513 shift = clk_shift[clk_id]; 514 switch ((con >> shift) & CRU_MODE_MASK) { 515 case APLL_MODE_SLOW: 516 return OSC_HZ; 517 case APLL_MODE_NORMAL: 518 /* normal mode */ 519 con = readl(&pll->con0); 520 no = ((con & CLKOD_MASK) >> CLKOD_SHIFT) + 1; 521 nr = ((con & CLKR_MASK) >> CLKR_SHIFT) + 1; 522 con = readl(&pll->con1); 523 nf = ((con & CLKF_MASK) >> CLKF_SHIFT) + 1; 524 525 return (24 * nf / (nr * no)) * 1000000; 526 case APLL_MODE_DEEP: 527 default: 528 return 32768; 529 } 530 } 531 532 static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate, 533 int periph) 534 { 535 uint src_rate; 536 uint div, mux; 537 u32 con; 538 539 switch (periph) { 540 case HCLK_EMMC: 541 case SCLK_EMMC: 542 case SCLK_EMMC_SAMPLE: 543 con = readl(&cru->cru_clksel_con[12]); 544 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; 545 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; 546 break; 547 case HCLK_SDMMC: 548 case SCLK_SDMMC: 549 con = readl(&cru->cru_clksel_con[11]); 550 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT; 551 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT; 552 break; 553 case HCLK_SDIO0: 554 case SCLK_SDIO0: 555 con = readl(&cru->cru_clksel_con[12]); 556 mux = (con & SDIO0_PLL_MASK) >> SDIO0_PLL_SHIFT; 557 div = (con & SDIO0_DIV_MASK) >> SDIO0_DIV_SHIFT; 558 break; 559 default: 560 return -EINVAL; 561 } 562 563 src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate; 564 return DIV_TO_RATE(src_rate, div) / 2; 565 } 566 567 static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate, 568 int periph, uint freq) 569 { 570 int src_clk_div; 571 int mux; 572 573 debug("%s: gclk_rate=%u\n", __func__, gclk_rate); 574 /* mmc clock default div 2 internal, need provide double in cru */ 575 src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq); 576 577 if (src_clk_div > 0x3f) { 578 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); 579 assert(src_clk_div < 0x40); 580 mux = EMMC_PLL_SELECT_24MHZ; 581 assert((int)EMMC_PLL_SELECT_24MHZ == 582 (int)MMC0_PLL_SELECT_24MHZ); 583 } else { 584 mux = EMMC_PLL_SELECT_GENERAL; 585 assert((int)EMMC_PLL_SELECT_GENERAL == 586 (int)MMC0_PLL_SELECT_GENERAL); 587 } 588 switch (periph) { 589 case HCLK_EMMC: 590 case SCLK_EMMC: 591 rk_clrsetreg(&cru->cru_clksel_con[12], 592 EMMC_PLL_MASK | EMMC_DIV_MASK, 593 mux << EMMC_PLL_SHIFT | 594 (src_clk_div - 1) << EMMC_DIV_SHIFT); 595 break; 596 case HCLK_SDMMC: 597 case SCLK_SDMMC: 598 rk_clrsetreg(&cru->cru_clksel_con[11], 599 MMC0_PLL_MASK | MMC0_DIV_MASK, 600 mux << MMC0_PLL_SHIFT | 601 (src_clk_div - 1) << MMC0_DIV_SHIFT); 602 break; 603 case HCLK_SDIO0: 604 case SCLK_SDIO0: 605 rk_clrsetreg(&cru->cru_clksel_con[12], 606 SDIO0_PLL_MASK | SDIO0_DIV_MASK, 607 mux << SDIO0_PLL_SHIFT | 608 (src_clk_div - 1) << SDIO0_DIV_SHIFT); 609 break; 610 default: 611 return -EINVAL; 612 } 613 614 return rockchip_mmc_get_clk(cru, gclk_rate, periph); 615 } 616 617 static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate, 618 int periph) 619 { 620 uint div, mux; 621 u32 con; 622 623 switch (periph) { 624 case SCLK_SPI0: 625 con = readl(&cru->cru_clksel_con[25]); 626 mux = (con & SPI0_PLL_MASK) >> SPI0_PLL_SHIFT; 627 div = (con & SPI0_DIV_MASK) >> SPI0_DIV_SHIFT; 628 break; 629 case SCLK_SPI1: 630 con = readl(&cru->cru_clksel_con[25]); 631 mux = (con & SPI1_PLL_MASK) >> SPI1_PLL_SHIFT; 632 div = (con & SPI1_DIV_MASK) >> SPI1_DIV_SHIFT; 633 break; 634 case SCLK_SPI2: 635 con = readl(&cru->cru_clksel_con[39]); 636 mux = (con & SPI2_PLL_MASK) >> SPI2_PLL_SHIFT; 637 div = (con & SPI2_DIV_MASK) >> SPI2_DIV_SHIFT; 638 break; 639 default: 640 return -EINVAL; 641 } 642 assert(mux == SPI0_PLL_SELECT_GENERAL); 643 644 return DIV_TO_RATE(gclk_rate, div); 645 } 646 647 static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate, 648 int periph, uint freq) 649 { 650 int src_clk_div; 651 652 debug("%s: clk_general_rate=%u\n", __func__, gclk_rate); 653 src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1; 654 assert(src_clk_div < 128); 655 switch (periph) { 656 case SCLK_SPI0: 657 rk_clrsetreg(&cru->cru_clksel_con[25], 658 SPI0_PLL_MASK | SPI0_DIV_MASK, 659 SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT | 660 src_clk_div << SPI0_DIV_SHIFT); 661 break; 662 case SCLK_SPI1: 663 rk_clrsetreg(&cru->cru_clksel_con[25], 664 SPI1_PLL_MASK | SPI1_DIV_MASK, 665 SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT | 666 src_clk_div << SPI1_DIV_SHIFT); 667 break; 668 case SCLK_SPI2: 669 rk_clrsetreg(&cru->cru_clksel_con[39], 670 SPI2_PLL_MASK | SPI2_DIV_MASK, 671 SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT | 672 src_clk_div << SPI2_DIV_SHIFT); 673 break; 674 default: 675 return -EINVAL; 676 } 677 678 return rockchip_spi_get_clk(cru, gclk_rate, periph); 679 } 680 681 static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru) 682 { 683 u32 div, val; 684 685 val = readl(&cru->cru_clksel_con[24]); 686 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT, 687 CLK_SARADC_DIV_CON_WIDTH); 688 689 return DIV_TO_RATE(OSC_HZ, div); 690 } 691 692 static ulong rockchip_saradc_set_clk(struct rk3288_cru *cru, uint hz) 693 { 694 int src_clk_div; 695 696 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; 697 assert(src_clk_div < 128); 698 699 rk_clrsetreg(&cru->cru_clksel_con[24], 700 CLK_SARADC_DIV_CON_MASK, 701 src_clk_div << CLK_SARADC_DIV_CON_SHIFT); 702 703 return rockchip_saradc_get_clk(cru); 704 } 705 706 static ulong rockchip_tsadc_get_clk(struct rk3288_cru *cru) 707 { 708 u32 div, val; 709 710 val = readl(&cru->cru_clksel_con[2]); 711 div = bitfield_extract(val, CLK_TSADC_DIV_CON_SHIFT, 712 CLK_TSADC_DIV_CON_WIDTH); 713 714 return DIV_TO_RATE(32768, div); 715 } 716 717 static ulong rockchip_tsadc_set_clk(struct rk3288_cru *cru, uint hz) 718 { 719 int src_clk_div; 720 721 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; 722 assert(src_clk_div < 128); 723 724 rk_clrsetreg(&cru->cru_clksel_con[2], 725 CLK_TSADC_DIV_CON_MASK, 726 src_clk_div << CLK_TSADC_DIV_CON_SHIFT); 727 728 return rockchip_tsadc_get_clk(cru); 729 } 730 731 static ulong rk3288_clk_get_rate(struct clk *clk) 732 { 733 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); 734 ulong new_rate, gclk_rate; 735 736 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); 737 switch (clk->id) { 738 case 0 ... 63: 739 new_rate = rkclk_pll_get_rate(priv->cru, clk->id); 740 break; 741 case HCLK_EMMC: 742 case HCLK_SDMMC: 743 case HCLK_SDIO0: 744 case SCLK_EMMC: 745 case SCLK_EMMC_SAMPLE: 746 case SCLK_SDMMC: 747 case SCLK_SDMMC_SAMPLE: 748 case SCLK_SDIO0: 749 new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id); 750 break; 751 case SCLK_SPI0: 752 case SCLK_SPI1: 753 case SCLK_SPI2: 754 new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, clk->id); 755 break; 756 case PCLK_I2C0: 757 case PCLK_I2C1: 758 case PCLK_I2C2: 759 case PCLK_I2C3: 760 case PCLK_I2C4: 761 case PCLK_I2C5: 762 return gclk_rate; 763 case PCLK_PWM: 764 return PD_BUS_PCLK_HZ; 765 case SCLK_SARADC: 766 new_rate = rockchip_saradc_get_clk(priv->cru); 767 break; 768 case SCLK_TSADC: 769 new_rate = rockchip_tsadc_get_clk(priv->cru); 770 break; 771 default: 772 return -ENOENT; 773 } 774 775 return new_rate; 776 } 777 778 static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate) 779 { 780 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); 781 struct rk3288_cru *cru = priv->cru; 782 ulong new_rate, gclk_rate; 783 784 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); 785 switch (clk->id) { 786 case PLL_APLL: 787 /* We only support a fixed rate here */ 788 if (rate != 1800000000) 789 return -EINVAL; 790 rk3288_clk_configure_cpu(priv->cru, priv->grf); 791 new_rate = rate; 792 break; 793 case CLK_DDR: 794 new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate); 795 break; 796 case HCLK_EMMC: 797 case HCLK_SDMMC: 798 case HCLK_SDIO0: 799 case SCLK_EMMC: 800 case SCLK_SDMMC: 801 case SCLK_SDIO0: 802 new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate); 803 break; 804 case SCLK_SPI0: 805 case SCLK_SPI1: 806 case SCLK_SPI2: 807 new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate); 808 break; 809 #ifndef CONFIG_SPL_BUILD 810 case SCLK_MAC: 811 new_rate = rockchip_mac_set_clk(priv->cru, rate); 812 break; 813 case DCLK_VOP0: 814 case DCLK_VOP1: 815 new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate); 816 break; 817 case SCLK_EDP_24M: 818 /* clk_edp_24M source: 24M */ 819 rk_setreg(&cru->cru_clksel_con[28], 1 << 15); 820 821 /* rst edp */ 822 rk_setreg(&cru->cru_clksel_con[6], 1 << 15); 823 udelay(1); 824 rk_clrreg(&cru->cru_clksel_con[6], 1 << 15); 825 new_rate = rate; 826 break; 827 case ACLK_VOP0: 828 case ACLK_VOP1: { 829 u32 div; 830 831 /* vop aclk source clk: cpll */ 832 div = CPLL_HZ / rate; 833 assert((div - 1 < 64) && (div * rate == CPLL_HZ)); 834 835 switch (clk->id) { 836 case ACLK_VOP0: 837 rk_clrsetreg(&cru->cru_clksel_con[31], 838 3 << 6 | 0x1f << 0, 839 0 << 6 | (div - 1) << 0); 840 break; 841 case ACLK_VOP1: 842 rk_clrsetreg(&cru->cru_clksel_con[31], 843 3 << 14 | 0x1f << 8, 844 0 << 14 | (div - 1) << 8); 845 break; 846 } 847 new_rate = rate; 848 break; 849 } 850 case PCLK_HDMI_CTRL: 851 /* enable pclk hdmi ctrl */ 852 rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9); 853 854 /* software reset hdmi */ 855 rk_setreg(&cru->cru_clkgate_con[7], 1 << 9); 856 udelay(1); 857 rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9); 858 new_rate = rate; 859 break; 860 #endif 861 case SCLK_SARADC: 862 new_rate = rockchip_saradc_set_clk(priv->cru, rate); 863 break; 864 case SCLK_TSADC: 865 new_rate = rockchip_tsadc_set_clk(priv->cru, rate); 866 break; 867 case PLL_GPLL: 868 case PLL_CPLL: 869 case PLL_NPLL: 870 case ACLK_CPU: 871 case HCLK_CPU: 872 case PCLK_CPU: 873 case ACLK_PERI: 874 case HCLK_PERI: 875 case PCLK_PERI: 876 case SCLK_UART0: 877 return 0; 878 default: 879 return -ENOENT; 880 } 881 882 return new_rate; 883 } 884 885 #define ROCKCHIP_MMC_DELAY_SEL BIT(10) 886 #define ROCKCHIP_MMC_DEGREE_MASK 0x3 887 #define ROCKCHIP_MMC_DELAYNUM_OFFSET 2 888 #define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET) 889 890 #define PSECS_PER_SEC 1000000000000LL 891 /* 892 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to 893 * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg. 894 */ 895 #define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60 896 897 int rockchip_mmc_get_phase(struct clk *clk) 898 { 899 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); 900 struct rk3288_cru *cru = priv->cru; 901 u32 raw_value, delay_num; 902 u16 degrees = 0; 903 ulong rate; 904 905 rate = rk3288_clk_get_rate(clk); 906 907 if (rate < 0) 908 return rate; 909 910 if (clk->id == SCLK_EMMC_SAMPLE) 911 raw_value = readl(&cru->cru_emmc_con[1]); 912 else 913 raw_value = readl(&cru->cru_sdmmc_con[1]); 914 915 degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90; 916 917 if (raw_value & ROCKCHIP_MMC_DELAY_SEL) { 918 /* degrees/delaynum * 10000 */ 919 unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) * 920 36 * (rate / 1000000); 921 922 delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK); 923 delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET; 924 degrees += DIV_ROUND_CLOSEST(delay_num * factor, 10000); 925 } 926 927 return degrees % 360; 928 } 929 930 int rockchip_mmc_set_phase(struct clk *clk, u32 degrees) 931 { 932 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); 933 struct rk3288_cru *cru = priv->cru; 934 u8 nineties, remainder, delay_num; 935 u32 raw_value, delay; 936 ulong rate; 937 938 rate = rk3288_clk_get_rate(clk); 939 940 if (rate < 0) 941 return rate; 942 943 nineties = degrees / 90; 944 remainder = (degrees % 90); 945 946 /* 947 * Convert to delay; do a little extra work to make sure we 948 * don't overflow 32-bit / 64-bit numbers. 949 */ 950 delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */ 951 delay *= remainder; 952 delay = DIV_ROUND_CLOSEST(delay, (rate / 1000) * 36 * 953 (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10)); 954 955 delay_num = (u8)min_t(u32, delay, 255); 956 957 raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0; 958 raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET; 959 raw_value |= nineties; 960 961 if (clk->id == SCLK_EMMC_SAMPLE) 962 writel(raw_value | 0xffff0000, &cru->cru_emmc_con[1]); 963 else 964 writel(raw_value | 0xffff0000, &cru->cru_sdmmc_con[1]); 965 966 debug("mmc set_phase(%d) delay_nums=%u reg=%#x actual_degrees=%d\n", 967 degrees, delay_num, raw_value, rockchip_mmc_get_phase(clk)); 968 969 return 0; 970 } 971 972 static int rk3288_clk_get_phase(struct clk *clk) 973 { 974 int ret; 975 976 switch (clk->id) { 977 case SCLK_EMMC_SAMPLE: 978 case SCLK_SDMMC_SAMPLE: 979 ret = rockchip_mmc_get_phase(clk); 980 break; 981 default: 982 return -ENOENT; 983 } 984 985 return ret; 986 } 987 988 static int rk3288_clk_set_phase(struct clk *clk, int degrees) 989 { 990 int ret; 991 992 switch (clk->id) { 993 case SCLK_EMMC_SAMPLE: 994 case SCLK_SDMMC_SAMPLE: 995 ret = rockchip_mmc_set_phase(clk, degrees); 996 break; 997 default: 998 return -ENOENT; 999 } 1000 1001 return ret; 1002 } 1003 1004 static int __maybe_unused rk3288_gmac_set_parent(struct clk *clk, struct clk *parent) 1005 { 1006 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); 1007 struct rk3288_cru *cru = priv->cru; 1008 const char *clock_output_name; 1009 int ret; 1010 1011 /* 1012 * If the requested parent is in the same clock-controller and 1013 * the id is SCLK_MAC_PLL ("mac_pll_src"), switch to the internal 1014 * clock. 1015 */ 1016 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_PLL)) { 1017 debug("%s: switching GAMC to SCLK_MAC_PLL\n", __func__); 1018 rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, 0); 1019 return 0; 1020 } 1021 1022 /* 1023 * Otherwise, we need to check the clock-output-names of the 1024 * requested parent to see if the requested id is "ext_gmac". 1025 */ 1026 ret = dev_read_string_index(parent->dev, "clock-output-names", 1027 parent->id, &clock_output_name); 1028 if (ret < 0) 1029 return -ENODATA; 1030 1031 /* If this is "ext_gmac", switch to the external clock input */ 1032 if (!strcmp(clock_output_name, "ext_gmac")) { 1033 debug("%s: switching GMAC to external clock\n", __func__); 1034 rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, 1035 RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT); 1036 return 0; 1037 } 1038 1039 return -EINVAL; 1040 } 1041 1042 static int __maybe_unused rk3288_clk_set_parent(struct clk *clk, struct clk *parent) 1043 { 1044 switch (clk->id) { 1045 case SCLK_MAC: 1046 return rk3288_gmac_set_parent(clk, parent); 1047 case SCLK_USBPHY480M_SRC: 1048 return 0; 1049 } 1050 1051 debug("%s: unsupported clk %ld\n", __func__, clk->id); 1052 return -ENOENT; 1053 } 1054 1055 static struct clk_ops rk3288_clk_ops = { 1056 .get_rate = rk3288_clk_get_rate, 1057 .set_rate = rk3288_clk_set_rate, 1058 .get_phase = rk3288_clk_get_phase, 1059 .set_phase = rk3288_clk_set_phase, 1060 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 1061 .set_parent = rk3288_clk_set_parent, 1062 #endif 1063 }; 1064 1065 static int rk3288_clk_ofdata_to_platdata(struct udevice *dev) 1066 { 1067 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 1068 struct rk3288_clk_priv *priv = dev_get_priv(dev); 1069 1070 priv->cru = dev_read_addr_ptr(dev); 1071 #endif 1072 1073 return 0; 1074 } 1075 1076 static int rk3288_clk_probe(struct udevice *dev) 1077 { 1078 struct rk3288_clk_priv *priv = dev_get_priv(dev); 1079 bool init_clocks = false; 1080 1081 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1082 if (IS_ERR(priv->grf)) 1083 return PTR_ERR(priv->grf); 1084 #ifdef CONFIG_SPL_BUILD 1085 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1086 struct rk3288_clk_plat *plat = dev_get_platdata(dev); 1087 1088 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); 1089 #endif 1090 init_clocks = true; 1091 #endif 1092 if (!(gd->flags & GD_FLG_RELOC)) { 1093 u32 reg; 1094 1095 /* 1096 * Init clocks in U-Boot proper if the NPLL is runnning. This 1097 * indicates that a previous boot loader set up the clocks, so 1098 * we need to redo it. U-Boot's SPL does not set this clock. 1099 * Or if the CPLL is not init, we need to redo the clk_init. 1100 */ 1101 reg = readl(&priv->cru->cru_mode_con); 1102 if ((((reg & NPLL_MODE_MASK) >> NPLL_MODE_SHIFT) == 1103 NPLL_MODE_NORMAL) || 1104 !(reg & CPLL_MODE_MASK)) 1105 init_clocks = true; 1106 } 1107 1108 if (init_clocks) 1109 rkclk_init(priv->cru, priv->grf); 1110 1111 return 0; 1112 } 1113 1114 static int rk3288_clk_bind(struct udevice *dev) 1115 { 1116 int ret; 1117 struct udevice *sys_child, *sf_child; 1118 struct sysreset_reg *priv; 1119 struct softreset_reg *sf_priv; 1120 1121 /* The reset driver does not have a device node, so bind it here */ 1122 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", 1123 &sys_child); 1124 if (ret) { 1125 debug("Warning: No sysreset driver: ret=%d\n", ret); 1126 } else { 1127 priv = malloc(sizeof(struct sysreset_reg)); 1128 priv->glb_srst_fst_value = offsetof(struct rk3288_cru, 1129 cru_glb_srst_fst_value); 1130 priv->glb_srst_snd_value = offsetof(struct rk3288_cru, 1131 cru_glb_srst_snd_value); 1132 sys_child->priv = priv; 1133 } 1134 1135 ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset", 1136 dev_ofnode(dev), &sf_child); 1137 if (ret) { 1138 debug("Warning: No rockchip reset driver: ret=%d\n", ret); 1139 } else { 1140 sf_priv = malloc(sizeof(struct softreset_reg)); 1141 sf_priv->sf_reset_offset = offsetof(struct rk3288_cru, 1142 cru_softrst_con[0]); 1143 sf_priv->sf_reset_num = 12; 1144 sf_child->priv = sf_priv; 1145 } 1146 1147 return 0; 1148 } 1149 1150 static const struct udevice_id rk3288_clk_ids[] = { 1151 { .compatible = "rockchip,rk3288-cru" }, 1152 { } 1153 }; 1154 1155 U_BOOT_DRIVER(rockchip_rk3288_cru) = { 1156 .name = "rockchip_rk3288_cru", 1157 .id = UCLASS_CLK, 1158 .of_match = rk3288_clk_ids, 1159 .priv_auto_alloc_size = sizeof(struct rk3288_clk_priv), 1160 .platdata_auto_alloc_size = sizeof(struct rk3288_clk_plat), 1161 .ops = &rk3288_clk_ops, 1162 .bind = rk3288_clk_bind, 1163 .ofdata_to_platdata = rk3288_clk_ofdata_to_platdata, 1164 .probe = rk3288_clk_probe, 1165 }; 1166