1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <clk-uclass.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <syscon.h> 12 #include <asm/io.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch/cru_rk322x.h> 15 #include <asm/arch/hardware.h> 16 #include <dm/lists.h> 17 #include <dt-bindings/clock/rk3228-cru.h> 18 #include <linux/log2.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 enum { 23 VCO_MAX_HZ = 3200U * 1000000, 24 VCO_MIN_HZ = 800 * 1000000, 25 OUTPUT_MAX_HZ = 3200U * 1000000, 26 OUTPUT_MIN_HZ = 24 * 1000000, 27 }; 28 29 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 30 31 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ 32 .refdiv = _refdiv,\ 33 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ), \ 34 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\ 35 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) * \ 36 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz, \ 37 #hz "Hz cannot be hit with PLL "\ 38 "divisors on line " __stringify(__LINE__)); 39 40 /* use integer mode*/ 41 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1); 42 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); 43 44 static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id, 45 const struct pll_div *div) 46 { 47 int pll_id = rk_pll_id(clk_id); 48 struct rk322x_pll *pll = &cru->pll[pll_id]; 49 50 /* All PLLs have same VCO and output frequency range restrictions. */ 51 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; 52 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; 53 54 debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n", 55 pll, div->fbdiv, div->refdiv, div->postdiv1, 56 div->postdiv2, vco_hz, output_hz); 57 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && 58 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ); 59 60 /* use integer mode */ 61 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); 62 /* Power down */ 63 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); 64 65 rk_clrsetreg(&pll->con0, 66 PLL_POSTDIV1_MASK | PLL_FBDIV_MASK, 67 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); 68 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, 69 (div->postdiv2 << PLL_POSTDIV2_SHIFT | 70 div->refdiv << PLL_REFDIV_SHIFT)); 71 72 /* Power Up */ 73 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); 74 75 /* waiting for pll lock */ 76 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) 77 udelay(1); 78 79 return 0; 80 } 81 82 static void rkclk_init(struct rk322x_cru *cru) 83 { 84 u32 aclk_div; 85 u32 hclk_div; 86 u32 pclk_div; 87 88 /* pll enter slow-mode */ 89 rk_clrsetreg(&cru->cru_mode_con, 90 GPLL_MODE_MASK | APLL_MODE_MASK, 91 GPLL_MODE_SLOW << GPLL_MODE_SHIFT | 92 APLL_MODE_SLOW << APLL_MODE_SHIFT); 93 94 /* init pll */ 95 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); 96 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); 97 98 /* 99 * select apll as cpu/core clock pll source and 100 * set up dependent divisors for PERI and ACLK clocks. 101 * core hz : apll = 1:1 102 */ 103 aclk_div = APLL_HZ / CORE_ACLK_HZ - 1; 104 assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7); 105 106 pclk_div = APLL_HZ / CORE_PERI_HZ - 1; 107 assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf); 108 109 rk_clrsetreg(&cru->cru_clksel_con[0], 110 CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK, 111 CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT | 112 0 << CORE_DIV_CON_SHIFT); 113 114 rk_clrsetreg(&cru->cru_clksel_con[1], 115 CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK, 116 aclk_div << CORE_ACLK_DIV_SHIFT | 117 pclk_div << CORE_PERI_DIV_SHIFT); 118 119 /* 120 * select gpll as pd_bus bus clock source and 121 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 122 */ 123 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; 124 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); 125 126 pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1; 127 128 hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1; 129 130 rk_clrsetreg(&cru->cru_clksel_con[0], 131 BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK, 132 BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT | 133 aclk_div << BUS_ACLK_DIV_SHIFT); 134 135 rk_clrsetreg(&cru->cru_clksel_con[1], 136 BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK, 137 pclk_div << BUS_PCLK_DIV_SHIFT | 138 hclk_div << BUS_HCLK_DIV_SHIFT); 139 140 /* 141 * select gpll as pd_peri bus clock source and 142 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 143 */ 144 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; 145 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); 146 147 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); 148 assert((1 << hclk_div) * PERI_HCLK_HZ == 149 PERI_ACLK_HZ && (hclk_div < 0x4)); 150 151 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); 152 assert((1 << pclk_div) * PERI_PCLK_HZ == 153 PERI_ACLK_HZ && pclk_div < 0x8); 154 155 rk_clrsetreg(&cru->cru_clksel_con[10], 156 PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK | 157 PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK, 158 PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT | 159 pclk_div << PERI_PCLK_DIV_SHIFT | 160 hclk_div << PERI_HCLK_DIV_SHIFT | 161 aclk_div << PERI_ACLK_DIV_SHIFT); 162 163 /* PLL enter normal-mode */ 164 rk_clrsetreg(&cru->cru_mode_con, 165 GPLL_MODE_MASK | APLL_MODE_MASK, 166 GPLL_MODE_NORM << GPLL_MODE_SHIFT | 167 APLL_MODE_NORM << APLL_MODE_SHIFT); 168 } 169 170 /* Get pll rate by id */ 171 static uint32_t rkclk_pll_get_rate(struct rk322x_cru *cru, 172 enum rk_clk_id clk_id) 173 { 174 uint32_t refdiv, fbdiv, postdiv1, postdiv2; 175 uint32_t con; 176 int pll_id = rk_pll_id(clk_id); 177 struct rk322x_pll *pll = &cru->pll[pll_id]; 178 static u8 clk_shift[CLK_COUNT] = { 179 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff, 180 GPLL_MODE_SHIFT, 0xff 181 }; 182 static u32 clk_mask[CLK_COUNT] = { 183 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff, 184 GPLL_MODE_MASK, 0xff 185 }; 186 uint shift; 187 uint mask; 188 189 con = readl(&cru->cru_mode_con); 190 shift = clk_shift[clk_id]; 191 mask = clk_mask[clk_id]; 192 193 switch ((con & mask) >> shift) { 194 case GPLL_MODE_SLOW: 195 return OSC_HZ; 196 case GPLL_MODE_NORM: 197 198 /* normal mode */ 199 con = readl(&pll->con0); 200 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; 201 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; 202 con = readl(&pll->con1); 203 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; 204 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; 205 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; 206 default: 207 return 32768; 208 } 209 } 210 211 static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate, 212 int periph) 213 { 214 uint src_rate; 215 uint div, mux; 216 u32 con; 217 218 switch (periph) { 219 case HCLK_EMMC: 220 case SCLK_EMMC: 221 case SCLK_EMMC_SAMPLE: 222 con = readl(&cru->cru_clksel_con[11]); 223 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; 224 con = readl(&cru->cru_clksel_con[12]); 225 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; 226 break; 227 case HCLK_SDMMC: 228 case SCLK_SDMMC: 229 con = readl(&cru->cru_clksel_con[11]); 230 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT; 231 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT; 232 break; 233 default: 234 return -EINVAL; 235 } 236 237 src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate; 238 return DIV_TO_RATE(src_rate, div) / 2; 239 } 240 241 static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate, 242 int periph, uint freq) 243 { 244 int src_clk_div; 245 int mux; 246 247 debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate); 248 249 /* mmc clock defaulg div 2 internal, need provide double in cru */ 250 src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq); 251 252 if (src_clk_div > 128) { 253 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); 254 assert(src_clk_div - 1 < 128); 255 mux = EMMC_SEL_24M; 256 } else { 257 mux = EMMC_SEL_GPLL; 258 } 259 260 switch (periph) { 261 case HCLK_EMMC: 262 case SCLK_EMMC: 263 case SCLK_EMMC_SAMPLE: 264 rk_clrsetreg(&cru->cru_clksel_con[11], 265 EMMC_PLL_MASK, 266 mux << EMMC_PLL_SHIFT); 267 rk_clrsetreg(&cru->cru_clksel_con[12], 268 EMMC_DIV_MASK, 269 (src_clk_div - 1) << EMMC_DIV_SHIFT); 270 break; 271 case HCLK_SDMMC: 272 case SCLK_SDMMC: 273 rk_clrsetreg(&cru->cru_clksel_con[11], 274 MMC0_PLL_MASK | MMC0_DIV_MASK, 275 mux << MMC0_PLL_SHIFT | 276 (src_clk_div - 1) << MMC0_DIV_SHIFT); 277 break; 278 default: 279 return -EINVAL; 280 } 281 282 return rockchip_mmc_get_clk(cru, clk_general_rate, periph); 283 } 284 285 static int rk322x_ddr_set_clk(struct rk322x_cru *cru, unsigned int set_rate) 286 { 287 struct pll_div dpll_cfg; 288 289 /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */ 290 switch (set_rate) { 291 case 400*MHz: 292 dpll_cfg = (struct pll_div) 293 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1}; 294 break; 295 case 600*MHz: 296 dpll_cfg = (struct pll_div) 297 {.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1}; 298 break; 299 case 800*MHz: 300 dpll_cfg = (struct pll_div) 301 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}; 302 break; 303 } 304 305 /* pll enter slow-mode */ 306 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, 307 DPLL_MODE_SLOW << DPLL_MODE_SHIFT); 308 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg); 309 /* PLL enter normal-mode */ 310 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, 311 DPLL_MODE_NORM << DPLL_MODE_SHIFT); 312 313 return set_rate; 314 } 315 316 static ulong rk322x_get_bus_aclk(struct rk322x_cru *cru, ulong gclk_rate) 317 { 318 u32 con; 319 u32 aclk_div; 320 321 con = readl(&cru->cru_clksel_con[0]); 322 aclk_div = ((con & BUS_ACLK_DIV_MASK) >> BUS_ACLK_DIV_SHIFT) + 1; 323 324 return gclk_rate / aclk_div; 325 } 326 327 static ulong rk322x_get_bus_pclk(struct rk322x_cru *cru, ulong gclk_rate) 328 { 329 u32 con; 330 u32 pclk_div; 331 332 con = readl(&cru->cru_clksel_con[1]); 333 pclk_div = ((con & BUS_PCLK_DIV_MASK) >> BUS_PCLK_DIV_SHIFT) + 1; 334 335 return rk322x_get_bus_aclk(cru, gclk_rate) / pclk_div; 336 } 337 338 static ulong rk322x_clk_get_rate(struct clk *clk) 339 { 340 struct rk322x_clk_priv *priv = dev_get_priv(clk->dev); 341 ulong rate, gclk_rate; 342 343 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); 344 switch (clk->id) { 345 case 0 ... 63: 346 rate = rkclk_pll_get_rate(priv->cru, clk->id); 347 break; 348 case HCLK_EMMC: 349 case SCLK_EMMC: 350 case HCLK_SDMMC: 351 case SCLK_SDMMC: 352 rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id); 353 break; 354 case PCLK_GPIO0 ... PCLK_TIMER: 355 rate = rk322x_get_bus_pclk(priv->cru, gclk_rate); 356 break; 357 default: 358 return -ENOENT; 359 } 360 361 return rate; 362 } 363 364 static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate) 365 { 366 struct rk322x_clk_priv *priv = dev_get_priv(clk->dev); 367 ulong new_rate, gclk_rate; 368 369 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); 370 switch (clk->id) { 371 case HCLK_EMMC: 372 case SCLK_EMMC: 373 case HCLK_SDMMC: 374 case SCLK_SDMMC: 375 new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate, 376 clk->id, rate); 377 break; 378 case CLK_DDR: 379 new_rate = rk322x_ddr_set_clk(priv->cru, rate); 380 break; 381 default: 382 return -ENOENT; 383 } 384 385 return new_rate; 386 } 387 388 static struct clk_ops rk322x_clk_ops = { 389 .get_rate = rk322x_clk_get_rate, 390 .set_rate = rk322x_clk_set_rate, 391 }; 392 393 static int rk322x_clk_ofdata_to_platdata(struct udevice *dev) 394 { 395 struct rk322x_clk_priv *priv = dev_get_priv(dev); 396 397 priv->cru = (struct rk322x_cru *)devfdt_get_addr(dev); 398 399 return 0; 400 } 401 402 static int rk322x_clk_probe(struct udevice *dev) 403 { 404 struct rk322x_clk_priv *priv = dev_get_priv(dev); 405 406 rkclk_init(priv->cru); 407 408 return 0; 409 } 410 411 static int rk322x_clk_bind(struct udevice *dev) 412 { 413 int ret; 414 struct udevice *sys_child, *sf_child; 415 struct sysreset_reg *priv; 416 struct softreset_reg *sf_priv; 417 418 /* The reset driver does not have a device node, so bind it here */ 419 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", 420 &sys_child); 421 if (ret) { 422 debug("Warning: No sysreset driver: ret=%d\n", ret); 423 } else { 424 priv = malloc(sizeof(struct sysreset_reg)); 425 priv->glb_srst_fst_value = offsetof(struct rk322x_cru, 426 cru_glb_srst_fst_value); 427 priv->glb_srst_snd_value = offsetof(struct rk322x_cru, 428 cru_glb_srst_snd_value); 429 sys_child->priv = priv; 430 } 431 432 ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset", 433 dev_ofnode(dev), &sf_child); 434 if (ret) { 435 debug("Warning: No rockchip reset driver: ret=%d\n", ret); 436 } else { 437 sf_priv = malloc(sizeof(struct softreset_reg)); 438 sf_priv->sf_reset_offset = offsetof(struct rk322x_cru, 439 cru_softrst_con[0]); 440 sf_priv->sf_reset_num = 9; 441 sf_child->priv = sf_priv; 442 } 443 444 return 0; 445 } 446 447 static const struct udevice_id rk322x_clk_ids[] = { 448 { .compatible = "rockchip,rk3228-cru" }, 449 { } 450 }; 451 452 U_BOOT_DRIVER(rockchip_rk322x_cru) = { 453 .name = "clk_rk322x", 454 .id = UCLASS_CLK, 455 .of_match = rk322x_clk_ids, 456 .priv_auto_alloc_size = sizeof(struct rk322x_clk_priv), 457 .ofdata_to_platdata = rk322x_clk_ofdata_to_platdata, 458 .ops = &rk322x_clk_ops, 459 .bind = rk322x_clk_bind, 460 .probe = rk322x_clk_probe, 461 }; 462