1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <clk-uclass.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <syscon.h> 12 #include <asm/io.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch/cru_rk3036.h> 15 #include <asm/arch/hardware.h> 16 #include <dm/lists.h> 17 #include <dt-bindings/clock/rk3036-cru.h> 18 #include <linux/log2.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 enum { 23 VCO_MAX_HZ = 2400U * 1000000, 24 VCO_MIN_HZ = 600 * 1000000, 25 OUTPUT_MAX_HZ = 2400U * 1000000, 26 OUTPUT_MIN_HZ = 24 * 1000000, 27 }; 28 29 #ifndef CONFIG_SPL_BUILD 30 #define RK3036_CLK_DUMP(_id, _name, _iscru) \ 31 { \ 32 .id = _id, \ 33 .name = _name, \ 34 .is_cru = _iscru, \ 35 } 36 37 static const struct rk3036_clk_info clks_dump[] = { 38 RK3036_CLK_DUMP(PLL_APLL, "apll", true), 39 RK3036_CLK_DUMP(PLL_DPLL, "dpll", true), 40 RK3036_CLK_DUMP(PLL_GPLL, "gpll", true), 41 }; 42 #endif 43 44 #define RATE_TO_DIV(input_rate, output_rate) \ 45 ((input_rate) / (output_rate) - 1); 46 47 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 48 49 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ 50 .refdiv = _refdiv,\ 51 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ 52 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\ 53 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\ 54 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\ 55 #hz "Hz cannot be hit with PLL "\ 56 "divisors on line " __stringify(__LINE__)); 57 58 /* use integer mode*/ 59 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1); 60 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); 61 62 static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id, 63 const struct pll_div *div) 64 { 65 int pll_id = rk_pll_id(clk_id); 66 struct rk3036_pll *pll = &cru->pll[pll_id]; 67 68 /* All PLLs have same VCO and output frequency range restrictions. */ 69 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; 70 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; 71 72 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, postdiv2=%d,\ 73 vco=%u Hz, output=%u Hz\n", 74 pll, div->fbdiv, div->refdiv, div->postdiv1, 75 div->postdiv2, vco_hz, output_hz); 76 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && 77 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ); 78 79 /* use integer mode */ 80 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); 81 82 /* Power down */ 83 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); 84 85 rk_clrsetreg(&pll->con0, 86 PLL_POSTDIV1_MASK | PLL_FBDIV_MASK, 87 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); 88 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, 89 (div->postdiv2 << PLL_POSTDIV2_SHIFT | 90 div->refdiv << PLL_REFDIV_SHIFT)); 91 92 /* Power Up */ 93 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); 94 95 /* waiting for pll lock */ 96 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) 97 udelay(1); 98 99 return 0; 100 } 101 102 static void rkclk_init(struct rk3036_cru *cru) 103 { 104 u32 aclk_div; 105 u32 hclk_div; 106 u32 pclk_div; 107 108 /* pll enter slow-mode */ 109 rk_clrsetreg(&cru->cru_mode_con, 110 GPLL_MODE_MASK | APLL_MODE_MASK, 111 GPLL_MODE_SLOW << GPLL_MODE_SHIFT | 112 APLL_MODE_SLOW << APLL_MODE_SHIFT); 113 114 /* init pll */ 115 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); 116 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); 117 118 /* 119 * select apll as cpu/core clock pll source and 120 * set up dependent divisors for PERI and ACLK clocks. 121 * core hz : apll = 1:1 122 */ 123 aclk_div = APLL_HZ / CORE_ACLK_HZ - 1; 124 assert((aclk_div + 1) * CORE_ACLK_HZ <= APLL_HZ && aclk_div < 0x7); 125 126 pclk_div = APLL_HZ / CORE_PERI_HZ - 1; 127 assert((pclk_div + 1) * CORE_PERI_HZ <= APLL_HZ && pclk_div < 0xf); 128 129 rk_clrsetreg(&cru->cru_clksel_con[0], 130 CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK, 131 CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT | 132 0 << CORE_DIV_CON_SHIFT); 133 134 rk_clrsetreg(&cru->cru_clksel_con[1], 135 CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK, 136 aclk_div << CORE_ACLK_DIV_SHIFT | 137 pclk_div << CORE_PERI_DIV_SHIFT); 138 139 /* 140 * select gpll as pd_bus bus clock source and 141 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 142 */ 143 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; 144 assert((aclk_div + 1) * BUS_ACLK_HZ <= GPLL_HZ && aclk_div <= 0x1f); 145 146 pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1; 147 assert((pclk_div + 1) * BUS_PCLK_HZ <= BUS_ACLK_HZ && pclk_div <= 0x7); 148 149 hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1; 150 assert((hclk_div + 1) * BUS_HCLK_HZ <= BUS_ACLK_HZ && hclk_div <= 0x3); 151 152 rk_clrsetreg(&cru->cru_clksel_con[0], 153 BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK, 154 BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT | 155 aclk_div << BUS_ACLK_DIV_SHIFT); 156 157 rk_clrsetreg(&cru->cru_clksel_con[1], 158 BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK, 159 pclk_div << BUS_PCLK_DIV_SHIFT | 160 hclk_div << BUS_HCLK_DIV_SHIFT); 161 162 /* 163 * select gpll as pd_peri bus clock source and 164 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 165 */ 166 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; 167 assert((aclk_div + 1) * PERI_ACLK_HZ <= GPLL_HZ && aclk_div < 0x1f); 168 169 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); 170 assert((1 << hclk_div) * PERI_HCLK_HZ <= 171 PERI_ACLK_HZ && (hclk_div < 0x4)); 172 173 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); 174 assert((1 << pclk_div) * PERI_PCLK_HZ <= 175 PERI_ACLK_HZ && pclk_div < 0x8); 176 177 rk_clrsetreg(&cru->cru_clksel_con[10], 178 PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK | 179 PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK, 180 PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT | 181 pclk_div << PERI_PCLK_DIV_SHIFT | 182 hclk_div << PERI_HCLK_DIV_SHIFT | 183 aclk_div << PERI_ACLK_DIV_SHIFT); 184 185 /* PLL enter normal-mode */ 186 rk_clrsetreg(&cru->cru_mode_con, 187 GPLL_MODE_MASK | APLL_MODE_MASK, 188 GPLL_MODE_NORM << GPLL_MODE_SHIFT | 189 APLL_MODE_NORM << APLL_MODE_SHIFT); 190 } 191 192 /* Get pll rate by id */ 193 static uint32_t rkclk_pll_get_rate(struct rk3036_cru *cru, 194 enum rk_clk_id clk_id) 195 { 196 uint32_t refdiv, fbdiv, postdiv1, postdiv2; 197 uint32_t con; 198 int pll_id = rk_pll_id(clk_id); 199 struct rk3036_pll *pll = &cru->pll[pll_id]; 200 static u8 clk_shift[CLK_COUNT] = { 201 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff, 202 GPLL_MODE_SHIFT, 0xff 203 }; 204 static u32 clk_mask[CLK_COUNT] = { 205 0xffffffff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xffffffff, 206 GPLL_MODE_MASK, 0xffffffff 207 }; 208 uint shift; 209 uint mask; 210 211 con = readl(&cru->cru_mode_con); 212 shift = clk_shift[clk_id]; 213 mask = clk_mask[clk_id]; 214 215 switch ((con & mask) >> shift) { 216 case GPLL_MODE_SLOW: 217 return OSC_HZ; 218 case GPLL_MODE_NORM: 219 220 /* normal mode */ 221 con = readl(&pll->con0); 222 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; 223 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; 224 con = readl(&pll->con1); 225 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; 226 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; 227 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; 228 case GPLL_MODE_DEEP: 229 default: 230 return 32768; 231 } 232 } 233 234 static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate, 235 int periph) 236 { 237 uint src_rate; 238 uint div, mux; 239 u32 con; 240 241 switch (periph) { 242 case HCLK_EMMC: 243 case SCLK_EMMC: 244 con = readl(&cru->cru_clksel_con[12]); 245 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; 246 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; 247 break; 248 case HCLK_SDIO: 249 case SCLK_SDIO: 250 con = readl(&cru->cru_clksel_con[12]); 251 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT; 252 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT; 253 break; 254 default: 255 return -EINVAL; 256 } 257 258 src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate; 259 return DIV_TO_RATE(src_rate, div) / 2; 260 } 261 262 static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate, 263 int periph, uint freq) 264 { 265 int src_clk_div; 266 int mux; 267 268 debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate); 269 270 /* mmc clock auto divide 2 in internal */ 271 src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq); 272 273 if (src_clk_div > 128) { 274 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); 275 assert(src_clk_div - 1 < 128); 276 mux = EMMC_SEL_24M; 277 } else { 278 mux = EMMC_SEL_GPLL; 279 } 280 281 switch (periph) { 282 case HCLK_EMMC: 283 case SCLK_EMMC: 284 rk_clrsetreg(&cru->cru_clksel_con[12], 285 EMMC_PLL_MASK | EMMC_DIV_MASK, 286 mux << EMMC_PLL_SHIFT | 287 (src_clk_div - 1) << EMMC_DIV_SHIFT); 288 break; 289 case HCLK_SDIO: 290 case SCLK_SDIO: 291 rk_clrsetreg(&cru->cru_clksel_con[11], 292 MMC0_PLL_MASK | MMC0_DIV_MASK, 293 mux << MMC0_PLL_SHIFT | 294 (src_clk_div - 1) << MMC0_DIV_SHIFT); 295 break; 296 default: 297 return -EINVAL; 298 } 299 300 return rockchip_mmc_get_clk(cru, clk_general_rate, periph); 301 } 302 303 static ulong rk3036_clk_get_rate(struct clk *clk) 304 { 305 struct rk3036_clk_priv *priv = dev_get_priv(clk->dev); 306 307 switch (clk->id) { 308 case 0 ... 63: 309 return rkclk_pll_get_rate(priv->cru, clk->id); 310 default: 311 return -ENOENT; 312 } 313 } 314 315 static ulong rk3036_clk_set_rate(struct clk *clk, ulong rate) 316 { 317 struct rk3036_clk_priv *priv = dev_get_priv(clk->dev); 318 ulong new_rate, gclk_rate; 319 320 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); 321 switch (clk->id) { 322 case 0 ... 63: 323 return 0; 324 case HCLK_EMMC: 325 case SCLK_EMMC: 326 new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate, 327 clk->id, rate); 328 break; 329 default: 330 return -ENOENT; 331 } 332 333 return new_rate; 334 } 335 336 static struct clk_ops rk3036_clk_ops = { 337 .get_rate = rk3036_clk_get_rate, 338 .set_rate = rk3036_clk_set_rate, 339 }; 340 341 static int rk3036_clk_ofdata_to_platdata(struct udevice *dev) 342 { 343 struct rk3036_clk_priv *priv = dev_get_priv(dev); 344 345 priv->cru = dev_read_addr_ptr(dev); 346 347 return 0; 348 } 349 350 static int rk3036_clk_probe(struct udevice *dev) 351 { 352 struct rk3036_clk_priv *priv = dev_get_priv(dev); 353 354 priv->sync_kernel = false; 355 if (!priv->armclk_enter_hz) 356 priv->armclk_enter_hz = rkclk_pll_get_rate(priv->cru, 357 CLK_ARM); 358 rkclk_init(priv->cru); 359 if (!priv->armclk_init_hz) 360 priv->armclk_init_hz = rkclk_pll_get_rate(priv->cru, 361 CLK_ARM); 362 363 return 0; 364 } 365 366 static int rk3036_clk_bind(struct udevice *dev) 367 { 368 int ret; 369 struct udevice *sys_child, *sf_child; 370 struct sysreset_reg *priv; 371 struct softreset_reg *sf_priv; 372 373 /* The reset driver does not have a device node, so bind it here */ 374 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", 375 &sys_child); 376 if (ret) { 377 debug("Warning: No sysreset driver: ret=%d\n", ret); 378 } else { 379 priv = malloc(sizeof(struct sysreset_reg)); 380 priv->glb_srst_fst_value = offsetof(struct rk3036_cru, 381 cru_glb_srst_fst_value); 382 priv->glb_srst_snd_value = offsetof(struct rk3036_cru, 383 cru_glb_srst_snd_value); 384 sys_child->priv = priv; 385 } 386 387 ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset", 388 dev_ofnode(dev), &sf_child); 389 if (ret) { 390 debug("Warning: No rockchip reset driver: ret=%d\n", ret); 391 } else { 392 sf_priv = malloc(sizeof(struct softreset_reg)); 393 sf_priv->sf_reset_offset = offsetof(struct rk3036_cru, 394 cru_softrst_con[0]); 395 sf_priv->sf_reset_num = 9; 396 sf_child->priv = sf_priv; 397 } 398 399 return 0; 400 } 401 402 static const struct udevice_id rk3036_clk_ids[] = { 403 { .compatible = "rockchip,rk3036-cru" }, 404 { } 405 }; 406 407 U_BOOT_DRIVER(rockchip_rk3036_cru) = { 408 .name = "clk_rk3036", 409 .id = UCLASS_CLK, 410 .of_match = rk3036_clk_ids, 411 .priv_auto_alloc_size = sizeof(struct rk3036_clk_priv), 412 .ofdata_to_platdata = rk3036_clk_ofdata_to_platdata, 413 .ops = &rk3036_clk_ops, 414 .bind = rk3036_clk_bind, 415 .probe = rk3036_clk_probe, 416 }; 417 418 #ifndef CONFIG_SPL_BUILD 419 /** 420 * soc_clk_dump() - Print clock frequencies 421 * Returns zero on success 422 * 423 * Implementation for the clk dump command. 424 */ 425 int soc_clk_dump(void) 426 { 427 struct udevice *cru_dev; 428 struct rk3036_clk_priv *priv; 429 const struct rk3036_clk_info *clk_dump; 430 struct clk clk; 431 unsigned long clk_count = ARRAY_SIZE(clks_dump); 432 unsigned long rate; 433 int i, ret; 434 435 ret = uclass_get_device_by_driver(UCLASS_CLK, 436 DM_GET_DRIVER(rockchip_rk3036_cru), 437 &cru_dev); 438 if (ret) { 439 printf("%s failed to get cru device\n", __func__); 440 return ret; 441 } 442 443 priv = dev_get_priv(cru_dev); 444 printf("CLK: (%s. arm: enter %lu KHz, init %lu KHz, kernel %lu%s)\n", 445 priv->sync_kernel ? "sync kernel" : "uboot", 446 priv->armclk_enter_hz / 1000, 447 priv->armclk_init_hz / 1000, 448 priv->set_armclk_rate ? priv->armclk_hz / 1000 : 0, 449 priv->set_armclk_rate ? " KHz" : "N/A"); 450 for (i = 0; i < clk_count; i++) { 451 clk_dump = &clks_dump[i]; 452 if (clk_dump->name) { 453 clk.id = clk_dump->id; 454 if (clk_dump->is_cru) 455 ret = clk_request(cru_dev, &clk); 456 if (ret < 0) 457 return ret; 458 459 rate = clk_get_rate(&clk); 460 clk_free(&clk); 461 if (i == 0) { 462 if (rate < 0) 463 printf(" %s %s\n", clk_dump->name, 464 "unknown"); 465 else 466 printf(" %s %lu KHz\n", clk_dump->name, 467 rate / 1000); 468 } else { 469 if (rate < 0) 470 printf(" %s %s\n", clk_dump->name, 471 "unknown"); 472 else 473 printf(" %s %lu KHz\n", clk_dump->name, 474 rate / 1000); 475 } 476 } 477 } 478 479 return 0; 480 } 481 #endif 482 483