1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <clk-uclass.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <syscon.h> 12 #include <asm/io.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch/cru_rk3036.h> 15 #include <asm/arch/hardware.h> 16 #include <dm/lists.h> 17 #include <dt-bindings/clock/rk3036-cru.h> 18 #include <linux/log2.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 enum { 23 VCO_MAX_HZ = 2400U * 1000000, 24 VCO_MIN_HZ = 600 * 1000000, 25 OUTPUT_MAX_HZ = 2400U * 1000000, 26 OUTPUT_MIN_HZ = 24 * 1000000, 27 }; 28 29 #define RATE_TO_DIV(input_rate, output_rate) \ 30 ((input_rate) / (output_rate) - 1); 31 32 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 33 34 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ 35 .refdiv = _refdiv,\ 36 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ 37 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\ 38 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\ 39 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\ 40 #hz "Hz cannot be hit with PLL "\ 41 "divisors on line " __stringify(__LINE__)); 42 43 /* use integer mode*/ 44 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1); 45 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); 46 47 static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id, 48 const struct pll_div *div) 49 { 50 int pll_id = rk_pll_id(clk_id); 51 struct rk3036_pll *pll = &cru->pll[pll_id]; 52 53 /* All PLLs have same VCO and output frequency range restrictions. */ 54 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; 55 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; 56 57 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, postdiv2=%d,\ 58 vco=%u Hz, output=%u Hz\n", 59 pll, div->fbdiv, div->refdiv, div->postdiv1, 60 div->postdiv2, vco_hz, output_hz); 61 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && 62 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ); 63 64 /* use integer mode */ 65 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); 66 67 /* Power down */ 68 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); 69 70 rk_clrsetreg(&pll->con0, 71 PLL_POSTDIV1_MASK | PLL_FBDIV_MASK, 72 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); 73 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, 74 (div->postdiv2 << PLL_POSTDIV2_SHIFT | 75 div->refdiv << PLL_REFDIV_SHIFT)); 76 77 /* Power Up */ 78 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); 79 80 /* waiting for pll lock */ 81 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) 82 udelay(1); 83 84 return 0; 85 } 86 87 static void rkclk_init(struct rk3036_cru *cru) 88 { 89 u32 aclk_div; 90 u32 hclk_div; 91 u32 pclk_div; 92 93 /* pll enter slow-mode */ 94 rk_clrsetreg(&cru->cru_mode_con, 95 GPLL_MODE_MASK | APLL_MODE_MASK, 96 GPLL_MODE_SLOW << GPLL_MODE_SHIFT | 97 APLL_MODE_SLOW << APLL_MODE_SHIFT); 98 99 /* init pll */ 100 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); 101 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); 102 103 /* 104 * select apll as cpu/core clock pll source and 105 * set up dependent divisors for PERI and ACLK clocks. 106 * core hz : apll = 1:1 107 */ 108 aclk_div = APLL_HZ / CORE_ACLK_HZ - 1; 109 assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7); 110 111 pclk_div = APLL_HZ / CORE_PERI_HZ - 1; 112 assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf); 113 114 rk_clrsetreg(&cru->cru_clksel_con[0], 115 CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK, 116 CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT | 117 0 << CORE_DIV_CON_SHIFT); 118 119 rk_clrsetreg(&cru->cru_clksel_con[1], 120 CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK, 121 aclk_div << CORE_ACLK_DIV_SHIFT | 122 pclk_div << CORE_PERI_DIV_SHIFT); 123 124 /* 125 * select gpll as pd_bus bus clock source and 126 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 127 */ 128 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; 129 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); 130 131 pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1; 132 assert((pclk_div + 1) * BUS_PCLK_HZ == BUS_ACLK_HZ && pclk_div <= 0x7); 133 134 hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1; 135 assert((hclk_div + 1) * BUS_HCLK_HZ == BUS_ACLK_HZ && hclk_div <= 0x3); 136 137 rk_clrsetreg(&cru->cru_clksel_con[0], 138 BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK, 139 BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT | 140 aclk_div << BUS_ACLK_DIV_SHIFT); 141 142 rk_clrsetreg(&cru->cru_clksel_con[1], 143 BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK, 144 pclk_div << BUS_PCLK_DIV_SHIFT | 145 hclk_div << BUS_HCLK_DIV_SHIFT); 146 147 /* 148 * select gpll as pd_peri bus clock source and 149 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 150 */ 151 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; 152 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); 153 154 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); 155 assert((1 << hclk_div) * PERI_HCLK_HZ == 156 PERI_ACLK_HZ && (hclk_div < 0x4)); 157 158 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); 159 assert((1 << pclk_div) * PERI_PCLK_HZ == 160 PERI_ACLK_HZ && pclk_div < 0x8); 161 162 rk_clrsetreg(&cru->cru_clksel_con[10], 163 PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK | 164 PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK, 165 PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT | 166 pclk_div << PERI_PCLK_DIV_SHIFT | 167 hclk_div << PERI_HCLK_DIV_SHIFT | 168 aclk_div << PERI_ACLK_DIV_SHIFT); 169 170 /* PLL enter normal-mode */ 171 rk_clrsetreg(&cru->cru_mode_con, 172 GPLL_MODE_MASK | APLL_MODE_MASK, 173 GPLL_MODE_NORM << GPLL_MODE_SHIFT | 174 APLL_MODE_NORM << APLL_MODE_SHIFT); 175 } 176 177 /* Get pll rate by id */ 178 static uint32_t rkclk_pll_get_rate(struct rk3036_cru *cru, 179 enum rk_clk_id clk_id) 180 { 181 uint32_t refdiv, fbdiv, postdiv1, postdiv2; 182 uint32_t con; 183 int pll_id = rk_pll_id(clk_id); 184 struct rk3036_pll *pll = &cru->pll[pll_id]; 185 static u8 clk_shift[CLK_COUNT] = { 186 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff, 187 GPLL_MODE_SHIFT, 0xff 188 }; 189 static u32 clk_mask[CLK_COUNT] = { 190 0xffffffff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xffffffff, 191 GPLL_MODE_MASK, 0xffffffff 192 }; 193 uint shift; 194 uint mask; 195 196 con = readl(&cru->cru_mode_con); 197 shift = clk_shift[clk_id]; 198 mask = clk_mask[clk_id]; 199 200 switch ((con & mask) >> shift) { 201 case GPLL_MODE_SLOW: 202 return OSC_HZ; 203 case GPLL_MODE_NORM: 204 205 /* normal mode */ 206 con = readl(&pll->con0); 207 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; 208 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; 209 con = readl(&pll->con1); 210 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; 211 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; 212 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; 213 case GPLL_MODE_DEEP: 214 default: 215 return 32768; 216 } 217 } 218 219 static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate, 220 int periph) 221 { 222 uint src_rate; 223 uint div, mux; 224 u32 con; 225 226 switch (periph) { 227 case HCLK_EMMC: 228 case SCLK_EMMC: 229 con = readl(&cru->cru_clksel_con[12]); 230 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; 231 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; 232 break; 233 case HCLK_SDIO: 234 case SCLK_SDIO: 235 con = readl(&cru->cru_clksel_con[12]); 236 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT; 237 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT; 238 break; 239 default: 240 return -EINVAL; 241 } 242 243 src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate; 244 return DIV_TO_RATE(src_rate, div) / 2; 245 } 246 247 static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate, 248 int periph, uint freq) 249 { 250 int src_clk_div; 251 int mux; 252 253 debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate); 254 255 /* mmc clock auto divide 2 in internal */ 256 src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq); 257 258 if (src_clk_div > 128) { 259 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); 260 assert(src_clk_div - 1 < 128); 261 mux = EMMC_SEL_24M; 262 } else { 263 mux = EMMC_SEL_GPLL; 264 } 265 266 switch (periph) { 267 case HCLK_EMMC: 268 case SCLK_EMMC: 269 rk_clrsetreg(&cru->cru_clksel_con[12], 270 EMMC_PLL_MASK | EMMC_DIV_MASK, 271 mux << EMMC_PLL_SHIFT | 272 (src_clk_div - 1) << EMMC_DIV_SHIFT); 273 break; 274 case HCLK_SDIO: 275 case SCLK_SDIO: 276 rk_clrsetreg(&cru->cru_clksel_con[11], 277 MMC0_PLL_MASK | MMC0_DIV_MASK, 278 mux << MMC0_PLL_SHIFT | 279 (src_clk_div - 1) << MMC0_DIV_SHIFT); 280 break; 281 default: 282 return -EINVAL; 283 } 284 285 return rockchip_mmc_get_clk(cru, clk_general_rate, periph); 286 } 287 288 static ulong rk3036_clk_get_rate(struct clk *clk) 289 { 290 struct rk3036_clk_priv *priv = dev_get_priv(clk->dev); 291 292 switch (clk->id) { 293 case 0 ... 63: 294 return rkclk_pll_get_rate(priv->cru, clk->id); 295 default: 296 return -ENOENT; 297 } 298 } 299 300 static ulong rk3036_clk_set_rate(struct clk *clk, ulong rate) 301 { 302 struct rk3036_clk_priv *priv = dev_get_priv(clk->dev); 303 ulong new_rate, gclk_rate; 304 305 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); 306 switch (clk->id) { 307 case 0 ... 63: 308 return 0; 309 case HCLK_EMMC: 310 case SCLK_EMMC: 311 new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate, 312 clk->id, rate); 313 break; 314 default: 315 return -ENOENT; 316 } 317 318 return new_rate; 319 } 320 321 static struct clk_ops rk3036_clk_ops = { 322 .get_rate = rk3036_clk_get_rate, 323 .set_rate = rk3036_clk_set_rate, 324 }; 325 326 static int rk3036_clk_ofdata_to_platdata(struct udevice *dev) 327 { 328 struct rk3036_clk_priv *priv = dev_get_priv(dev); 329 330 priv->cru = dev_read_addr_ptr(dev); 331 332 return 0; 333 } 334 335 static int rk3036_clk_probe(struct udevice *dev) 336 { 337 struct rk3036_clk_priv *priv = dev_get_priv(dev); 338 339 rkclk_init(priv->cru); 340 341 return 0; 342 } 343 344 static int rk3036_clk_bind(struct udevice *dev) 345 { 346 int ret; 347 struct udevice *sys_child, *sf_child; 348 struct sysreset_reg *priv; 349 struct softreset_reg *sf_priv; 350 351 /* The reset driver does not have a device node, so bind it here */ 352 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", 353 &sys_child); 354 if (ret) { 355 debug("Warning: No sysreset driver: ret=%d\n", ret); 356 } else { 357 priv = malloc(sizeof(struct sysreset_reg)); 358 priv->glb_srst_fst_value = offsetof(struct rk3036_cru, 359 cru_glb_srst_fst_value); 360 priv->glb_srst_snd_value = offsetof(struct rk3036_cru, 361 cru_glb_srst_snd_value); 362 sys_child->priv = priv; 363 } 364 365 ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset", 366 dev_ofnode(dev), &sf_child); 367 if (ret) { 368 debug("Warning: No rockchip reset driver: ret=%d\n", ret); 369 } else { 370 sf_priv = malloc(sizeof(struct softreset_reg)); 371 sf_priv->sf_reset_offset = offsetof(struct rk3036_cru, 372 cru_softrst_con[0]); 373 sf_priv->sf_reset_num = 9; 374 sf_child->priv = sf_priv; 375 } 376 377 return 0; 378 } 379 380 static const struct udevice_id rk3036_clk_ids[] = { 381 { .compatible = "rockchip,rk3036-cru" }, 382 { } 383 }; 384 385 U_BOOT_DRIVER(rockchip_rk3036_cru) = { 386 .name = "clk_rk3036", 387 .id = UCLASS_CLK, 388 .of_match = rk3036_clk_ids, 389 .priv_auto_alloc_size = sizeof(struct rk3036_clk_priv), 390 .ofdata_to_platdata = rk3036_clk_ofdata_to_platdata, 391 .ops = &rk3036_clk_ops, 392 .bind = rk3036_clk_bind, 393 .probe = rk3036_clk_probe, 394 }; 395