1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <clk-uclass.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <syscon.h> 12 #include <asm/io.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch/cru_rk3036.h> 15 #include <asm/arch/hardware.h> 16 #include <dm/lists.h> 17 #include <dt-bindings/clock/rk3036-cru.h> 18 #include <linux/log2.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 enum { 23 VCO_MAX_HZ = 2400U * 1000000, 24 VCO_MIN_HZ = 600 * 1000000, 25 OUTPUT_MAX_HZ = 2400U * 1000000, 26 OUTPUT_MIN_HZ = 24 * 1000000, 27 }; 28 29 #ifndef CONFIG_SPL_BUILD 30 #define RK3036_CLK_DUMP(_id, _name, _iscru) \ 31 { \ 32 .id = _id, \ 33 .name = _name, \ 34 .is_cru = _iscru, \ 35 } 36 37 static const struct rk3036_clk_info clks_dump[] = { 38 RK3036_CLK_DUMP(PLL_APLL, "apll", true), 39 RK3036_CLK_DUMP(PLL_DPLL, "dpll", true), 40 RK3036_CLK_DUMP(PLL_GPLL, "gpll", true), 41 }; 42 #endif 43 44 #define RATE_TO_DIV(input_rate, output_rate) \ 45 ((input_rate) / (output_rate) - 1); 46 47 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 48 49 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ 50 .refdiv = _refdiv,\ 51 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ 52 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\ 53 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\ 54 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\ 55 #hz "Hz cannot be hit with PLL "\ 56 "divisors on line " __stringify(__LINE__)); 57 58 /* use integer mode*/ 59 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1); 60 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); 61 62 static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id, 63 const struct pll_div *div) 64 { 65 int pll_id = rk_pll_id(clk_id); 66 struct rk3036_pll *pll = &cru->pll[pll_id]; 67 68 /* All PLLs have same VCO and output frequency range restrictions. */ 69 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; 70 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; 71 72 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, postdiv2=%d,\ 73 vco=%u Hz, output=%u Hz\n", 74 pll, div->fbdiv, div->refdiv, div->postdiv1, 75 div->postdiv2, vco_hz, output_hz); 76 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && 77 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ); 78 79 /* use integer mode */ 80 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); 81 82 /* Power down */ 83 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); 84 85 rk_clrsetreg(&pll->con0, 86 PLL_POSTDIV1_MASK | PLL_FBDIV_MASK, 87 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); 88 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, 89 (div->postdiv2 << PLL_POSTDIV2_SHIFT | 90 div->refdiv << PLL_REFDIV_SHIFT)); 91 92 /* Power Up */ 93 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); 94 95 /* waiting for pll lock */ 96 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) 97 udelay(1); 98 99 return 0; 100 } 101 102 static void rkclk_init(struct rk3036_cru *cru) 103 { 104 u32 aclk_div; 105 u32 hclk_div; 106 u32 pclk_div; 107 u32 nandc_div; 108 109 /* pll enter slow-mode */ 110 rk_clrsetreg(&cru->cru_mode_con, 111 GPLL_MODE_MASK | APLL_MODE_MASK, 112 GPLL_MODE_SLOW << GPLL_MODE_SHIFT | 113 APLL_MODE_SLOW << APLL_MODE_SHIFT); 114 115 /* init pll */ 116 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); 117 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); 118 119 /* 120 * select apll as cpu/core clock pll source and 121 * set up dependent divisors for PERI and ACLK clocks. 122 * core hz : apll = 1:1 123 */ 124 aclk_div = APLL_HZ / CORE_ACLK_HZ - 1; 125 assert((aclk_div + 1) * CORE_ACLK_HZ <= APLL_HZ && aclk_div < 0x7); 126 127 pclk_div = APLL_HZ / CORE_PERI_HZ - 1; 128 assert((pclk_div + 1) * CORE_PERI_HZ <= APLL_HZ && pclk_div < 0xf); 129 130 rk_clrsetreg(&cru->cru_clksel_con[0], 131 CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK, 132 CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT | 133 0 << CORE_DIV_CON_SHIFT); 134 135 rk_clrsetreg(&cru->cru_clksel_con[1], 136 CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK, 137 aclk_div << CORE_ACLK_DIV_SHIFT | 138 pclk_div << CORE_PERI_DIV_SHIFT); 139 140 /* 141 * select gpll as pd_bus bus clock source and 142 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 143 */ 144 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; 145 assert((aclk_div + 1) * BUS_ACLK_HZ <= GPLL_HZ && aclk_div <= 0x1f); 146 147 pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1; 148 assert((pclk_div + 1) * BUS_PCLK_HZ <= BUS_ACLK_HZ && pclk_div <= 0x7); 149 150 hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1; 151 assert((hclk_div + 1) * BUS_HCLK_HZ <= BUS_ACLK_HZ && hclk_div <= 0x3); 152 153 rk_clrsetreg(&cru->cru_clksel_con[0], 154 BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK, 155 BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT | 156 aclk_div << BUS_ACLK_DIV_SHIFT); 157 158 rk_clrsetreg(&cru->cru_clksel_con[1], 159 BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK, 160 pclk_div << BUS_PCLK_DIV_SHIFT | 161 hclk_div << BUS_HCLK_DIV_SHIFT); 162 163 /* 164 * select gpll as pd_peri bus clock source and 165 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 166 */ 167 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; 168 assert((aclk_div + 1) * PERI_ACLK_HZ <= GPLL_HZ && aclk_div < 0x1f); 169 170 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); 171 assert((1 << hclk_div) * PERI_HCLK_HZ <= 172 PERI_ACLK_HZ && (hclk_div < 0x4)); 173 174 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); 175 assert((1 << pclk_div) * PERI_PCLK_HZ <= 176 PERI_ACLK_HZ && pclk_div < 0x8); 177 178 rk_clrsetreg(&cru->cru_clksel_con[10], 179 PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK | 180 PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK, 181 PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT | 182 pclk_div << PERI_PCLK_DIV_SHIFT | 183 hclk_div << PERI_HCLK_DIV_SHIFT | 184 aclk_div << PERI_ACLK_DIV_SHIFT); 185 186 nandc_div = DIV_ROUND_UP(GPLL_HZ, 150 * 1000000); 187 188 rk_clrsetreg(&cru->cru_clksel_con[16], 189 NANDC_PLL_MASK | NANDC_DIV_MASK, 190 NANDC_SEL_GPLL << NANDC_PLL_SHIFT | 191 nandc_div << NANDC_DIV_SHIFT); 192 193 /* PLL enter normal-mode */ 194 rk_clrsetreg(&cru->cru_mode_con, 195 GPLL_MODE_MASK | APLL_MODE_MASK, 196 GPLL_MODE_NORM << GPLL_MODE_SHIFT | 197 APLL_MODE_NORM << APLL_MODE_SHIFT); 198 } 199 200 /* Get pll rate by id */ 201 static uint32_t rkclk_pll_get_rate(struct rk3036_cru *cru, 202 enum rk_clk_id clk_id) 203 { 204 uint32_t refdiv, fbdiv, postdiv1, postdiv2; 205 uint32_t con; 206 int pll_id = rk_pll_id(clk_id); 207 struct rk3036_pll *pll = &cru->pll[pll_id]; 208 static u8 clk_shift[CLK_COUNT] = { 209 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff, 210 GPLL_MODE_SHIFT, 0xff 211 }; 212 static u32 clk_mask[CLK_COUNT] = { 213 0xffffffff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xffffffff, 214 GPLL_MODE_MASK, 0xffffffff 215 }; 216 uint shift; 217 uint mask; 218 219 con = readl(&cru->cru_mode_con); 220 shift = clk_shift[clk_id]; 221 mask = clk_mask[clk_id]; 222 223 switch ((con & mask) >> shift) { 224 case GPLL_MODE_SLOW: 225 return OSC_HZ; 226 case GPLL_MODE_NORM: 227 228 /* normal mode */ 229 con = readl(&pll->con0); 230 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; 231 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; 232 con = readl(&pll->con1); 233 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; 234 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; 235 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; 236 case GPLL_MODE_DEEP: 237 default: 238 return 32768; 239 } 240 } 241 242 static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate, 243 int periph) 244 { 245 uint src_rate; 246 uint div, mux; 247 u32 con; 248 249 switch (periph) { 250 case HCLK_EMMC: 251 case SCLK_EMMC: 252 con = readl(&cru->cru_clksel_con[12]); 253 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; 254 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; 255 break; 256 case HCLK_SDIO: 257 case SCLK_SDIO: 258 con = readl(&cru->cru_clksel_con[12]); 259 mux = (con & SDIO_PLL_MASK) >> SDIO_PLL_SHIFT; 260 con = readl(&cru->cru_clksel_con[11]); 261 div = (con & SDIO_DIV_MASK) >> SDIO_DIV_SHIFT; 262 break; 263 case HCLK_SDMMC: 264 case SCLK_SDMMC: 265 con = readl(&cru->cru_clksel_con[12]); 266 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT; 267 con = readl(&cru->cru_clksel_con[11]); 268 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT; 269 break; 270 default: 271 return -EINVAL; 272 } 273 274 src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate; 275 return DIV_TO_RATE(src_rate, div) / 2; 276 } 277 278 static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate, 279 int periph, uint freq) 280 { 281 int src_clk_div; 282 int mux; 283 284 debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate); 285 286 /* mmc clock auto divide 2 in internal */ 287 src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq); 288 289 if (src_clk_div > 128) { 290 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); 291 assert(src_clk_div - 1 < 128); 292 mux = EMMC_SEL_24M; 293 } else { 294 mux = EMMC_SEL_GPLL; 295 } 296 297 switch (periph) { 298 case HCLK_EMMC: 299 case SCLK_EMMC: 300 rk_clrsetreg(&cru->cru_clksel_con[12], 301 EMMC_PLL_MASK | EMMC_DIV_MASK, 302 mux << EMMC_PLL_SHIFT | 303 (src_clk_div - 1) << EMMC_DIV_SHIFT); 304 break; 305 case HCLK_SDIO: 306 case SCLK_SDIO: 307 rk_clrsetreg(&cru->cru_clksel_con[12], 308 SDIO_PLL_MASK, 309 SDIO_SEL_24M << SDIO_PLL_SHIFT); 310 rk_clrsetreg(&cru->cru_clksel_con[11], 311 SDIO_DIV_MASK, 312 (src_clk_div - 1) << SDIO_DIV_SHIFT); 313 rk_clrsetreg(&cru->cru_clksel_con[12], 314 SDIO_PLL_MASK, 315 mux << SDIO_PLL_SHIFT); 316 break; 317 case HCLK_SDMMC: 318 case SCLK_SDMMC: 319 rk_clrsetreg(&cru->cru_clksel_con[12], 320 MMC0_PLL_MASK, 321 MMC0_SEL_24M << MMC0_PLL_SHIFT); 322 rk_clrsetreg(&cru->cru_clksel_con[11], 323 MMC0_DIV_MASK, 324 (src_clk_div - 1) << MMC0_DIV_SHIFT); 325 rk_clrsetreg(&cru->cru_clksel_con[12], 326 MMC0_PLL_MASK, 327 mux << MMC0_PLL_SHIFT); 328 break; 329 default: 330 return -EINVAL; 331 } 332 333 return rockchip_mmc_get_clk(cru, clk_general_rate, periph); 334 } 335 336 static ulong rk3036_spi_get_clk(struct rk3036_cru *cru, uint clk_general_rate) 337 { 338 u32 div, con; 339 340 con = readl(&cru->cru_clksel_con[25]); 341 div = (con & SPI_DIV_MASK) >> SPI_DIV_SHIFT; 342 343 return DIV_TO_RATE(clk_general_rate, div); 344 } 345 346 static ulong rk3036_spi_set_clk(struct rk3036_cru *cru, 347 uint clk_general_rate, 348 ulong hz) 349 { 350 int div; 351 352 div = DIV_ROUND_UP(clk_general_rate, hz); 353 assert(div - 1 < 128); 354 rk_clrsetreg(&cru->cru_clksel_con[25], 355 SPI_PLL_SEL_MASK | SPI_DIV_MASK, 356 SPI_PLL_SEL_GPLL << SPI_PLL_SEL_SHIFT | 357 (div - 1) << SPI_DIV_SHIFT); 358 return rk3036_spi_get_clk(cru, clk_general_rate); 359 } 360 361 static ulong rockchip_dclk_lcdc_get_clk(struct rk3036_cru *cru, 362 uint clk_general_rate) 363 { 364 u32 con, div, sel, parent; 365 366 con = readl(&cru->cru_clksel_con[28]); 367 div = (con & LCDC_DCLK_DIV_MASK) >> LCDC_DCLK_DIV_SHIFT; 368 sel = (con & LCDC_DCLK_SEL_MASK) >> LCDC_DCLK_SEL_SHIFT; 369 if (sel == LCDC_DCLK_SEL_GPLL) 370 parent = clk_general_rate; 371 else 372 return -ENOENT; 373 374 return DIV_TO_RATE(parent, div); 375 } 376 377 static ulong rockchip_dclk_lcdc_set_clk(struct rk3036_cru *cru, 378 uint clk_general_rate, uint freq) 379 { 380 int src_clk_div; 381 382 src_clk_div = DIV_ROUND_UP(clk_general_rate, freq); 383 assert(src_clk_div - 1 <= 255); 384 385 rk_clrsetreg(&cru->cru_clksel_con[28], 386 LCDC_DCLK_SEL_MASK | LCDC_DCLK_DIV_MASK, 387 LCDC_DCLK_SEL_GPLL << LCDC_DCLK_SEL_SHIFT | 388 (src_clk_div - 1) << LCDC_DCLK_DIV_SHIFT); 389 390 return rockchip_dclk_lcdc_get_clk(cru, clk_general_rate); 391 } 392 393 static ulong rockchip_aclk_lcdc_get_clk(struct rk3036_cru *cru, 394 uint clk_general_rate) 395 { 396 u32 con, div, sel, parent; 397 398 con = readl(&cru->cru_clksel_con[31]); 399 div = (con & LCDC_ACLK_DIV_MASK) >> LCDC_ACLK_DIV_SHIFT; 400 sel = (con & LCDC_ACLK_SEL_MASK) >> LCDC_ACLK_SEL_SHIFT; 401 if (sel == LCDC_ACLK_SEL_GPLL) 402 parent = clk_general_rate; 403 else 404 return -ENOENT; 405 406 return DIV_TO_RATE(parent, div); 407 } 408 409 static ulong rockchip_aclk_lcdc_set_clk(struct rk3036_cru *cru, 410 uint clk_general_rate, uint freq) 411 { 412 int src_clk_div; 413 414 src_clk_div = DIV_ROUND_UP(clk_general_rate, freq); 415 assert(src_clk_div - 1 <= 31); 416 417 rk_clrsetreg(&cru->cru_clksel_con[31], 418 LCDC_ACLK_SEL_MASK | LCDC_ACLK_DIV_MASK, 419 LCDC_ACLK_SEL_GPLL << LCDC_ACLK_SEL_SHIFT | 420 (src_clk_div - 1) << LCDC_ACLK_DIV_SHIFT); 421 422 return rockchip_aclk_lcdc_get_clk(cru, clk_general_rate); 423 } 424 425 static ulong rk3036_peri_get_clk(struct rk3036_clk_priv *priv, ulong clk_id, 426 uint clk_general_rate) 427 { 428 struct rk3036_cru *cru = priv->cru; 429 u32 div, con, parent; 430 431 switch (clk_id) { 432 case ACLK_PERI: 433 con = readl(&cru->cru_clksel_con[10]); 434 div = (con & PERI_ACLK_DIV_MASK) >> PERI_ACLK_DIV_SHIFT; 435 parent = clk_general_rate; 436 break; 437 case PCLK_PWM: 438 con = readl(&cru->cru_clksel_con[10]); 439 div = (con & PERI_PCLK_DIV_MASK) >> PERI_PCLK_DIV_SHIFT; 440 parent = rk3036_peri_get_clk(priv, ACLK_PERI, clk_general_rate); 441 break; 442 default: 443 printf("do not support this peripheral bus\n"); 444 return -EINVAL; 445 } 446 447 return DIV_TO_RATE(parent, div); 448 } 449 450 static ulong rk3036_peri_set_clk(struct rk3036_clk_priv *priv, 451 ulong clk_id, uint clk_general_rate, 452 uint hz) 453 { 454 struct rk3036_cru *cru = priv->cru; 455 int src_clk_div; 456 457 switch (clk_id) { 458 case ACLK_PERI: 459 src_clk_div = DIV_ROUND_UP(clk_general_rate, hz); 460 assert(src_clk_div - 1 < 32); 461 rk_clrsetreg(&cru->cru_clksel_con[10], 462 PERI_PLL_SEL_MASK | PERI_ACLK_DIV_MASK, 463 PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT | 464 (src_clk_div - 1) << PERI_ACLK_DIV_SHIFT); 465 break; 466 case PCLK_PWM: 467 src_clk_div = DIV_ROUND_UP(rk3036_peri_get_clk(priv, 468 ACLK_PERI, 469 clk_general_rate), 470 hz); 471 assert(src_clk_div - 1 < 8); 472 rk_clrsetreg(&cru->cru_clksel_con[10], 473 PERI_PCLK_DIV_MASK, 474 (src_clk_div - 1) << PERI_PCLK_DIV_SHIFT); 475 break; 476 default: 477 printf("do not support this peripheral bus\n"); 478 return -EINVAL; 479 } 480 481 return rk3036_peri_get_clk(priv, clk_id, clk_general_rate); 482 } 483 484 static ulong rk3036_clk_get_rate(struct clk *clk) 485 { 486 struct rk3036_clk_priv *priv = dev_get_priv(clk->dev); 487 ulong gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); 488 489 switch (clk->id) { 490 case 0 ... 63: 491 return rkclk_pll_get_rate(priv->cru, clk->id); 492 case SCLK_EMMC: 493 case SCLK_SDMMC: 494 case SCLK_SDIO: 495 case HCLK_EMMC: 496 case HCLK_SDMMC: 497 case HCLK_SDIO: 498 return rockchip_mmc_get_clk(priv->cru, gclk_rate, 499 clk->id); 500 case SCLK_LCDC: 501 return rockchip_dclk_lcdc_get_clk(priv->cru, gclk_rate); 502 case ACLK_LCDC: 503 return rockchip_aclk_lcdc_get_clk(priv->cru, gclk_rate); 504 case SCLK_SPI: 505 return rk3036_spi_get_clk(priv->cru, gclk_rate); 506 case PCLK_PWM: 507 return rk3036_peri_get_clk(priv, clk->id, gclk_rate); 508 default: 509 return -ENOENT; 510 } 511 } 512 513 static ulong rk3036_clk_set_rate(struct clk *clk, ulong rate) 514 { 515 struct rk3036_clk_priv *priv = dev_get_priv(clk->dev); 516 ulong new_rate, gclk_rate; 517 518 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); 519 switch (clk->id) { 520 case 0 ... 63: 521 return 0; 522 case HCLK_EMMC: 523 case HCLK_SDMMC: 524 case HCLK_SDIO: 525 case SCLK_EMMC: 526 case SCLK_SDMMC: 527 case SCLK_SDIO: 528 new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate, 529 clk->id, rate); 530 break; 531 case SCLK_LCDC: 532 new_rate = rockchip_dclk_lcdc_set_clk(priv->cru, gclk_rate, 533 rate); 534 break; 535 case ACLK_LCDC: 536 new_rate = rockchip_aclk_lcdc_set_clk(priv->cru, gclk_rate, 537 rate); 538 break; 539 case SCLK_SPI: 540 new_rate = rk3036_spi_set_clk(priv->cru, gclk_rate, 541 rate); 542 break; 543 case PCLK_PWM: 544 new_rate = rk3036_peri_set_clk(priv, clk->id, gclk_rate, 545 rate); 546 break; 547 default: 548 return -ENOENT; 549 } 550 551 return new_rate; 552 } 553 554 static struct clk_ops rk3036_clk_ops = { 555 .get_rate = rk3036_clk_get_rate, 556 .set_rate = rk3036_clk_set_rate, 557 }; 558 559 static int rk3036_clk_ofdata_to_platdata(struct udevice *dev) 560 { 561 struct rk3036_clk_priv *priv = dev_get_priv(dev); 562 563 priv->cru = dev_read_addr_ptr(dev); 564 565 return 0; 566 } 567 568 static int rk3036_clk_probe(struct udevice *dev) 569 { 570 struct rk3036_clk_priv *priv = dev_get_priv(dev); 571 572 priv->sync_kernel = false; 573 if (!priv->armclk_enter_hz) 574 priv->armclk_enter_hz = rkclk_pll_get_rate(priv->cru, 575 CLK_ARM); 576 rkclk_init(priv->cru); 577 if (!priv->armclk_init_hz) 578 priv->armclk_init_hz = rkclk_pll_get_rate(priv->cru, 579 CLK_ARM); 580 581 return 0; 582 } 583 584 static int rk3036_clk_bind(struct udevice *dev) 585 { 586 int ret; 587 struct udevice *sys_child, *sf_child; 588 struct sysreset_reg *priv; 589 struct softreset_reg *sf_priv; 590 591 /* The reset driver does not have a device node, so bind it here */ 592 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", 593 &sys_child); 594 if (ret) { 595 debug("Warning: No sysreset driver: ret=%d\n", ret); 596 } else { 597 priv = malloc(sizeof(struct sysreset_reg)); 598 priv->glb_srst_fst_value = offsetof(struct rk3036_cru, 599 cru_glb_srst_fst_value); 600 priv->glb_srst_snd_value = offsetof(struct rk3036_cru, 601 cru_glb_srst_snd_value); 602 sys_child->priv = priv; 603 } 604 605 ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset", 606 dev_ofnode(dev), &sf_child); 607 if (ret) { 608 debug("Warning: No rockchip reset driver: ret=%d\n", ret); 609 } else { 610 sf_priv = malloc(sizeof(struct softreset_reg)); 611 sf_priv->sf_reset_offset = offsetof(struct rk3036_cru, 612 cru_softrst_con[0]); 613 sf_priv->sf_reset_num = 9; 614 sf_child->priv = sf_priv; 615 } 616 617 return 0; 618 } 619 620 static const struct udevice_id rk3036_clk_ids[] = { 621 { .compatible = "rockchip,rk3036-cru" }, 622 { } 623 }; 624 625 U_BOOT_DRIVER(rockchip_rk3036_cru) = { 626 .name = "clk_rk3036", 627 .id = UCLASS_CLK, 628 .of_match = rk3036_clk_ids, 629 .priv_auto_alloc_size = sizeof(struct rk3036_clk_priv), 630 .ofdata_to_platdata = rk3036_clk_ofdata_to_platdata, 631 .ops = &rk3036_clk_ops, 632 .bind = rk3036_clk_bind, 633 .probe = rk3036_clk_probe, 634 }; 635 636 #ifndef CONFIG_SPL_BUILD 637 /** 638 * soc_clk_dump() - Print clock frequencies 639 * Returns zero on success 640 * 641 * Implementation for the clk dump command. 642 */ 643 int soc_clk_dump(void) 644 { 645 struct udevice *cru_dev; 646 struct rk3036_clk_priv *priv; 647 const struct rk3036_clk_info *clk_dump; 648 struct clk clk; 649 unsigned long clk_count = ARRAY_SIZE(clks_dump); 650 unsigned long rate; 651 int i, ret; 652 653 ret = uclass_get_device_by_driver(UCLASS_CLK, 654 DM_GET_DRIVER(rockchip_rk3036_cru), 655 &cru_dev); 656 if (ret) { 657 printf("%s failed to get cru device\n", __func__); 658 return ret; 659 } 660 661 priv = dev_get_priv(cru_dev); 662 printf("CLK: (%s. arm: enter %lu KHz, init %lu KHz, kernel %lu%s)\n", 663 priv->sync_kernel ? "sync kernel" : "uboot", 664 priv->armclk_enter_hz / 1000, 665 priv->armclk_init_hz / 1000, 666 priv->set_armclk_rate ? priv->armclk_hz / 1000 : 0, 667 priv->set_armclk_rate ? " KHz" : "N/A"); 668 for (i = 0; i < clk_count; i++) { 669 clk_dump = &clks_dump[i]; 670 if (clk_dump->name) { 671 clk.id = clk_dump->id; 672 if (clk_dump->is_cru) 673 ret = clk_request(cru_dev, &clk); 674 if (ret < 0) 675 return ret; 676 677 rate = clk_get_rate(&clk); 678 clk_free(&clk); 679 if (i == 0) { 680 if (rate < 0) 681 printf(" %s %s\n", clk_dump->name, 682 "unknown"); 683 else 684 printf(" %s %lu KHz\n", clk_dump->name, 685 rate / 1000); 686 } else { 687 if (rate < 0) 688 printf(" %s %s\n", clk_dump->name, 689 "unknown"); 690 else 691 printf(" %s %lu KHz\n", clk_dump->name, 692 rate / 1000); 693 } 694 } 695 } 696 697 return 0; 698 } 699 #endif 700 701