1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <bitfield.h> 9 #include <clk-uclass.h> 10 #include <dm.h> 11 #include <errno.h> 12 #include <syscon.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch/cru_px30.h> 15 #include <asm/arch/hardware.h> 16 #include <asm/io.h> 17 #include <dm/lists.h> 18 #include <dt-bindings/clock/px30-cru.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 enum { 23 VCO_MAX_HZ = 3200U * 1000000, 24 VCO_MIN_HZ = 800 * 1000000, 25 OUTPUT_MAX_HZ = 3200U * 1000000, 26 OUTPUT_MIN_HZ = 24 * 1000000, 27 }; 28 29 #define PX30_VOP_PLL_LIMIT 600000000 30 31 #define PX30_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ 32 _postdiv2, _dsmpd, _frac) \ 33 { \ 34 .rate = _rate##U, \ 35 .fbdiv = _fbdiv, \ 36 .postdiv1 = _postdiv1, \ 37 .refdiv = _refdiv, \ 38 .postdiv2 = _postdiv2, \ 39 .dsmpd = _dsmpd, \ 40 .frac = _frac, \ 41 } 42 43 #define PX30_CPUCLK_RATE(_rate, _aclk_div, _pclk_div) \ 44 { \ 45 .rate = _rate##U, \ 46 .aclk_div = _aclk_div, \ 47 .pclk_div = _pclk_div, \ 48 } 49 50 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 51 52 #define PX30_CLK_DUMP(_id, _name, _iscru) \ 53 { \ 54 .id = _id, \ 55 .name = _name, \ 56 .is_cru = _iscru, \ 57 } 58 59 static struct pll_rate_table px30_pll_rates[] = { 60 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 61 PX30_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), 62 PX30_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), 63 PX30_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), 64 PX30_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 65 PX30_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), 66 PX30_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), 67 PX30_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0), 68 }; 69 70 static const struct px30_clk_info clks_dump[] = { 71 PX30_CLK_DUMP(PLL_APLL, "apll", true), 72 PX30_CLK_DUMP(PLL_DPLL, "dpll", true), 73 PX30_CLK_DUMP(PLL_CPLL, "cpll", true), 74 PX30_CLK_DUMP(PLL_NPLL, "npll", true), 75 PX30_CLK_DUMP(PLL_GPLL, "gpll", false), 76 PX30_CLK_DUMP(ACLK_BUS_PRE, "aclk_bus", true), 77 PX30_CLK_DUMP(HCLK_BUS_PRE, "hclk_bus", true), 78 PX30_CLK_DUMP(PCLK_BUS_PRE, "pclk_bus", true), 79 PX30_CLK_DUMP(ACLK_PERI_PRE, "aclk_peri", true), 80 PX30_CLK_DUMP(HCLK_PERI_PRE, "hclk_peri", true), 81 PX30_CLK_DUMP(PCLK_PMU_PRE, "pclk_pmu", false), 82 }; 83 84 static struct cpu_rate_table px30_cpu_rates[] = { 85 PX30_CPUCLK_RATE(1200000000, 1, 5), 86 PX30_CPUCLK_RATE(1008000000, 1, 5), 87 PX30_CPUCLK_RATE(816000000, 1, 3), 88 PX30_CPUCLK_RATE(600000000, 1, 3), 89 PX30_CPUCLK_RATE(408000000, 1, 1), 90 }; 91 92 static u8 pll_mode_shift[PLL_COUNT] = { 93 APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, 94 NPLL_MODE_SHIFT, GPLL_MODE_SHIFT 95 }; 96 static u32 pll_mode_mask[PLL_COUNT] = { 97 APLL_MODE_MASK, DPLL_MODE_MASK, CPLL_MODE_MASK, 98 NPLL_MODE_MASK, GPLL_MODE_MASK 99 }; 100 101 static struct pll_rate_table auto_table; 102 103 static ulong px30_clk_get_pll_rate(struct px30_clk_priv *priv, 104 enum px30_pll_id pll_id); 105 106 static struct pll_rate_table *pll_clk_set_by_auto(u32 drate) 107 { 108 struct pll_rate_table *rate = &auto_table; 109 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; 110 u32 postdiv1, postdiv2 = 1; 111 u32 fref_khz; 112 u32 diff_khz, best_diff_khz; 113 const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16; 114 const u32 max_postdiv1 = 7, max_postdiv2 = 7; 115 u32 vco_khz; 116 u32 rate_khz = drate / KHz; 117 118 if (!drate) { 119 printf("%s: the frequency can't be 0 Hz\n", __func__); 120 return NULL; 121 } 122 123 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, rate_khz); 124 if (postdiv1 > max_postdiv1) { 125 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); 126 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); 127 } 128 129 vco_khz = rate_khz * postdiv1 * postdiv2; 130 131 if (vco_khz < (VCO_MIN_HZ / KHz) || vco_khz > (VCO_MAX_HZ / KHz) || 132 postdiv2 > max_postdiv2) { 133 printf("%s: Cannot find out a supported VCO for Freq (%uHz)\n", 134 __func__, rate_khz); 135 return NULL; 136 } 137 138 rate->postdiv1 = postdiv1; 139 rate->postdiv2 = postdiv2; 140 141 best_diff_khz = vco_khz; 142 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { 143 fref_khz = ref_khz / refdiv; 144 145 fbdiv = vco_khz / fref_khz; 146 if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv)) 147 continue; 148 diff_khz = vco_khz - fbdiv * fref_khz; 149 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) { 150 fbdiv++; 151 diff_khz = fref_khz - diff_khz; 152 } 153 154 if (diff_khz >= best_diff_khz) 155 continue; 156 157 best_diff_khz = diff_khz; 158 rate->refdiv = refdiv; 159 rate->fbdiv = fbdiv; 160 } 161 162 if (best_diff_khz > 4 * (MHz / KHz)) { 163 printf("%s: Failed to match output frequency %u bestis %u Hz\n", 164 __func__, rate_khz, 165 best_diff_khz * KHz); 166 return NULL; 167 } 168 169 return rate; 170 } 171 172 static const struct pll_rate_table *get_pll_settings(unsigned long rate) 173 { 174 unsigned int rate_count = ARRAY_SIZE(px30_pll_rates); 175 int i; 176 177 for (i = 0; i < rate_count; i++) { 178 if (rate == px30_pll_rates[i].rate) 179 return &px30_pll_rates[i]; 180 } 181 182 return pll_clk_set_by_auto(rate); 183 } 184 185 static const struct cpu_rate_table *get_cpu_settings(unsigned long rate) 186 { 187 unsigned int rate_count = ARRAY_SIZE(px30_cpu_rates); 188 int i; 189 190 for (i = 0; i < rate_count; i++) { 191 if (rate == px30_cpu_rates[i].rate) 192 return &px30_cpu_rates[i]; 193 } 194 195 return NULL; 196 } 197 198 /* 199 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63): 200 * Formulas also embedded within the Fractional PLL Verilog model: 201 * If DSMPD = 1 (DSM is disabled, "integer mode") 202 * FOUTVCO = FREF / REFDIV * FBDIV 203 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 204 * Where: 205 * FOUTVCO = Fractional PLL non-divided output frequency 206 * FOUTPOSTDIV = Fractional PLL divided output frequency 207 * (output of second post divider) 208 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input) 209 * REFDIV = Fractional PLL input reference clock divider 210 * FBDIV = Integer value programmed into feedback divide 211 * 212 */ 213 static int rkclk_set_pll(struct px30_pll *pll, unsigned int *mode, 214 enum px30_pll_id pll_id, 215 unsigned long drate) 216 { 217 const struct pll_rate_table *rate; 218 uint vco_hz, output_hz; 219 220 rate = get_pll_settings(drate); 221 if (!rate) { 222 printf("%s unsupport rate\n", __func__); 223 return -EINVAL; 224 } 225 226 /* All PLLs have same VCO and output frequency range restrictions. */ 227 vco_hz = OSC_HZ / 1000 * rate->fbdiv / rate->refdiv * 1000; 228 output_hz = vco_hz / rate->postdiv1 / rate->postdiv2; 229 230 debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n", 231 pll, rate->fbdiv, rate->refdiv, rate->postdiv1, 232 rate->postdiv2, vco_hz, output_hz); 233 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && 234 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ); 235 236 /* 237 * When power on or changing PLL setting, 238 * we must force PLL into slow mode to ensure output stable clock. 239 */ 240 rk_clrsetreg(mode, pll_mode_mask[pll_id], 241 PLLMUX_FROM_XIN24M << pll_mode_shift[pll_id]); 242 243 /* use integer mode */ 244 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); 245 /* Power down */ 246 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); 247 248 rk_clrsetreg(&pll->con0, 249 PLL_POSTDIV1_MASK | PLL_FBDIV_MASK, 250 (rate->postdiv1 << PLL_POSTDIV1_SHIFT) | rate->fbdiv); 251 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, 252 (rate->postdiv2 << PLL_POSTDIV2_SHIFT | 253 rate->refdiv << PLL_REFDIV_SHIFT)); 254 255 /* Power Up */ 256 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); 257 258 /* waiting for pll lock */ 259 while (!(readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))) 260 udelay(1); 261 262 rk_clrsetreg(mode, pll_mode_mask[pll_id], 263 PLLMUX_FROM_PLL << pll_mode_shift[pll_id]); 264 265 return 0; 266 } 267 268 static uint32_t rkclk_pll_get_rate(struct px30_pll *pll, unsigned int *mode, 269 enum px30_pll_id pll_id) 270 { 271 u32 refdiv, fbdiv, postdiv1, postdiv2; 272 u32 con, shift, mask; 273 274 con = readl(mode); 275 shift = pll_mode_shift[pll_id]; 276 mask = pll_mode_mask[pll_id]; 277 278 switch ((con & mask) >> shift) { 279 case PLLMUX_FROM_XIN24M: 280 return OSC_HZ; 281 case PLLMUX_FROM_PLL: 282 /* normal mode */ 283 con = readl(&pll->con0); 284 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; 285 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; 286 con = readl(&pll->con1); 287 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; 288 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; 289 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; 290 case PLLMUX_FROM_RTC32K: 291 default: 292 return 32768; 293 } 294 } 295 296 static ulong px30_i2c_get_clk(struct px30_clk_priv *priv, ulong clk_id) 297 { 298 struct px30_cru *cru = priv->cru; 299 u32 div, con; 300 301 switch (clk_id) { 302 case SCLK_I2C0: 303 con = readl(&cru->clksel_con[49]); 304 div = con >> CLK_I2C0_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; 305 break; 306 case SCLK_I2C1: 307 con = readl(&cru->clksel_con[49]); 308 div = con >> CLK_I2C1_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; 309 break; 310 case SCLK_I2C2: 311 con = readl(&cru->clksel_con[50]); 312 div = con >> CLK_I2C2_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; 313 break; 314 case SCLK_I2C3: 315 con = readl(&cru->clksel_con[50]); 316 div = con >> CLK_I2C3_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; 317 break; 318 default: 319 printf("do not support this i2c bus\n"); 320 return -EINVAL; 321 } 322 323 return DIV_TO_RATE(priv->gpll_hz, div); 324 } 325 326 static ulong px30_i2c_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) 327 { 328 struct px30_cru *cru = priv->cru; 329 int src_clk_div; 330 331 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 332 assert(src_clk_div - 1 <= 127); 333 334 switch (clk_id) { 335 case SCLK_I2C0: 336 rk_clrsetreg(&cru->clksel_con[49], 337 CLK_I2C_DIV_CON_MASK << CLK_I2C0_DIV_CON_SHIFT | 338 CLK_I2C_PLL_SEL_MASK << CLK_I2C0_PLL_SEL_SHIFT, 339 (src_clk_div - 1) << CLK_I2C0_DIV_CON_SHIFT | 340 CLK_I2C_PLL_SEL_GPLL << CLK_I2C0_PLL_SEL_SHIFT); 341 break; 342 case SCLK_I2C1: 343 rk_clrsetreg(&cru->clksel_con[49], 344 CLK_I2C_DIV_CON_MASK << CLK_I2C1_DIV_CON_SHIFT | 345 CLK_I2C_PLL_SEL_MASK << CLK_I2C1_PLL_SEL_SHIFT, 346 (src_clk_div - 1) << CLK_I2C1_DIV_CON_SHIFT | 347 CLK_I2C_PLL_SEL_GPLL << CLK_I2C1_PLL_SEL_SHIFT); 348 break; 349 case SCLK_I2C2: 350 rk_clrsetreg(&cru->clksel_con[50], 351 CLK_I2C_DIV_CON_MASK << CLK_I2C2_DIV_CON_SHIFT | 352 CLK_I2C_PLL_SEL_MASK << CLK_I2C2_PLL_SEL_SHIFT, 353 (src_clk_div - 1) << CLK_I2C2_DIV_CON_SHIFT | 354 CLK_I2C_PLL_SEL_GPLL << CLK_I2C2_PLL_SEL_SHIFT); 355 break; 356 case SCLK_I2C3: 357 rk_clrsetreg(&cru->clksel_con[50], 358 CLK_I2C_DIV_CON_MASK << CLK_I2C3_DIV_CON_SHIFT | 359 CLK_I2C_PLL_SEL_MASK << CLK_I2C3_PLL_SEL_SHIFT, 360 (src_clk_div - 1) << CLK_I2C3_DIV_CON_SHIFT | 361 CLK_I2C_PLL_SEL_GPLL << CLK_I2C3_PLL_SEL_SHIFT); 362 break; 363 default: 364 printf("do not support this i2c bus\n"); 365 return -EINVAL; 366 } 367 368 return px30_i2c_get_clk(priv, clk_id); 369 } 370 371 /* 372 * calculate best rational approximation for a given fraction 373 * taking into account restricted register size, e.g. to find 374 * appropriate values for a pll with 5 bit denominator and 375 * 8 bit numerator register fields, trying to set up with a 376 * frequency ratio of 3.1415, one would say: 377 * 378 * rational_best_approximation(31415, 10000, 379 * (1 << 8) - 1, (1 << 5) - 1, &n, &d); 380 * 381 * you may look at given_numerator as a fixed point number, 382 * with the fractional part size described in given_denominator. 383 * 384 * for theoretical background, see: 385 * http://en.wikipedia.org/wiki/Continued_fraction 386 */ 387 static void rational_best_approximation( 388 unsigned long given_numerator, unsigned long given_denominator, 389 unsigned long max_numerator, unsigned long max_denominator, 390 unsigned long *best_numerator, unsigned long *best_denominator) 391 { 392 unsigned long n, d, n0, d0, n1, d1; 393 394 n = given_numerator; 395 d = given_denominator; 396 n0 = 0; 397 d1 = 0; 398 n1 = 1; 399 d0 = 1; 400 for (;;) { 401 unsigned long t, a; 402 403 if (n1 > max_numerator || d1 > max_denominator) { 404 n1 = n0; 405 d1 = d0; 406 break; 407 } 408 if (d == 0) 409 break; 410 t = d; 411 a = n / d; 412 d = n % d; 413 n = t; 414 t = n0 + a * n1; 415 n0 = n1; 416 n1 = t; 417 t = d0 + a * d1; 418 d0 = d1; 419 d1 = t; 420 } 421 *best_numerator = n1; 422 *best_denominator = d1; 423 } 424 425 static ulong px30_i2s_get_clk(struct px30_clk_priv *priv, ulong clk_id) 426 { 427 u32 con, fracdiv, gate; 428 u32 clk_src = GPLL_HZ / 2; 429 unsigned long m, n; 430 struct px30_cru *cru = priv->cru; 431 432 switch (clk_id) { 433 case SCLK_I2S1: 434 con = readl(&cru->clksel_con[30]); 435 fracdiv = readl(&cru->clksel_con[31]); 436 gate = readl(&cru->clkgate_con[10]); 437 m = fracdiv & CLK_I2S1_FRAC_NUMERATOR_MASK; 438 m >>= CLK_I2S1_FRAC_NUMERATOR_SHIFT; 439 n = fracdiv & CLK_I2S1_FRAC_DENOMINATOR_MASK; 440 n >>= CLK_I2S1_FRAC_DENOMINATOR_SHIFT; 441 debug("con30: 0x%x, gate: 0x%x, frac: 0x%x\n", 442 con, gate, fracdiv); 443 break; 444 default: 445 printf("do not support this i2s bus\n"); 446 return -EINVAL; 447 } 448 449 return clk_src * n / m; 450 } 451 452 static ulong px30_i2s_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) 453 { 454 u32 clk_src; 455 unsigned long m, n, val; 456 struct px30_cru *cru = priv->cru; 457 458 clk_src = GPLL_HZ / 2; 459 rational_best_approximation(hz, clk_src, 460 GENMASK(16 - 1, 0), 461 GENMASK(16 - 1, 0), 462 &m, &n); 463 switch (clk_id) { 464 case SCLK_I2S1: 465 rk_clrsetreg(&cru->clksel_con[30], 466 CLK_I2S1_PLL_SEL_MASK, CLK_I2S1_PLL_SEL_GPLL); 467 rk_clrsetreg(&cru->clksel_con[30], 468 CLK_I2S1_DIV_CON_MASK, 0x1); 469 rk_clrsetreg(&cru->clksel_con[30], 470 CLK_I2S1_SEL_MASK, CLK_I2S1_SEL_FRAC); 471 val = m << CLK_I2S1_FRAC_NUMERATOR_SHIFT | n; 472 writel(val, &cru->clksel_con[31]); 473 rk_clrsetreg(&cru->clkgate_con[10], 474 CLK_I2S1_OUT_MCLK_PAD_MASK, 475 CLK_I2S1_OUT_MCLK_PAD_ENABLE); 476 break; 477 default: 478 printf("do not support this i2s bus\n"); 479 return -EINVAL; 480 } 481 482 return px30_i2s_get_clk(priv, clk_id); 483 } 484 485 static ulong px30_nandc_get_clk(struct px30_clk_priv *priv) 486 { 487 struct px30_cru *cru = priv->cru; 488 u32 div, con; 489 490 con = readl(&cru->clksel_con[15]); 491 div = (con & NANDC_DIV_MASK) >> NANDC_DIV_SHIFT; 492 493 return DIV_TO_RATE(priv->gpll_hz, div); 494 } 495 496 static ulong px30_nandc_set_clk(struct px30_clk_priv *priv, 497 ulong set_rate) 498 { 499 struct px30_cru *cru = priv->cru; 500 int src_clk_div; 501 502 /* Select nandc source from GPLL by default */ 503 /* nandc clock defaulg div 2 internal, need provide double in cru */ 504 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, set_rate); 505 assert(src_clk_div - 1 <= 31); 506 507 rk_clrsetreg(&cru->clksel_con[15], 508 NANDC_CLK_SEL_MASK | NANDC_PLL_MASK | 509 NANDC_DIV_MASK, 510 NANDC_CLK_SEL_NANDC << NANDC_CLK_SEL_SHIFT | 511 NANDC_SEL_GPLL << NANDC_PLL_SHIFT | 512 (src_clk_div - 1) << NANDC_DIV_SHIFT); 513 514 return px30_nandc_get_clk(priv); 515 } 516 517 static ulong px30_mmc_get_clk(struct px30_clk_priv *priv, uint clk_id) 518 { 519 struct px30_cru *cru = priv->cru; 520 u32 div, con, con_id; 521 522 switch (clk_id) { 523 case HCLK_SDMMC: 524 case SCLK_SDMMC: 525 con_id = 16; 526 break; 527 case HCLK_EMMC: 528 case SCLK_EMMC: 529 case SCLK_EMMC_SAMPLE: 530 con_id = 20; 531 break; 532 default: 533 return -EINVAL; 534 } 535 536 con = readl(&cru->clksel_con[con_id]); 537 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; 538 539 if ((con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT 540 == EMMC_SEL_24M) 541 return DIV_TO_RATE(OSC_HZ, div) / 2; 542 else 543 return DIV_TO_RATE(priv->gpll_hz, div) / 2; 544 545 } 546 547 static ulong px30_mmc_set_clk(struct px30_clk_priv *priv, 548 ulong clk_id, ulong set_rate) 549 { 550 struct px30_cru *cru = priv->cru; 551 int src_clk_div; 552 u32 con_id; 553 554 switch (clk_id) { 555 case HCLK_SDMMC: 556 case SCLK_SDMMC: 557 con_id = 16; 558 break; 559 case HCLK_EMMC: 560 case SCLK_EMMC: 561 con_id = 20; 562 break; 563 default: 564 return -EINVAL; 565 } 566 567 /* Select clk_sdmmc/emmc source from GPLL by default */ 568 /* mmc clock defaulg div 2 internal, need provide double in cru */ 569 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, set_rate); 570 571 if (src_clk_div > 127) { 572 /* use 24MHz source for 400KHz clock */ 573 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); 574 rk_clrsetreg(&cru->clksel_con[con_id], 575 EMMC_PLL_MASK | EMMC_DIV_MASK, 576 EMMC_SEL_24M << EMMC_PLL_SHIFT | 577 (src_clk_div - 1) << EMMC_DIV_SHIFT); 578 } else { 579 rk_clrsetreg(&cru->clksel_con[con_id], 580 EMMC_PLL_MASK | EMMC_DIV_MASK, 581 EMMC_SEL_GPLL << EMMC_PLL_SHIFT | 582 (src_clk_div - 1) << EMMC_DIV_SHIFT); 583 } 584 rk_clrsetreg(&cru->clksel_con[con_id +1], EMMC_CLK_SEL_MASK, 585 EMMC_CLK_SEL_EMMC); 586 587 return px30_mmc_get_clk(priv, clk_id); 588 } 589 590 static ulong px30_pwm_get_clk(struct px30_clk_priv *priv, ulong clk_id) 591 { 592 struct px30_cru *cru = priv->cru; 593 u32 div, con; 594 595 switch (clk_id) { 596 case SCLK_PWM0: 597 con = readl(&cru->clksel_con[52]); 598 div = con >> CLK_PWM0_DIV_CON_SHIFT & CLK_PWM_DIV_CON_MASK; 599 break; 600 case SCLK_PWM1: 601 con = readl(&cru->clksel_con[52]); 602 div = con >> CLK_PWM1_DIV_CON_SHIFT & CLK_PWM_DIV_CON_MASK; 603 break; 604 default: 605 printf("do not support this pwm bus\n"); 606 return -EINVAL; 607 } 608 609 return DIV_TO_RATE(priv->gpll_hz, div); 610 } 611 612 static ulong px30_pwm_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) 613 { 614 struct px30_cru *cru = priv->cru; 615 int src_clk_div; 616 617 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 618 assert(src_clk_div - 1 <= 127); 619 620 switch (clk_id) { 621 case SCLK_PWM0: 622 rk_clrsetreg(&cru->clksel_con[52], 623 CLK_PWM_DIV_CON_MASK << CLK_PWM0_DIV_CON_SHIFT | 624 CLK_PWM_PLL_SEL_MASK << CLK_PWM0_PLL_SEL_SHIFT, 625 (src_clk_div - 1) << CLK_PWM0_DIV_CON_SHIFT | 626 CLK_PWM_PLL_SEL_GPLL << CLK_PWM0_PLL_SEL_SHIFT); 627 break; 628 case SCLK_PWM1: 629 rk_clrsetreg(&cru->clksel_con[52], 630 CLK_PWM_DIV_CON_MASK << CLK_PWM1_DIV_CON_SHIFT | 631 CLK_PWM_PLL_SEL_MASK << CLK_PWM1_PLL_SEL_SHIFT, 632 (src_clk_div - 1) << CLK_PWM1_DIV_CON_SHIFT | 633 CLK_PWM_PLL_SEL_GPLL << CLK_PWM1_PLL_SEL_SHIFT); 634 break; 635 default: 636 printf("do not support this pwm bus\n"); 637 return -EINVAL; 638 } 639 640 return px30_pwm_get_clk(priv, clk_id); 641 } 642 643 static ulong px30_saradc_get_clk(struct px30_clk_priv *priv) 644 { 645 struct px30_cru *cru = priv->cru; 646 u32 div, con; 647 648 con = readl(&cru->clksel_con[55]); 649 div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK; 650 651 return DIV_TO_RATE(OSC_HZ, div); 652 } 653 654 static ulong px30_saradc_set_clk(struct px30_clk_priv *priv, uint hz) 655 { 656 struct px30_cru *cru = priv->cru; 657 int src_clk_div; 658 659 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); 660 assert(src_clk_div - 1 <= 2047); 661 662 rk_clrsetreg(&cru->clksel_con[55], 663 CLK_SARADC_DIV_CON_MASK, 664 (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT); 665 666 return px30_saradc_get_clk(priv); 667 } 668 669 static ulong px30_tsadc_get_clk(struct px30_clk_priv *priv) 670 { 671 struct px30_cru *cru = priv->cru; 672 u32 div, con; 673 674 con = readl(&cru->clksel_con[54]); 675 div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK; 676 677 return DIV_TO_RATE(OSC_HZ, div); 678 } 679 680 static ulong px30_tsadc_set_clk(struct px30_clk_priv *priv, uint hz) 681 { 682 struct px30_cru *cru = priv->cru; 683 int src_clk_div; 684 685 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); 686 assert(src_clk_div - 1 <= 2047); 687 688 rk_clrsetreg(&cru->clksel_con[54], 689 CLK_SARADC_DIV_CON_MASK, 690 (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT); 691 692 return px30_tsadc_get_clk(priv); 693 } 694 695 static ulong px30_spi_get_clk(struct px30_clk_priv *priv, ulong clk_id) 696 { 697 struct px30_cru *cru = priv->cru; 698 u32 div, con; 699 700 switch (clk_id) { 701 case SCLK_SPI0: 702 con = readl(&cru->clksel_con[53]); 703 div = con >> CLK_SPI0_DIV_CON_SHIFT & CLK_SPI_DIV_CON_MASK; 704 break; 705 case SCLK_SPI1: 706 con = readl(&cru->clksel_con[53]); 707 div = con >> CLK_SPI1_DIV_CON_SHIFT & CLK_SPI_DIV_CON_MASK; 708 break; 709 default: 710 printf("do not support this pwm bus\n"); 711 return -EINVAL; 712 } 713 714 return DIV_TO_RATE(priv->gpll_hz, div); 715 } 716 717 static ulong px30_spi_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) 718 { 719 struct px30_cru *cru = priv->cru; 720 int src_clk_div; 721 722 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 723 assert(src_clk_div - 1 <= 127); 724 725 switch (clk_id) { 726 case SCLK_SPI0: 727 rk_clrsetreg(&cru->clksel_con[53], 728 CLK_SPI_DIV_CON_MASK << CLK_SPI0_DIV_CON_SHIFT | 729 CLK_SPI_PLL_SEL_MASK << CLK_SPI0_PLL_SEL_SHIFT, 730 (src_clk_div - 1) << CLK_SPI0_DIV_CON_SHIFT | 731 CLK_SPI_PLL_SEL_GPLL << CLK_SPI0_PLL_SEL_SHIFT); 732 break; 733 case SCLK_SPI1: 734 rk_clrsetreg(&cru->clksel_con[53], 735 CLK_SPI_DIV_CON_MASK << CLK_SPI1_DIV_CON_SHIFT | 736 CLK_SPI_PLL_SEL_MASK << CLK_SPI1_PLL_SEL_SHIFT, 737 (src_clk_div - 1) << CLK_SPI1_DIV_CON_SHIFT | 738 CLK_SPI_PLL_SEL_GPLL << CLK_SPI1_PLL_SEL_SHIFT); 739 break; 740 default: 741 printf("do not support this pwm bus\n"); 742 return -EINVAL; 743 } 744 745 return px30_spi_get_clk(priv, clk_id); 746 } 747 748 static ulong px30_vop_get_clk(struct px30_clk_priv *priv, ulong clk_id) 749 { 750 struct px30_cru *cru = priv->cru; 751 u32 div, con, parent; 752 753 switch (clk_id) { 754 case ACLK_VOPB: 755 case ACLK_VOPL: 756 con = readl(&cru->clksel_con[3]); 757 div = con & ACLK_VO_DIV_MASK; 758 parent = priv->gpll_hz; 759 break; 760 case DCLK_VOPB: 761 con = readl(&cru->clksel_con[5]); 762 div = con & DCLK_VOPB_DIV_MASK; 763 parent = rkclk_pll_get_rate(&cru->pll[CPLL], &cru->mode, CPLL); 764 break; 765 case DCLK_VOPL: 766 con = readl(&cru->clksel_con[8]); 767 div = con & DCLK_VOPL_DIV_MASK; 768 parent = rkclk_pll_get_rate(&cru->pll[NPLL], &cru->mode, NPLL); 769 break; 770 default: 771 return -ENOENT; 772 } 773 774 return DIV_TO_RATE(parent, div); 775 } 776 777 static ulong px30_vop_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) 778 { 779 struct px30_cru *cru = priv->cru; 780 ulong npll_hz; 781 int src_clk_div; 782 783 switch (clk_id) { 784 case ACLK_VOPB: 785 case ACLK_VOPL: 786 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 787 assert(src_clk_div - 1 <= 31); 788 rk_clrsetreg(&cru->clksel_con[3], 789 ACLK_VO_PLL_MASK | ACLK_VO_DIV_MASK, 790 ACLK_VO_SEL_GPLL << ACLK_VO_PLL_SHIFT | 791 (src_clk_div - 1) << ACLK_VO_DIV_SHIFT); 792 break; 793 case DCLK_VOPB: 794 if (hz < PX30_VOP_PLL_LIMIT) 795 src_clk_div = DIV_ROUND_UP(PX30_VOP_PLL_LIMIT, hz); 796 else 797 src_clk_div = 1; 798 assert(src_clk_div - 1 <= 255); 799 rkclk_set_pll(&cru->pll[CPLL], &cru->mode, CPLL, hz * src_clk_div); 800 rk_clrsetreg(&cru->clksel_con[5], 801 DCLK_VOPB_SEL_MASK | DCLK_VOPB_PLL_SEL_MASK | 802 DCLK_VOPB_DIV_MASK, 803 DCLK_VOPB_SEL_DIVOUT << DCLK_VOPB_SEL_SHIFT | 804 DCLK_VOPB_PLL_SEL_CPLL << DCLK_VOPB_PLL_SEL_SHIFT | 805 (src_clk_div - 1) << DCLK_VOPB_DIV_SHIFT); 806 break; 807 case DCLK_VOPL: 808 npll_hz = px30_clk_get_pll_rate(priv, NPLL); 809 if (npll_hz >= PX30_VOP_PLL_LIMIT && npll_hz >= hz && npll_hz % hz == 0) { 810 src_clk_div = npll_hz / hz; 811 assert(src_clk_div - 1 <= 255); 812 } else { 813 if (hz < PX30_VOP_PLL_LIMIT) 814 src_clk_div = DIV_ROUND_UP(PX30_VOP_PLL_LIMIT, hz); 815 else 816 src_clk_div = 1; 817 assert(src_clk_div - 1 <= 255); 818 rkclk_set_pll(&cru->pll[NPLL], &cru->mode, NPLL, hz * src_clk_div); 819 } 820 rk_clrsetreg(&cru->clksel_con[8], 821 DCLK_VOPL_SEL_MASK | DCLK_VOPL_PLL_SEL_MASK | 822 DCLK_VOPL_DIV_MASK, 823 DCLK_VOPL_SEL_DIVOUT << DCLK_VOPL_SEL_SHIFT | 824 DCLK_VOPL_PLL_SEL_NPLL << DCLK_VOPL_PLL_SEL_SHIFT | 825 (src_clk_div - 1) << DCLK_VOPL_DIV_SHIFT); 826 break; 827 default: 828 printf("do not support this vop freq\n"); 829 return -EINVAL; 830 } 831 832 return px30_vop_get_clk(priv, clk_id); 833 } 834 835 static ulong px30_bus_get_clk(struct px30_clk_priv *priv, ulong clk_id) 836 { 837 struct px30_cru *cru = priv->cru; 838 u32 div, con, parent; 839 840 switch (clk_id) { 841 case ACLK_BUS_PRE: 842 con = readl(&cru->clksel_con[23]); 843 div = (con & BUS_ACLK_DIV_MASK) >> BUS_ACLK_DIV_SHIFT; 844 parent = priv->gpll_hz; 845 break; 846 case HCLK_BUS_PRE: 847 con = readl(&cru->clksel_con[24]); 848 div = (con & BUS_HCLK_DIV_MASK) >> BUS_HCLK_DIV_SHIFT; 849 parent = priv->gpll_hz; 850 break; 851 case PCLK_BUS_PRE: 852 parent = px30_bus_get_clk(priv, ACLK_BUS_PRE); 853 con = readl(&cru->clksel_con[24]); 854 div = (con & BUS_PCLK_DIV_MASK) >> BUS_PCLK_DIV_SHIFT; 855 break; 856 default: 857 return -ENOENT; 858 } 859 860 return DIV_TO_RATE(parent, div); 861 } 862 863 static ulong px30_bus_set_clk(struct px30_clk_priv *priv, ulong clk_id, 864 ulong hz) 865 { 866 struct px30_cru *cru = priv->cru; 867 int src_clk_div; 868 869 /* 870 * select gpll as pd_bus bus clock source and 871 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 872 */ 873 switch (clk_id) { 874 case ACLK_BUS_PRE: 875 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 876 assert(src_clk_div - 1 <= 31); 877 rk_clrsetreg(&cru->clksel_con[23], 878 BUS_PLL_SEL_MASK | BUS_ACLK_DIV_MASK, 879 BUS_PLL_SEL_GPLL << BUS_PLL_SEL_SHIFT | 880 (src_clk_div - 1) << BUS_ACLK_DIV_SHIFT); 881 break; 882 case HCLK_BUS_PRE: 883 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 884 assert(src_clk_div - 1 <= 31); 885 rk_clrsetreg(&cru->clksel_con[24], 886 BUS_PLL_SEL_MASK | BUS_HCLK_DIV_MASK, 887 BUS_PLL_SEL_GPLL << BUS_PLL_SEL_SHIFT | 888 (src_clk_div - 1) << BUS_HCLK_DIV_SHIFT); 889 break; 890 case PCLK_BUS_PRE: 891 src_clk_div = 892 DIV_ROUND_UP(px30_bus_get_clk(priv, ACLK_BUS_PRE), hz); 893 assert(src_clk_div - 1 <= 3); 894 rk_clrsetreg(&cru->clksel_con[24], 895 BUS_PCLK_DIV_MASK, 896 (src_clk_div - 1) << BUS_PCLK_DIV_SHIFT); 897 break; 898 default: 899 printf("do not support this bus freq\n"); 900 return -EINVAL; 901 } 902 903 return px30_bus_get_clk(priv, clk_id); 904 } 905 906 static ulong px30_peri_get_clk(struct px30_clk_priv *priv, ulong clk_id) 907 { 908 struct px30_cru *cru = priv->cru; 909 u32 div, con, parent; 910 911 switch (clk_id) { 912 case ACLK_PERI_PRE: 913 con = readl(&cru->clksel_con[14]); 914 div = (con & PERI_ACLK_DIV_MASK) >> PERI_ACLK_DIV_SHIFT; 915 parent = priv->gpll_hz; 916 break; 917 case HCLK_PERI_PRE: 918 con = readl(&cru->clksel_con[14]); 919 div = (con & PERI_HCLK_DIV_MASK) >> PERI_HCLK_DIV_SHIFT; 920 parent = priv->gpll_hz; 921 break; 922 default: 923 return -ENOENT; 924 } 925 926 return DIV_TO_RATE(parent, div); 927 } 928 929 static ulong px30_peri_set_clk(struct px30_clk_priv *priv, ulong clk_id, 930 ulong hz) 931 { 932 struct px30_cru *cru = priv->cru; 933 int src_clk_div; 934 935 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 936 assert(src_clk_div - 1 <= 31); 937 938 /* 939 * select gpll as pd_peri bus clock source and 940 * set up dependent divisors for HCLK and ACLK clocks. 941 */ 942 switch (clk_id) { 943 case ACLK_PERI_PRE: 944 rk_clrsetreg(&cru->clksel_con[14], 945 PERI_PLL_SEL_MASK | PERI_ACLK_DIV_MASK, 946 PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT | 947 (src_clk_div - 1) << PERI_ACLK_DIV_SHIFT); 948 break; 949 case HCLK_PERI_PRE: 950 rk_clrsetreg(&cru->clksel_con[14], 951 PERI_PLL_SEL_MASK | PERI_HCLK_DIV_MASK, 952 PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT | 953 (src_clk_div - 1) << PERI_HCLK_DIV_SHIFT); 954 break; 955 default: 956 printf("do not support this peri freq\n"); 957 return -EINVAL; 958 } 959 960 return px30_peri_get_clk(priv, clk_id); 961 } 962 963 #ifndef CONFIG_SPL_BUILD 964 static ulong px30_crypto_get_clk(struct px30_clk_priv *priv, ulong clk_id) 965 { 966 struct px30_cru *cru = priv->cru; 967 u32 div, con, parent; 968 969 switch (clk_id) { 970 case SCLK_CRYPTO: 971 con = readl(&cru->clksel_con[25]); 972 div = (con & CRYPTO_DIV_MASK) >> CRYPTO_DIV_SHIFT; 973 parent = priv->gpll_hz; 974 break; 975 case SCLK_CRYPTO_APK: 976 con = readl(&cru->clksel_con[25]); 977 div = (con & CRYPTO_APK_DIV_MASK) >> CRYPTO_APK_DIV_SHIFT; 978 parent = priv->gpll_hz; 979 break; 980 default: 981 return -ENOENT; 982 } 983 984 return DIV_TO_RATE(parent, div); 985 } 986 987 static ulong px30_crypto_set_clk(struct px30_clk_priv *priv, ulong clk_id, 988 ulong hz) 989 { 990 struct px30_cru *cru = priv->cru; 991 int src_clk_div; 992 993 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 994 assert(src_clk_div - 1 <= 31); 995 996 /* 997 * select gpll as crypto clock source and 998 * set up dependent divisors for crypto clocks. 999 */ 1000 switch (clk_id) { 1001 case SCLK_CRYPTO: 1002 rk_clrsetreg(&cru->clksel_con[25], 1003 CRYPTO_PLL_SEL_MASK | CRYPTO_DIV_MASK, 1004 CRYPTO_PLL_SEL_GPLL << CRYPTO_PLL_SEL_SHIFT | 1005 (src_clk_div - 1) << CRYPTO_DIV_SHIFT); 1006 break; 1007 case SCLK_CRYPTO_APK: 1008 rk_clrsetreg(&cru->clksel_con[25], 1009 CRYPTO_APK_PLL_SEL_MASK | CRYPTO_APK_DIV_MASK, 1010 CRYPTO_PLL_SEL_GPLL << CRYPTO_APK_SEL_SHIFT | 1011 (src_clk_div - 1) << CRYPTO_APK_DIV_SHIFT); 1012 break; 1013 default: 1014 printf("do not support this peri freq\n"); 1015 return -EINVAL; 1016 } 1017 1018 return px30_crypto_get_clk(priv, clk_id); 1019 } 1020 #endif 1021 1022 static int px30_clk_get_gpll_rate(ulong *rate) 1023 { 1024 struct udevice *pmucru_dev; 1025 struct px30_pmuclk_priv *priv; 1026 int ret; 1027 1028 ret = uclass_get_device_by_driver(UCLASS_CLK, 1029 DM_GET_DRIVER(rockchip_px30_pmucru), 1030 &pmucru_dev); 1031 if (ret) { 1032 printf("%s: could not find pmucru device\n", __func__); 1033 return ret; 1034 } 1035 priv = dev_get_priv(pmucru_dev); 1036 *rate = priv->gpll_hz; 1037 1038 return 0; 1039 } 1040 1041 static ulong px30_clk_get_pll_rate(struct px30_clk_priv *priv, 1042 enum px30_pll_id pll_id) 1043 { 1044 struct px30_cru *cru = priv->cru; 1045 1046 return rkclk_pll_get_rate(&cru->pll[pll_id], &cru->mode, pll_id); 1047 } 1048 1049 static ulong px30_clk_set_pll_rate(struct px30_clk_priv *priv, 1050 enum px30_pll_id pll_id, ulong hz) 1051 { 1052 struct px30_cru *cru = priv->cru; 1053 1054 if (rkclk_set_pll(&cru->pll[pll_id], &cru->mode, pll_id, hz)) 1055 return -EINVAL; 1056 return rkclk_pll_get_rate(&cru->pll[pll_id], &cru->mode, pll_id); 1057 } 1058 1059 static ulong px30_armclk_set_clk(struct px30_clk_priv *priv, ulong hz) 1060 { 1061 struct px30_cru *cru = priv->cru; 1062 const struct cpu_rate_table *rate; 1063 ulong old_rate; 1064 1065 rate = get_cpu_settings(hz); 1066 if (!rate) { 1067 printf("%s unsupport rate\n", __func__); 1068 return -EINVAL; 1069 } 1070 1071 /* 1072 * select apll as cpu/core clock pll source and 1073 * set up dependent divisors for PERI and ACLK clocks. 1074 * core hz : apll = 1:1 1075 */ 1076 old_rate = px30_clk_get_pll_rate(priv, APLL); 1077 if (old_rate > hz) { 1078 if (rkclk_set_pll(&cru->pll[APLL], &cru->mode, APLL, hz)) 1079 return -EINVAL; 1080 rk_clrsetreg(&cru->clksel_con[0], 1081 CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK | 1082 CORE_ACLK_DIV_MASK | CORE_DBG_DIV_MASK, 1083 rate->aclk_div << CORE_ACLK_DIV_SHIFT | 1084 rate->pclk_div << CORE_DBG_DIV_SHIFT | 1085 CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT | 1086 0 << CORE_DIV_CON_SHIFT); 1087 } else if (old_rate < hz) { 1088 rk_clrsetreg(&cru->clksel_con[0], 1089 CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK | 1090 CORE_ACLK_DIV_MASK | CORE_DBG_DIV_MASK, 1091 rate->aclk_div << CORE_ACLK_DIV_SHIFT | 1092 rate->pclk_div << CORE_DBG_DIV_SHIFT | 1093 CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT | 1094 0 << CORE_DIV_CON_SHIFT); 1095 if (rkclk_set_pll(&cru->pll[APLL], &cru->mode, APLL, hz)) 1096 return -EINVAL; 1097 } 1098 1099 return px30_clk_get_pll_rate(priv, APLL); 1100 } 1101 1102 static ulong px30_clk_get_rate(struct clk *clk) 1103 { 1104 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 1105 ulong rate = 0; 1106 1107 if (!priv->gpll_hz && clk->id > ARMCLK) { 1108 printf("%s gpll=%lu\n", __func__, priv->gpll_hz); 1109 return -ENOENT; 1110 } 1111 1112 debug("%s %ld\n", __func__, clk->id); 1113 switch (clk->id) { 1114 case PLL_APLL: 1115 rate = px30_clk_get_pll_rate(priv, APLL); 1116 break; 1117 case PLL_DPLL: 1118 rate = px30_clk_get_pll_rate(priv, DPLL); 1119 break; 1120 case PLL_CPLL: 1121 rate = px30_clk_get_pll_rate(priv, CPLL); 1122 break; 1123 case PLL_NPLL: 1124 rate = px30_clk_get_pll_rate(priv, NPLL); 1125 break; 1126 case ARMCLK: 1127 rate = px30_clk_get_pll_rate(priv, APLL); 1128 break; 1129 case HCLK_SDMMC: 1130 case HCLK_EMMC: 1131 case SCLK_SDMMC: 1132 case SCLK_EMMC: 1133 case SCLK_EMMC_SAMPLE: 1134 rate = px30_mmc_get_clk(priv, clk->id); 1135 break; 1136 case SCLK_I2C0: 1137 case SCLK_I2C1: 1138 case SCLK_I2C2: 1139 case SCLK_I2C3: 1140 rate = px30_i2c_get_clk(priv, clk->id); 1141 break; 1142 case SCLK_I2S1: 1143 rate = px30_i2s_get_clk(priv, clk->id); 1144 break; 1145 case SCLK_PWM0: 1146 case SCLK_PWM1: 1147 rate = px30_pwm_get_clk(priv, clk->id); 1148 break; 1149 case SCLK_SARADC: 1150 rate = px30_saradc_get_clk(priv); 1151 break; 1152 case SCLK_TSADC: 1153 rate = px30_tsadc_get_clk(priv); 1154 break; 1155 case SCLK_SPI0: 1156 case SCLK_SPI1: 1157 rate = px30_spi_get_clk(priv, clk->id); 1158 break; 1159 case ACLK_VOPB: 1160 case ACLK_VOPL: 1161 case DCLK_VOPB: 1162 case DCLK_VOPL: 1163 rate = px30_vop_get_clk(priv, clk->id); 1164 break; 1165 case ACLK_BUS_PRE: 1166 case HCLK_BUS_PRE: 1167 case PCLK_BUS_PRE: 1168 rate = px30_bus_get_clk(priv, clk->id); 1169 break; 1170 case ACLK_PERI_PRE: 1171 case HCLK_PERI_PRE: 1172 rate = px30_peri_get_clk(priv, clk->id); 1173 break; 1174 #ifndef CONFIG_SPL_BUILD 1175 case SCLK_CRYPTO: 1176 case SCLK_CRYPTO_APK: 1177 rate = px30_crypto_get_clk(priv, clk->id); 1178 break; 1179 #endif 1180 default: 1181 return -ENOENT; 1182 } 1183 1184 return rate; 1185 } 1186 1187 static ulong px30_clk_set_rate(struct clk *clk, ulong rate) 1188 { 1189 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 1190 ulong ret = 0; 1191 1192 if (!priv->gpll_hz && clk->id > ARMCLK) { 1193 printf("%s gpll=%lu\n", __func__, priv->gpll_hz); 1194 return -ENOENT; 1195 } 1196 1197 debug("%s %ld %ld\n", __func__, clk->id, rate); 1198 switch (clk->id) { 1199 case PLL_NPLL: 1200 ret = px30_clk_set_pll_rate(priv, NPLL, rate); 1201 break; 1202 case ARMCLK: 1203 if (priv->armclk_hz) 1204 px30_armclk_set_clk(priv, rate); 1205 priv->armclk_hz = rate; 1206 break; 1207 case HCLK_SDMMC: 1208 case HCLK_EMMC: 1209 case SCLK_SDMMC: 1210 case SCLK_EMMC: 1211 ret = px30_mmc_set_clk(priv, clk->id, rate); 1212 break; 1213 case SCLK_I2C0: 1214 case SCLK_I2C1: 1215 case SCLK_I2C2: 1216 case SCLK_I2C3: 1217 ret = px30_i2c_set_clk(priv, clk->id, rate); 1218 break; 1219 case SCLK_I2S1: 1220 ret = px30_i2s_set_clk(priv, clk->id, rate); 1221 break; 1222 case SCLK_PWM0: 1223 case SCLK_PWM1: 1224 ret = px30_pwm_set_clk(priv, clk->id, rate); 1225 break; 1226 case SCLK_SARADC: 1227 ret = px30_saradc_set_clk(priv, rate); 1228 break; 1229 case SCLK_TSADC: 1230 ret = px30_tsadc_set_clk(priv, rate); 1231 break; 1232 case SCLK_SPI0: 1233 case SCLK_SPI1: 1234 ret = px30_spi_set_clk(priv, clk->id, rate); 1235 break; 1236 case ACLK_VOPB: 1237 case ACLK_VOPL: 1238 case DCLK_VOPB: 1239 case DCLK_VOPL: 1240 ret = px30_vop_set_clk(priv, clk->id, rate); 1241 break; 1242 case ACLK_BUS_PRE: 1243 case HCLK_BUS_PRE: 1244 case PCLK_BUS_PRE: 1245 ret = px30_bus_set_clk(priv, clk->id, rate); 1246 break; 1247 case ACLK_PERI_PRE: 1248 case HCLK_PERI_PRE: 1249 ret = px30_peri_set_clk(priv, clk->id, rate); 1250 break; 1251 #ifndef CONFIG_SPL_BUILD 1252 case SCLK_CRYPTO: 1253 case SCLK_CRYPTO_APK: 1254 ret = px30_crypto_set_clk(priv, clk->id, rate); 1255 break; 1256 #endif 1257 default: 1258 return -ENOENT; 1259 } 1260 1261 return ret; 1262 } 1263 1264 #define ROCKCHIP_MMC_DELAY_SEL BIT(10) 1265 #define ROCKCHIP_MMC_DEGREE_MASK 0x3 1266 #define ROCKCHIP_MMC_DELAYNUM_OFFSET 2 1267 #define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET) 1268 1269 #define PSECS_PER_SEC 1000000000000LL 1270 /* 1271 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to 1272 * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg. 1273 */ 1274 #define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60 1275 1276 int rockchip_mmc_get_phase(struct clk *clk) 1277 { 1278 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 1279 struct px30_cru *cru = priv->cru; 1280 u32 raw_value, delay_num; 1281 u16 degrees = 0; 1282 ulong rate; 1283 1284 rate = px30_clk_get_rate(clk); 1285 1286 if (rate < 0) 1287 return rate; 1288 1289 if (clk->id == SCLK_EMMC_SAMPLE) 1290 raw_value = readl(&cru->emmc_con[1]); 1291 else 1292 raw_value = readl(&cru->sdmmc_con[1]); 1293 1294 raw_value >>= 1; 1295 degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90; 1296 1297 if (raw_value & ROCKCHIP_MMC_DELAY_SEL) { 1298 /* degrees/delaynum * 10000 */ 1299 unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) * 1300 36 * (rate / 1000000); 1301 1302 delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK); 1303 delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET; 1304 degrees += DIV_ROUND_CLOSEST(delay_num * factor, 10000); 1305 } 1306 1307 return degrees % 360; 1308 } 1309 1310 int rockchip_mmc_set_phase(struct clk *clk, u32 degrees) 1311 { 1312 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 1313 struct px30_cru *cru = priv->cru; 1314 u8 nineties, remainder, delay_num; 1315 u32 raw_value, delay; 1316 ulong rate; 1317 1318 rate = px30_clk_get_rate(clk); 1319 1320 if (rate < 0) 1321 return rate; 1322 1323 nineties = degrees / 90; 1324 remainder = (degrees % 90); 1325 1326 /* 1327 * Convert to delay; do a little extra work to make sure we 1328 * don't overflow 32-bit / 64-bit numbers. 1329 */ 1330 delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */ 1331 delay *= remainder; 1332 delay = DIV_ROUND_CLOSEST(delay, (rate / 1000) * 36 * 1333 (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10)); 1334 1335 delay_num = (u8)min_t(u32, delay, 255); 1336 1337 raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0; 1338 raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET; 1339 raw_value |= nineties; 1340 1341 raw_value <<= 1; 1342 if (clk->id == SCLK_EMMC_SAMPLE) 1343 writel(raw_value | 0xffff0000, &cru->emmc_con[1]); 1344 else 1345 writel(raw_value | 0xffff0000, &cru->sdmmc_con[1]); 1346 1347 debug("mmc set_phase(%d) delay_nums=%u reg=%#x actual_degrees=%d\n", 1348 degrees, delay_num, raw_value, rockchip_mmc_get_phase(clk)); 1349 1350 return 0; 1351 } 1352 1353 static int px30_clk_get_phase(struct clk *clk) 1354 { 1355 int ret; 1356 1357 debug("%s %ld\n", __func__, clk->id); 1358 switch (clk->id) { 1359 case SCLK_EMMC_SAMPLE: 1360 case SCLK_SDMMC_SAMPLE: 1361 ret = rockchip_mmc_get_phase(clk); 1362 break; 1363 default: 1364 return -ENOENT; 1365 } 1366 1367 return ret; 1368 } 1369 1370 static int px30_clk_set_phase(struct clk *clk, int degrees) 1371 { 1372 int ret; 1373 1374 debug("%s %ld\n", __func__, clk->id); 1375 switch (clk->id) { 1376 case SCLK_EMMC_SAMPLE: 1377 case SCLK_SDMMC_SAMPLE: 1378 ret = rockchip_mmc_set_phase(clk, degrees); 1379 break; 1380 default: 1381 return -ENOENT; 1382 } 1383 1384 return ret; 1385 } 1386 1387 static struct clk_ops px30_clk_ops = { 1388 .get_rate = px30_clk_get_rate, 1389 .set_rate = px30_clk_set_rate, 1390 .get_phase = px30_clk_get_phase, 1391 .set_phase = px30_clk_set_phase, 1392 }; 1393 1394 static int px30_clk_probe(struct udevice *dev) 1395 { 1396 struct px30_clk_priv *priv = dev_get_priv(dev); 1397 int ret; 1398 1399 if (px30_clk_get_pll_rate(priv, APLL) != APLL_HZ) { 1400 ret = px30_armclk_set_clk(priv, APLL_HZ); 1401 if (ret < 0) 1402 printf("%s failed to set armclk rate\n", __func__); 1403 } 1404 1405 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 1406 ret = clk_set_defaults(dev); 1407 if (ret) 1408 debug("%s clk_set_defaults failed %d\n", __func__, ret); 1409 1410 if (!priv->gpll_hz) { 1411 ret = px30_clk_get_gpll_rate(&priv->gpll_hz); 1412 if (ret) { 1413 printf("%s failed to get gpll rate\n", __func__); 1414 return ret; 1415 } 1416 } 1417 1418 return 0; 1419 } 1420 1421 static int px30_clk_ofdata_to_platdata(struct udevice *dev) 1422 { 1423 struct px30_clk_priv *priv = dev_get_priv(dev); 1424 1425 priv->cru = dev_read_addr_ptr(dev); 1426 1427 return 0; 1428 } 1429 1430 static int px30_clk_bind(struct udevice *dev) 1431 { 1432 int ret; 1433 struct udevice *sys_child, *sf_child; 1434 struct sysreset_reg *priv; 1435 struct softreset_reg *sf_priv; 1436 1437 /* The reset driver does not have a device node, so bind it here */ 1438 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", 1439 &sys_child); 1440 if (ret) { 1441 debug("Warning: No sysreset driver: ret=%d\n", ret); 1442 } else { 1443 priv = malloc(sizeof(struct sysreset_reg)); 1444 priv->glb_srst_fst_value = offsetof(struct px30_cru, 1445 glb_srst_fst); 1446 priv->glb_srst_snd_value = offsetof(struct px30_cru, 1447 glb_srst_snd); 1448 sys_child->priv = priv; 1449 } 1450 1451 ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset", 1452 dev_ofnode(dev), &sf_child); 1453 if (ret) { 1454 debug("Warning: No rockchip reset driver: ret=%d\n", ret); 1455 } else { 1456 sf_priv = malloc(sizeof(struct softreset_reg)); 1457 sf_priv->sf_reset_offset = offsetof(struct px30_cru, 1458 softrst_con[0]); 1459 sf_priv->sf_reset_num = 12; 1460 sf_child->priv = sf_priv; 1461 } 1462 1463 return 0; 1464 } 1465 1466 static const struct udevice_id px30_clk_ids[] = { 1467 { .compatible = "rockchip,px30-cru" }, 1468 { } 1469 }; 1470 1471 U_BOOT_DRIVER(rockchip_px30_cru) = { 1472 .name = "rockchip_px30_cru", 1473 .id = UCLASS_CLK, 1474 .of_match = px30_clk_ids, 1475 .priv_auto_alloc_size = sizeof(struct px30_clk_priv), 1476 .ofdata_to_platdata = px30_clk_ofdata_to_platdata, 1477 .ops = &px30_clk_ops, 1478 .bind = px30_clk_bind, 1479 .probe = px30_clk_probe, 1480 }; 1481 1482 static ulong px30_pclk_pmu_get_pmuclk(struct px30_pmuclk_priv *priv) 1483 { 1484 struct px30_pmucru *pmucru = priv->pmucru; 1485 u32 div, con; 1486 1487 con = readl(&pmucru->pmu_clksel_con[0]); 1488 div = (con & CLK_PMU_PCLK_DIV_MASK) >> CLK_PMU_PCLK_DIV_SHIFT; 1489 1490 return DIV_TO_RATE(priv->gpll_hz, div); 1491 } 1492 1493 static ulong px30_pclk_pmu_set_pmuclk(struct px30_pmuclk_priv *priv, ulong hz) 1494 { 1495 struct px30_pmucru *pmucru = priv->pmucru; 1496 int src_clk_div; 1497 1498 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 1499 assert(src_clk_div - 1 <= 31); 1500 1501 rk_clrsetreg(&pmucru->pmu_clksel_con[0], 1502 CLK_PMU_PCLK_DIV_MASK, 1503 (src_clk_div - 1) << CLK_PMU_PCLK_DIV_SHIFT); 1504 1505 return px30_pclk_pmu_get_pmuclk(priv); 1506 } 1507 1508 static ulong px30_gpll_get_pmuclk(struct px30_pmuclk_priv *priv) 1509 { 1510 struct px30_pmucru *pmucru = priv->pmucru; 1511 1512 return rkclk_pll_get_rate(&pmucru->pll, &pmucru->pmu_mode, GPLL); 1513 } 1514 1515 static ulong px30_gpll_set_pmuclk(struct px30_pmuclk_priv *priv, ulong hz) 1516 { 1517 struct udevice *cru_dev; 1518 struct px30_clk_priv *cru_priv; 1519 struct px30_pmucru *pmucru = priv->pmucru; 1520 u32 div; 1521 ulong emmc_rate, sdmmc_rate, nandc_rate; 1522 ulong aclk_bus_rate, hclk_bus_rate, pclk_bus_rate; 1523 ulong aclk_peri_rate, hclk_peri_rate, pclk_pmu_rate; 1524 int ret; 1525 1526 ret = uclass_get_device_by_name(UCLASS_CLK, 1527 "clock-controller@ff2b0000", 1528 &cru_dev); 1529 if (ret) { 1530 printf("%s failed to get cru device\n", __func__); 1531 return ret; 1532 } 1533 cru_priv = dev_get_priv(cru_dev); 1534 1535 if (priv->gpll_hz == hz) 1536 return priv->gpll_hz; 1537 1538 cru_priv->gpll_hz = priv->gpll_hz; 1539 div = DIV_ROUND_UP(hz, priv->gpll_hz); 1540 1541 /* save clock rate */ 1542 aclk_bus_rate = px30_bus_get_clk(cru_priv, ACLK_BUS_PRE); 1543 hclk_bus_rate = px30_bus_get_clk(cru_priv, HCLK_BUS_PRE); 1544 pclk_bus_rate = px30_bus_get_clk(cru_priv, PCLK_BUS_PRE); 1545 aclk_peri_rate = px30_peri_get_clk(cru_priv, ACLK_PERI_PRE); 1546 hclk_peri_rate = px30_peri_get_clk(cru_priv, HCLK_PERI_PRE); 1547 pclk_pmu_rate = px30_pclk_pmu_get_pmuclk(priv); 1548 debug("%s aclk_bus=%lu, hclk_bus=%lu, pclk_bus=%lu\n", __func__, 1549 aclk_bus_rate, hclk_bus_rate, pclk_bus_rate); 1550 debug("%s aclk_peri=%lu, hclk_peri=%lu, pclk_pmu=%lu\n", __func__, 1551 aclk_peri_rate, hclk_peri_rate, pclk_pmu_rate); 1552 emmc_rate = px30_mmc_get_clk(cru_priv, SCLK_EMMC); 1553 sdmmc_rate = px30_mmc_get_clk(cru_priv, SCLK_SDMMC); 1554 nandc_rate = px30_nandc_get_clk(cru_priv); 1555 debug("%s emmc=%lu, sdmmc=%lu, nandc=%lu\n", __func__, 1556 emmc_rate, sdmmc_rate, nandc_rate); 1557 1558 /* avoid rate too large, reduce rate first */ 1559 px30_bus_set_clk(cru_priv, ACLK_BUS_PRE, aclk_bus_rate / div); 1560 px30_bus_set_clk(cru_priv, HCLK_BUS_PRE, hclk_bus_rate / div); 1561 px30_bus_set_clk(cru_priv, PCLK_BUS_PRE, pclk_bus_rate / div); 1562 px30_peri_set_clk(cru_priv, ACLK_PERI_PRE, aclk_peri_rate / div); 1563 px30_peri_set_clk(cru_priv, HCLK_PERI_PRE, hclk_peri_rate / div); 1564 px30_pclk_pmu_set_pmuclk(priv, pclk_pmu_rate / div); 1565 1566 px30_mmc_set_clk(cru_priv, SCLK_EMMC, emmc_rate / div); 1567 px30_mmc_set_clk(cru_priv, SCLK_SDMMC, sdmmc_rate / div); 1568 px30_nandc_set_clk(cru_priv, nandc_rate / div); 1569 1570 /* change gpll rate */ 1571 rkclk_set_pll(&pmucru->pll, &pmucru->pmu_mode, GPLL, hz); 1572 priv->gpll_hz = px30_gpll_get_pmuclk(priv); 1573 cru_priv->gpll_hz = priv->gpll_hz; 1574 1575 /* restore clock rate */ 1576 px30_bus_set_clk(cru_priv, ACLK_BUS_PRE, aclk_bus_rate); 1577 px30_bus_set_clk(cru_priv, HCLK_BUS_PRE, hclk_bus_rate); 1578 px30_bus_set_clk(cru_priv, PCLK_BUS_PRE, pclk_bus_rate); 1579 px30_peri_set_clk(cru_priv, ACLK_PERI_PRE, aclk_peri_rate); 1580 px30_peri_set_clk(cru_priv, HCLK_PERI_PRE, hclk_peri_rate); 1581 px30_pclk_pmu_set_pmuclk(priv, pclk_pmu_rate); 1582 1583 px30_mmc_set_clk(cru_priv, SCLK_EMMC, emmc_rate); 1584 px30_mmc_set_clk(cru_priv, SCLK_SDMMC, sdmmc_rate); 1585 px30_nandc_set_clk(cru_priv, nandc_rate); 1586 1587 return priv->gpll_hz; 1588 } 1589 1590 static ulong px30_pmuclk_get_rate(struct clk *clk) 1591 { 1592 struct px30_pmuclk_priv *priv = dev_get_priv(clk->dev); 1593 ulong rate = 0; 1594 1595 debug("%s %ld\n", __func__, clk->id); 1596 switch (clk->id) { 1597 case PLL_GPLL: 1598 rate = px30_gpll_get_pmuclk(priv); 1599 break; 1600 case PCLK_PMU_PRE: 1601 rate = px30_pclk_pmu_get_pmuclk(priv); 1602 break; 1603 default: 1604 return -ENOENT; 1605 } 1606 1607 return rate; 1608 } 1609 1610 static ulong px30_pmuclk_set_rate(struct clk *clk, ulong rate) 1611 { 1612 struct px30_pmuclk_priv *priv = dev_get_priv(clk->dev); 1613 ulong ret = 0; 1614 1615 debug("%s %ld %ld\n", __func__, clk->id, rate); 1616 switch (clk->id) { 1617 case PLL_GPLL: 1618 ret = px30_gpll_set_pmuclk(priv, rate); 1619 break; 1620 case PCLK_PMU_PRE: 1621 ret = px30_pclk_pmu_set_pmuclk(priv, rate); 1622 break; 1623 default: 1624 return -ENOENT; 1625 } 1626 1627 return ret; 1628 } 1629 1630 static struct clk_ops px30_pmuclk_ops = { 1631 .get_rate = px30_pmuclk_get_rate, 1632 .set_rate = px30_pmuclk_set_rate, 1633 }; 1634 1635 static void px30_clk_init(struct px30_pmuclk_priv *priv) 1636 { 1637 struct udevice *cru_dev; 1638 struct px30_clk_priv *cru_priv; 1639 ulong npll_hz; 1640 int ret; 1641 1642 priv->gpll_hz = px30_gpll_get_pmuclk(priv); 1643 if (priv->gpll_hz != GPLL_HZ) { 1644 ret = px30_gpll_set_pmuclk(priv, GPLL_HZ); 1645 if (ret < 0) 1646 printf("%s failed to set gpll rate\n", __func__); 1647 } 1648 1649 ret = uclass_get_device_by_name(UCLASS_CLK, 1650 "clock-controller@ff2b0000", 1651 &cru_dev); 1652 if (ret) { 1653 printf("%s failed to get cru device\n", __func__); 1654 return; 1655 } 1656 cru_priv = dev_get_priv(cru_dev); 1657 cru_priv->gpll_hz = priv->gpll_hz; 1658 1659 npll_hz = px30_clk_get_pll_rate(cru_priv, NPLL); 1660 if (npll_hz != NPLL_HZ) { 1661 ret = px30_clk_set_pll_rate(cru_priv, NPLL, NPLL_HZ); 1662 if (ret < 0) 1663 printf("%s failed to set npll rate\n", __func__); 1664 } 1665 1666 px30_bus_set_clk(cru_priv, ACLK_BUS_PRE, ACLK_BUS_HZ); 1667 px30_bus_set_clk(cru_priv, HCLK_BUS_PRE, HCLK_BUS_HZ); 1668 px30_bus_set_clk(cru_priv, PCLK_BUS_PRE, PCLK_BUS_HZ); 1669 px30_peri_set_clk(cru_priv, ACLK_PERI_PRE, ACLK_PERI_HZ); 1670 px30_peri_set_clk(cru_priv, HCLK_PERI_PRE, HCLK_PERI_HZ); 1671 px30_pclk_pmu_set_pmuclk(priv, PCLK_PMU_HZ); 1672 } 1673 1674 static int px30_pmuclk_probe(struct udevice *dev) 1675 { 1676 struct px30_pmuclk_priv *priv = dev_get_priv(dev); 1677 int ret; 1678 1679 px30_clk_init(priv); 1680 1681 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 1682 ret = clk_set_defaults(dev); 1683 if (ret) 1684 debug("%s clk_set_defaults failed %d\n", __func__, ret); 1685 1686 return 0; 1687 } 1688 1689 static int px30_pmuclk_ofdata_to_platdata(struct udevice *dev) 1690 { 1691 struct px30_pmuclk_priv *priv = dev_get_priv(dev); 1692 1693 priv->pmucru = dev_read_addr_ptr(dev); 1694 1695 return 0; 1696 } 1697 1698 static const struct udevice_id px30_pmuclk_ids[] = { 1699 { .compatible = "rockchip,px30-pmucru" }, 1700 { } 1701 }; 1702 1703 U_BOOT_DRIVER(rockchip_px30_pmucru) = { 1704 .name = "rockchip_px30_pmucru", 1705 .id = UCLASS_CLK, 1706 .of_match = px30_pmuclk_ids, 1707 .priv_auto_alloc_size = sizeof(struct px30_pmuclk_priv), 1708 .ofdata_to_platdata = px30_pmuclk_ofdata_to_platdata, 1709 .ops = &px30_pmuclk_ops, 1710 .probe = px30_pmuclk_probe, 1711 }; 1712 1713 /** 1714 * soc_clk_dump() - Print clock frequencies 1715 * Returns zero on success 1716 * 1717 * Implementation for the clk dump command. 1718 */ 1719 int soc_clk_dump(void) 1720 { 1721 struct udevice *cru_dev, *pmucru_dev; 1722 const struct px30_clk_info *clk_dump; 1723 struct clk clk; 1724 unsigned long clk_count = ARRAY_SIZE(clks_dump); 1725 unsigned long rate; 1726 int i, ret; 1727 1728 ret = uclass_get_device_by_driver(UCLASS_CLK, 1729 DM_GET_DRIVER(rockchip_px30_cru), 1730 &cru_dev); 1731 if (ret) { 1732 printf("%s failed to get cru device\n", __func__); 1733 return ret; 1734 } 1735 1736 ret = uclass_get_device_by_driver(UCLASS_CLK, 1737 DM_GET_DRIVER(rockchip_px30_pmucru), 1738 &pmucru_dev); 1739 if (ret) { 1740 printf("%s failed to get pmucru device\n", __func__); 1741 return ret; 1742 } 1743 1744 printf("CLK:\n"); 1745 for (i = 0; i < clk_count; i++) { 1746 clk_dump = &clks_dump[i]; 1747 if (clk_dump->name) { 1748 clk.id = clk_dump->id; 1749 if (clk_dump->is_cru) 1750 ret = clk_request(cru_dev, &clk); 1751 else 1752 ret = clk_request(pmucru_dev, &clk); 1753 if (ret < 0) 1754 return ret; 1755 1756 rate = clk_get_rate(&clk); 1757 clk_free(&clk); 1758 if (i == 0) { 1759 if (rate < 0) 1760 printf("%s %s\n", clk_dump->name, 1761 "unknown"); 1762 else 1763 printf("%s %lu KHz\n", clk_dump->name, 1764 rate / 1000); 1765 } else { 1766 if (rate < 0) 1767 printf("%s %s\n", clk_dump->name, 1768 "unknown"); 1769 else 1770 printf("%s %lu KHz\n", clk_dump->name, 1771 rate / 1000); 1772 } 1773 } 1774 } 1775 1776 return 0; 1777 } 1778