1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <bitfield.h> 9 #include <clk-uclass.h> 10 #include <dm.h> 11 #include <errno.h> 12 #include <syscon.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch/cru_px30.h> 15 #include <asm/arch/hardware.h> 16 #include <asm/io.h> 17 #include <dm/lists.h> 18 #include <dt-bindings/clock/px30-cru.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 enum { 23 VCO_MAX_HZ = 3200U * 1000000, 24 VCO_MIN_HZ = 800 * 1000000, 25 OUTPUT_MAX_HZ = 3200U * 1000000, 26 OUTPUT_MIN_HZ = 24 * 1000000, 27 }; 28 29 #define PX30_VOP_PLL_LIMIT 600000000 30 31 #define PX30_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ 32 _postdiv2, _dsmpd, _frac) \ 33 { \ 34 .rate = _rate##U, \ 35 .fbdiv = _fbdiv, \ 36 .postdiv1 = _postdiv1, \ 37 .refdiv = _refdiv, \ 38 .postdiv2 = _postdiv2, \ 39 .dsmpd = _dsmpd, \ 40 .frac = _frac, \ 41 } 42 43 #define PX30_CPUCLK_RATE(_rate, _aclk_div, _pclk_div) \ 44 { \ 45 .rate = _rate##U, \ 46 .aclk_div = _aclk_div, \ 47 .pclk_div = _pclk_div, \ 48 } 49 50 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 51 52 #define PX30_CLK_DUMP(_id, _name, _iscru) \ 53 { \ 54 .id = _id, \ 55 .name = _name, \ 56 .is_cru = _iscru, \ 57 } 58 59 static struct pll_rate_table px30_pll_rates[] = { 60 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 61 PX30_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), 62 PX30_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), 63 PX30_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), 64 PX30_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 65 PX30_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), 66 PX30_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), 67 PX30_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0), 68 }; 69 70 static const struct px30_clk_info clks_dump[] = { 71 PX30_CLK_DUMP(PLL_APLL, "apll", true), 72 PX30_CLK_DUMP(PLL_DPLL, "dpll", true), 73 PX30_CLK_DUMP(PLL_CPLL, "cpll", true), 74 PX30_CLK_DUMP(PLL_NPLL, "npll", true), 75 PX30_CLK_DUMP(PLL_GPLL, "gpll", false), 76 PX30_CLK_DUMP(ACLK_BUS_PRE, "aclk_bus", true), 77 PX30_CLK_DUMP(HCLK_BUS_PRE, "hclk_bus", true), 78 PX30_CLK_DUMP(PCLK_BUS_PRE, "pclk_bus", true), 79 PX30_CLK_DUMP(ACLK_PERI_PRE, "aclk_peri", true), 80 PX30_CLK_DUMP(HCLK_PERI_PRE, "hclk_peri", true), 81 PX30_CLK_DUMP(PCLK_PMU_PRE, "pclk_pmu", false), 82 }; 83 84 static struct cpu_rate_table px30_cpu_rates[] = { 85 PX30_CPUCLK_RATE(1200000000, 1, 5), 86 PX30_CPUCLK_RATE(1008000000, 1, 5), 87 PX30_CPUCLK_RATE(816000000, 1, 3), 88 PX30_CPUCLK_RATE(600000000, 1, 3), 89 PX30_CPUCLK_RATE(408000000, 1, 1), 90 }; 91 92 static u8 pll_mode_shift[PLL_COUNT] = { 93 APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, 94 NPLL_MODE_SHIFT, GPLL_MODE_SHIFT 95 }; 96 static u32 pll_mode_mask[PLL_COUNT] = { 97 APLL_MODE_MASK, DPLL_MODE_MASK, CPLL_MODE_MASK, 98 NPLL_MODE_MASK, GPLL_MODE_MASK 99 }; 100 101 static struct pll_rate_table auto_table; 102 103 static ulong px30_clk_get_pll_rate(struct px30_clk_priv *priv, 104 enum px30_pll_id pll_id); 105 106 static struct pll_rate_table *pll_clk_set_by_auto(u32 drate) 107 { 108 struct pll_rate_table *rate = &auto_table; 109 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; 110 u32 postdiv1, postdiv2 = 1; 111 u32 fref_khz; 112 u32 diff_khz, best_diff_khz; 113 const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16; 114 const u32 max_postdiv1 = 7, max_postdiv2 = 7; 115 u32 vco_khz; 116 u32 rate_khz = drate / KHz; 117 118 if (!drate) { 119 printf("%s: the frequency can't be 0 Hz\n", __func__); 120 return NULL; 121 } 122 123 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, rate_khz); 124 if (postdiv1 > max_postdiv1) { 125 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); 126 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); 127 } 128 129 vco_khz = rate_khz * postdiv1 * postdiv2; 130 131 if (vco_khz < (VCO_MIN_HZ / KHz) || vco_khz > (VCO_MAX_HZ / KHz) || 132 postdiv2 > max_postdiv2) { 133 printf("%s: Cannot find out a supported VCO for Freq (%uHz)\n", 134 __func__, rate_khz); 135 return NULL; 136 } 137 138 rate->postdiv1 = postdiv1; 139 rate->postdiv2 = postdiv2; 140 141 best_diff_khz = vco_khz; 142 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { 143 fref_khz = ref_khz / refdiv; 144 145 fbdiv = vco_khz / fref_khz; 146 if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv)) 147 continue; 148 diff_khz = vco_khz - fbdiv * fref_khz; 149 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) { 150 fbdiv++; 151 diff_khz = fref_khz - diff_khz; 152 } 153 154 if (diff_khz >= best_diff_khz) 155 continue; 156 157 best_diff_khz = diff_khz; 158 rate->refdiv = refdiv; 159 rate->fbdiv = fbdiv; 160 } 161 162 if (best_diff_khz > 4 * (MHz / KHz)) { 163 printf("%s: Failed to match output frequency %u bestis %u Hz\n", 164 __func__, rate_khz, 165 best_diff_khz * KHz); 166 return NULL; 167 } 168 169 return rate; 170 } 171 172 static const struct pll_rate_table *get_pll_settings(unsigned long rate) 173 { 174 unsigned int rate_count = ARRAY_SIZE(px30_pll_rates); 175 int i; 176 177 for (i = 0; i < rate_count; i++) { 178 if (rate == px30_pll_rates[i].rate) 179 return &px30_pll_rates[i]; 180 } 181 182 return pll_clk_set_by_auto(rate); 183 } 184 185 static const struct cpu_rate_table *get_cpu_settings(unsigned long rate) 186 { 187 unsigned int rate_count = ARRAY_SIZE(px30_cpu_rates); 188 int i; 189 190 for (i = 0; i < rate_count; i++) { 191 if (rate == px30_cpu_rates[i].rate) 192 return &px30_cpu_rates[i]; 193 } 194 195 return NULL; 196 } 197 198 /* 199 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63): 200 * Formulas also embedded within the Fractional PLL Verilog model: 201 * If DSMPD = 1 (DSM is disabled, "integer mode") 202 * FOUTVCO = FREF / REFDIV * FBDIV 203 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 204 * Where: 205 * FOUTVCO = Fractional PLL non-divided output frequency 206 * FOUTPOSTDIV = Fractional PLL divided output frequency 207 * (output of second post divider) 208 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input) 209 * REFDIV = Fractional PLL input reference clock divider 210 * FBDIV = Integer value programmed into feedback divide 211 * 212 */ 213 static int rkclk_set_pll(struct px30_pll *pll, unsigned int *mode, 214 enum px30_pll_id pll_id, 215 unsigned long drate) 216 { 217 const struct pll_rate_table *rate; 218 uint vco_hz, output_hz; 219 220 rate = get_pll_settings(drate); 221 if (!rate) { 222 printf("%s unsupport rate\n", __func__); 223 return -EINVAL; 224 } 225 226 /* All PLLs have same VCO and output frequency range restrictions. */ 227 vco_hz = OSC_HZ / 1000 * rate->fbdiv / rate->refdiv * 1000; 228 output_hz = vco_hz / rate->postdiv1 / rate->postdiv2; 229 230 debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n", 231 pll, rate->fbdiv, rate->refdiv, rate->postdiv1, 232 rate->postdiv2, vco_hz, output_hz); 233 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && 234 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ); 235 236 /* 237 * When power on or changing PLL setting, 238 * we must force PLL into slow mode to ensure output stable clock. 239 */ 240 rk_clrsetreg(mode, pll_mode_mask[pll_id], 241 PLLMUX_FROM_XIN24M << pll_mode_shift[pll_id]); 242 243 /* use integer mode */ 244 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); 245 /* Power down */ 246 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); 247 248 rk_clrsetreg(&pll->con0, 249 PLL_POSTDIV1_MASK | PLL_FBDIV_MASK, 250 (rate->postdiv1 << PLL_POSTDIV1_SHIFT) | rate->fbdiv); 251 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, 252 (rate->postdiv2 << PLL_POSTDIV2_SHIFT | 253 rate->refdiv << PLL_REFDIV_SHIFT)); 254 255 /* Power Up */ 256 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); 257 258 /* waiting for pll lock */ 259 while (!(readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))) 260 udelay(1); 261 262 rk_clrsetreg(mode, pll_mode_mask[pll_id], 263 PLLMUX_FROM_PLL << pll_mode_shift[pll_id]); 264 265 return 0; 266 } 267 268 static uint32_t rkclk_pll_get_rate(struct px30_pll *pll, unsigned int *mode, 269 enum px30_pll_id pll_id) 270 { 271 u32 refdiv, fbdiv, postdiv1, postdiv2; 272 u32 con, shift, mask; 273 274 con = readl(mode); 275 shift = pll_mode_shift[pll_id]; 276 mask = pll_mode_mask[pll_id]; 277 278 switch ((con & mask) >> shift) { 279 case PLLMUX_FROM_XIN24M: 280 return OSC_HZ; 281 case PLLMUX_FROM_PLL: 282 /* normal mode */ 283 con = readl(&pll->con0); 284 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; 285 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; 286 con = readl(&pll->con1); 287 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; 288 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; 289 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; 290 case PLLMUX_FROM_RTC32K: 291 default: 292 return 32768; 293 } 294 } 295 296 static ulong px30_i2c_get_clk(struct px30_clk_priv *priv, ulong clk_id) 297 { 298 struct px30_cru *cru = priv->cru; 299 u32 div, con; 300 301 switch (clk_id) { 302 case SCLK_I2C0: 303 con = readl(&cru->clksel_con[49]); 304 div = con >> CLK_I2C0_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; 305 break; 306 case SCLK_I2C1: 307 con = readl(&cru->clksel_con[49]); 308 div = con >> CLK_I2C1_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; 309 break; 310 case SCLK_I2C2: 311 con = readl(&cru->clksel_con[50]); 312 div = con >> CLK_I2C2_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; 313 break; 314 case SCLK_I2C3: 315 con = readl(&cru->clksel_con[50]); 316 div = con >> CLK_I2C3_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; 317 break; 318 default: 319 printf("do not support this i2c bus\n"); 320 return -EINVAL; 321 } 322 323 return DIV_TO_RATE(priv->gpll_hz, div); 324 } 325 326 static ulong px30_i2c_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) 327 { 328 struct px30_cru *cru = priv->cru; 329 int src_clk_div; 330 331 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 332 assert(src_clk_div - 1 <= 127); 333 334 switch (clk_id) { 335 case SCLK_I2C0: 336 rk_clrsetreg(&cru->clksel_con[49], 337 CLK_I2C_DIV_CON_MASK << CLK_I2C0_DIV_CON_SHIFT | 338 CLK_I2C_PLL_SEL_MASK << CLK_I2C0_PLL_SEL_SHIFT, 339 (src_clk_div - 1) << CLK_I2C0_DIV_CON_SHIFT | 340 CLK_I2C_PLL_SEL_GPLL << CLK_I2C0_PLL_SEL_SHIFT); 341 break; 342 case SCLK_I2C1: 343 rk_clrsetreg(&cru->clksel_con[49], 344 CLK_I2C_DIV_CON_MASK << CLK_I2C1_DIV_CON_SHIFT | 345 CLK_I2C_PLL_SEL_MASK << CLK_I2C1_PLL_SEL_SHIFT, 346 (src_clk_div - 1) << CLK_I2C1_DIV_CON_SHIFT | 347 CLK_I2C_PLL_SEL_GPLL << CLK_I2C1_PLL_SEL_SHIFT); 348 break; 349 case SCLK_I2C2: 350 rk_clrsetreg(&cru->clksel_con[50], 351 CLK_I2C_DIV_CON_MASK << CLK_I2C2_DIV_CON_SHIFT | 352 CLK_I2C_PLL_SEL_MASK << CLK_I2C2_PLL_SEL_SHIFT, 353 (src_clk_div - 1) << CLK_I2C2_DIV_CON_SHIFT | 354 CLK_I2C_PLL_SEL_GPLL << CLK_I2C2_PLL_SEL_SHIFT); 355 break; 356 case SCLK_I2C3: 357 rk_clrsetreg(&cru->clksel_con[50], 358 CLK_I2C_DIV_CON_MASK << CLK_I2C3_DIV_CON_SHIFT | 359 CLK_I2C_PLL_SEL_MASK << CLK_I2C3_PLL_SEL_SHIFT, 360 (src_clk_div - 1) << CLK_I2C3_DIV_CON_SHIFT | 361 CLK_I2C_PLL_SEL_GPLL << CLK_I2C3_PLL_SEL_SHIFT); 362 break; 363 default: 364 printf("do not support this i2c bus\n"); 365 return -EINVAL; 366 } 367 368 return px30_i2c_get_clk(priv, clk_id); 369 } 370 371 /* 372 * calculate best rational approximation for a given fraction 373 * taking into account restricted register size, e.g. to find 374 * appropriate values for a pll with 5 bit denominator and 375 * 8 bit numerator register fields, trying to set up with a 376 * frequency ratio of 3.1415, one would say: 377 * 378 * rational_best_approximation(31415, 10000, 379 * (1 << 8) - 1, (1 << 5) - 1, &n, &d); 380 * 381 * you may look at given_numerator as a fixed point number, 382 * with the fractional part size described in given_denominator. 383 * 384 * for theoretical background, see: 385 * http://en.wikipedia.org/wiki/Continued_fraction 386 */ 387 static void rational_best_approximation( 388 unsigned long given_numerator, unsigned long given_denominator, 389 unsigned long max_numerator, unsigned long max_denominator, 390 unsigned long *best_numerator, unsigned long *best_denominator) 391 { 392 unsigned long n, d, n0, d0, n1, d1; 393 394 n = given_numerator; 395 d = given_denominator; 396 n0 = 0; 397 d1 = 0; 398 n1 = 1; 399 d0 = 1; 400 for (;;) { 401 unsigned long t, a; 402 403 if (n1 > max_numerator || d1 > max_denominator) { 404 n1 = n0; 405 d1 = d0; 406 break; 407 } 408 if (d == 0) 409 break; 410 t = d; 411 a = n / d; 412 d = n % d; 413 n = t; 414 t = n0 + a * n1; 415 n0 = n1; 416 n1 = t; 417 t = d0 + a * d1; 418 d0 = d1; 419 d1 = t; 420 } 421 *best_numerator = n1; 422 *best_denominator = d1; 423 } 424 425 static ulong px30_i2s_get_clk(struct px30_clk_priv *priv, ulong clk_id) 426 { 427 u32 con, fracdiv, gate; 428 u32 clk_src = GPLL_HZ / 2; 429 unsigned long m, n; 430 struct px30_cru *cru = priv->cru; 431 432 switch (clk_id) { 433 case SCLK_I2S1: 434 con = readl(&cru->clksel_con[30]); 435 fracdiv = readl(&cru->clksel_con[31]); 436 gate = readl(&cru->clkgate_con[10]); 437 m = fracdiv & CLK_I2S1_FRAC_NUMERATOR_MASK; 438 m >>= CLK_I2S1_FRAC_NUMERATOR_SHIFT; 439 n = fracdiv & CLK_I2S1_FRAC_DENOMINATOR_MASK; 440 n >>= CLK_I2S1_FRAC_DENOMINATOR_SHIFT; 441 debug("con30: 0x%x, gate: 0x%x, frac: 0x%x\n", 442 con, gate, fracdiv); 443 break; 444 default: 445 printf("do not support this i2s bus\n"); 446 return -EINVAL; 447 } 448 449 return clk_src * n / m; 450 } 451 452 static ulong px30_i2s_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) 453 { 454 u32 clk_src; 455 unsigned long m, n, val; 456 struct px30_cru *cru = priv->cru; 457 458 clk_src = GPLL_HZ / 2; 459 rational_best_approximation(hz, clk_src, 460 GENMASK(16 - 1, 0), 461 GENMASK(16 - 1, 0), 462 &m, &n); 463 switch (clk_id) { 464 case SCLK_I2S1: 465 rk_clrsetreg(&cru->clksel_con[30], 466 CLK_I2S1_PLL_SEL_MASK, CLK_I2S1_PLL_SEL_GPLL); 467 rk_clrsetreg(&cru->clksel_con[30], 468 CLK_I2S1_DIV_CON_MASK, 0x1); 469 rk_clrsetreg(&cru->clksel_con[30], 470 CLK_I2S1_SEL_MASK, CLK_I2S1_SEL_FRAC); 471 val = m << CLK_I2S1_FRAC_NUMERATOR_SHIFT | n; 472 writel(val, &cru->clksel_con[31]); 473 rk_clrsetreg(&cru->clkgate_con[10], 474 CLK_I2S1_OUT_MCLK_PAD_MASK, 475 CLK_I2S1_OUT_MCLK_PAD_ENABLE); 476 break; 477 default: 478 printf("do not support this i2s bus\n"); 479 return -EINVAL; 480 } 481 482 return px30_i2s_get_clk(priv, clk_id); 483 } 484 485 static ulong px30_nandc_get_clk(struct px30_clk_priv *priv) 486 { 487 struct px30_cru *cru = priv->cru; 488 u32 div, con; 489 490 con = readl(&cru->clksel_con[15]); 491 div = (con & NANDC_DIV_MASK) >> NANDC_DIV_SHIFT; 492 493 return DIV_TO_RATE(priv->gpll_hz, div); 494 } 495 496 static ulong px30_nandc_set_clk(struct px30_clk_priv *priv, 497 ulong set_rate) 498 { 499 struct px30_cru *cru = priv->cru; 500 int src_clk_div; 501 502 /* Select nandc source from GPLL by default */ 503 /* nandc clock defaulg div 2 internal, need provide double in cru */ 504 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, set_rate); 505 assert(src_clk_div - 1 <= 31); 506 507 rk_clrsetreg(&cru->clksel_con[15], 508 NANDC_CLK_SEL_MASK | NANDC_PLL_MASK | 509 NANDC_DIV_MASK, 510 NANDC_CLK_SEL_NANDC << NANDC_CLK_SEL_SHIFT | 511 NANDC_SEL_GPLL << NANDC_PLL_SHIFT | 512 (src_clk_div - 1) << NANDC_DIV_SHIFT); 513 514 return px30_nandc_get_clk(priv); 515 } 516 517 static ulong px30_mmc_get_clk(struct px30_clk_priv *priv, uint clk_id) 518 { 519 struct px30_cru *cru = priv->cru; 520 u32 div, con, con_id; 521 522 switch (clk_id) { 523 case HCLK_SDMMC: 524 case SCLK_SDMMC: 525 con_id = 16; 526 break; 527 case HCLK_EMMC: 528 case SCLK_EMMC: 529 case SCLK_EMMC_SAMPLE: 530 con_id = 20; 531 break; 532 default: 533 return -EINVAL; 534 } 535 536 con = readl(&cru->clksel_con[con_id]); 537 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; 538 539 if ((con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT 540 == EMMC_SEL_24M) 541 return DIV_TO_RATE(OSC_HZ, div) / 2; 542 else 543 return DIV_TO_RATE(priv->gpll_hz, div) / 2; 544 545 } 546 547 static ulong px30_mmc_set_clk(struct px30_clk_priv *priv, 548 ulong clk_id, ulong set_rate) 549 { 550 struct px30_cru *cru = priv->cru; 551 int src_clk_div; 552 u32 con_id; 553 554 switch (clk_id) { 555 case HCLK_SDMMC: 556 case SCLK_SDMMC: 557 con_id = 16; 558 break; 559 case HCLK_EMMC: 560 case SCLK_EMMC: 561 con_id = 20; 562 break; 563 default: 564 return -EINVAL; 565 } 566 567 /* Select clk_sdmmc/emmc source from GPLL by default */ 568 /* mmc clock defaulg div 2 internal, need provide double in cru */ 569 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, set_rate); 570 571 if (src_clk_div > 127) { 572 /* use 24MHz source for 400KHz clock */ 573 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); 574 rk_clrsetreg(&cru->clksel_con[con_id], 575 EMMC_PLL_MASK | EMMC_DIV_MASK, 576 EMMC_SEL_24M << EMMC_PLL_SHIFT | 577 (src_clk_div - 1) << EMMC_DIV_SHIFT); 578 } else { 579 rk_clrsetreg(&cru->clksel_con[con_id], 580 EMMC_PLL_MASK | EMMC_DIV_MASK, 581 EMMC_SEL_GPLL << EMMC_PLL_SHIFT | 582 (src_clk_div - 1) << EMMC_DIV_SHIFT); 583 } 584 rk_clrsetreg(&cru->clksel_con[con_id +1], EMMC_CLK_SEL_MASK, 585 EMMC_CLK_SEL_EMMC); 586 587 return px30_mmc_get_clk(priv, clk_id); 588 } 589 590 static ulong px30_pwm_get_clk(struct px30_clk_priv *priv, ulong clk_id) 591 { 592 struct px30_cru *cru = priv->cru; 593 u32 div, con; 594 595 switch (clk_id) { 596 case SCLK_PWM0: 597 con = readl(&cru->clksel_con[52]); 598 div = con >> CLK_PWM0_DIV_CON_SHIFT & CLK_PWM_DIV_CON_MASK; 599 break; 600 case SCLK_PWM1: 601 con = readl(&cru->clksel_con[52]); 602 div = con >> CLK_PWM1_DIV_CON_SHIFT & CLK_PWM_DIV_CON_MASK; 603 break; 604 default: 605 printf("do not support this pwm bus\n"); 606 return -EINVAL; 607 } 608 609 return DIV_TO_RATE(priv->gpll_hz, div); 610 } 611 612 static ulong px30_pwm_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) 613 { 614 struct px30_cru *cru = priv->cru; 615 int src_clk_div; 616 617 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 618 assert(src_clk_div - 1 <= 127); 619 620 switch (clk_id) { 621 case SCLK_PWM0: 622 rk_clrsetreg(&cru->clksel_con[52], 623 CLK_PWM_DIV_CON_MASK << CLK_PWM0_DIV_CON_SHIFT | 624 CLK_PWM_PLL_SEL_MASK << CLK_PWM0_PLL_SEL_SHIFT, 625 (src_clk_div - 1) << CLK_PWM0_DIV_CON_SHIFT | 626 CLK_PWM_PLL_SEL_GPLL << CLK_PWM0_PLL_SEL_SHIFT); 627 break; 628 case SCLK_PWM1: 629 rk_clrsetreg(&cru->clksel_con[52], 630 CLK_PWM_DIV_CON_MASK << CLK_PWM1_DIV_CON_SHIFT | 631 CLK_PWM_PLL_SEL_MASK << CLK_PWM1_PLL_SEL_SHIFT, 632 (src_clk_div - 1) << CLK_PWM1_DIV_CON_SHIFT | 633 CLK_PWM_PLL_SEL_GPLL << CLK_PWM1_PLL_SEL_SHIFT); 634 break; 635 default: 636 printf("do not support this pwm bus\n"); 637 return -EINVAL; 638 } 639 640 return px30_pwm_get_clk(priv, clk_id); 641 } 642 643 static ulong px30_saradc_get_clk(struct px30_clk_priv *priv) 644 { 645 struct px30_cru *cru = priv->cru; 646 u32 div, con; 647 648 con = readl(&cru->clksel_con[55]); 649 div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK; 650 651 return DIV_TO_RATE(OSC_HZ, div); 652 } 653 654 static ulong px30_saradc_set_clk(struct px30_clk_priv *priv, uint hz) 655 { 656 struct px30_cru *cru = priv->cru; 657 int src_clk_div; 658 659 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); 660 assert(src_clk_div - 1 <= 2047); 661 662 rk_clrsetreg(&cru->clksel_con[55], 663 CLK_SARADC_DIV_CON_MASK, 664 (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT); 665 666 return px30_saradc_get_clk(priv); 667 } 668 669 static ulong px30_tsadc_get_clk(struct px30_clk_priv *priv) 670 { 671 struct px30_cru *cru = priv->cru; 672 u32 div, con; 673 674 con = readl(&cru->clksel_con[54]); 675 div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK; 676 677 return DIV_TO_RATE(OSC_HZ, div); 678 } 679 680 static ulong px30_tsadc_set_clk(struct px30_clk_priv *priv, uint hz) 681 { 682 struct px30_cru *cru = priv->cru; 683 int src_clk_div; 684 685 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); 686 assert(src_clk_div - 1 <= 2047); 687 688 rk_clrsetreg(&cru->clksel_con[54], 689 CLK_SARADC_DIV_CON_MASK, 690 (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT); 691 692 return px30_tsadc_get_clk(priv); 693 } 694 695 static ulong px30_spi_get_clk(struct px30_clk_priv *priv, ulong clk_id) 696 { 697 struct px30_cru *cru = priv->cru; 698 u32 div, con; 699 700 switch (clk_id) { 701 case SCLK_SPI0: 702 con = readl(&cru->clksel_con[53]); 703 div = con >> CLK_SPI0_DIV_CON_SHIFT & CLK_SPI_DIV_CON_MASK; 704 break; 705 case SCLK_SPI1: 706 con = readl(&cru->clksel_con[53]); 707 div = con >> CLK_SPI1_DIV_CON_SHIFT & CLK_SPI_DIV_CON_MASK; 708 break; 709 default: 710 printf("do not support this pwm bus\n"); 711 return -EINVAL; 712 } 713 714 return DIV_TO_RATE(priv->gpll_hz, div); 715 } 716 717 static ulong px30_spi_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) 718 { 719 struct px30_cru *cru = priv->cru; 720 int src_clk_div; 721 722 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 723 assert(src_clk_div - 1 <= 127); 724 725 switch (clk_id) { 726 case SCLK_SPI0: 727 rk_clrsetreg(&cru->clksel_con[53], 728 CLK_SPI_DIV_CON_MASK << CLK_SPI0_DIV_CON_SHIFT | 729 CLK_SPI_PLL_SEL_MASK << CLK_SPI0_PLL_SEL_SHIFT, 730 (src_clk_div - 1) << CLK_SPI0_DIV_CON_SHIFT | 731 CLK_SPI_PLL_SEL_GPLL << CLK_SPI0_PLL_SEL_SHIFT); 732 break; 733 case SCLK_SPI1: 734 rk_clrsetreg(&cru->clksel_con[53], 735 CLK_SPI_DIV_CON_MASK << CLK_SPI1_DIV_CON_SHIFT | 736 CLK_SPI_PLL_SEL_MASK << CLK_SPI1_PLL_SEL_SHIFT, 737 (src_clk_div - 1) << CLK_SPI1_DIV_CON_SHIFT | 738 CLK_SPI_PLL_SEL_GPLL << CLK_SPI1_PLL_SEL_SHIFT); 739 break; 740 default: 741 printf("do not support this pwm bus\n"); 742 return -EINVAL; 743 } 744 745 return px30_spi_get_clk(priv, clk_id); 746 } 747 748 static ulong px30_vop_get_clk(struct px30_clk_priv *priv, ulong clk_id) 749 { 750 struct px30_cru *cru = priv->cru; 751 u32 div, con, parent; 752 753 switch (clk_id) { 754 case ACLK_VOPB: 755 case ACLK_VOPL: 756 con = readl(&cru->clksel_con[3]); 757 div = con & ACLK_VO_DIV_MASK; 758 parent = priv->gpll_hz; 759 break; 760 case DCLK_VOPB: 761 con = readl(&cru->clksel_con[5]); 762 div = con & DCLK_VOPB_DIV_MASK; 763 parent = rkclk_pll_get_rate(&cru->pll[CPLL], &cru->mode, CPLL); 764 break; 765 case DCLK_VOPL: 766 con = readl(&cru->clksel_con[8]); 767 div = con & DCLK_VOPL_DIV_MASK; 768 parent = rkclk_pll_get_rate(&cru->pll[NPLL], &cru->mode, NPLL); 769 break; 770 default: 771 return -ENOENT; 772 } 773 774 return DIV_TO_RATE(parent, div); 775 } 776 777 static ulong px30_vop_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) 778 { 779 struct px30_cru *cru = priv->cru; 780 ulong npll_hz; 781 int src_clk_div; 782 783 switch (clk_id) { 784 case ACLK_VOPB: 785 case ACLK_VOPL: 786 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 787 assert(src_clk_div - 1 <= 31); 788 rk_clrsetreg(&cru->clksel_con[3], 789 ACLK_VO_PLL_MASK | ACLK_VO_DIV_MASK, 790 ACLK_VO_SEL_GPLL << ACLK_VO_PLL_SHIFT | 791 (src_clk_div - 1) << ACLK_VO_DIV_SHIFT); 792 break; 793 case DCLK_VOPB: 794 if (hz < PX30_VOP_PLL_LIMIT) { 795 src_clk_div = DIV_ROUND_UP(PX30_VOP_PLL_LIMIT, hz); 796 if (src_clk_div % 2) 797 src_clk_div = src_clk_div - 1; 798 } else { 799 src_clk_div = 1; 800 } 801 assert(src_clk_div - 1 <= 255); 802 rkclk_set_pll(&cru->pll[CPLL], &cru->mode, CPLL, hz * src_clk_div); 803 rk_clrsetreg(&cru->clksel_con[5], 804 DCLK_VOPB_SEL_MASK | DCLK_VOPB_PLL_SEL_MASK | 805 DCLK_VOPB_DIV_MASK, 806 DCLK_VOPB_SEL_DIVOUT << DCLK_VOPB_SEL_SHIFT | 807 DCLK_VOPB_PLL_SEL_CPLL << DCLK_VOPB_PLL_SEL_SHIFT | 808 (src_clk_div - 1) << DCLK_VOPB_DIV_SHIFT); 809 break; 810 case DCLK_VOPL: 811 npll_hz = px30_clk_get_pll_rate(priv, NPLL); 812 if (npll_hz >= PX30_VOP_PLL_LIMIT && npll_hz >= hz && npll_hz % hz == 0) { 813 src_clk_div = npll_hz / hz; 814 assert(src_clk_div - 1 <= 255); 815 } else { 816 if (hz < PX30_VOP_PLL_LIMIT) { 817 src_clk_div = DIV_ROUND_UP(PX30_VOP_PLL_LIMIT, hz); 818 if (src_clk_div % 2) 819 src_clk_div = src_clk_div - 1; 820 } else { 821 src_clk_div = 1; 822 } 823 assert(src_clk_div - 1 <= 255); 824 rkclk_set_pll(&cru->pll[NPLL], &cru->mode, NPLL, hz * src_clk_div); 825 } 826 rk_clrsetreg(&cru->clksel_con[8], 827 DCLK_VOPL_SEL_MASK | DCLK_VOPL_PLL_SEL_MASK | 828 DCLK_VOPL_DIV_MASK, 829 DCLK_VOPL_SEL_DIVOUT << DCLK_VOPL_SEL_SHIFT | 830 DCLK_VOPL_PLL_SEL_NPLL << DCLK_VOPL_PLL_SEL_SHIFT | 831 (src_clk_div - 1) << DCLK_VOPL_DIV_SHIFT); 832 break; 833 default: 834 printf("do not support this vop freq\n"); 835 return -EINVAL; 836 } 837 838 return px30_vop_get_clk(priv, clk_id); 839 } 840 841 static ulong px30_bus_get_clk(struct px30_clk_priv *priv, ulong clk_id) 842 { 843 struct px30_cru *cru = priv->cru; 844 u32 div, con, parent; 845 846 switch (clk_id) { 847 case ACLK_BUS_PRE: 848 con = readl(&cru->clksel_con[23]); 849 div = (con & BUS_ACLK_DIV_MASK) >> BUS_ACLK_DIV_SHIFT; 850 parent = priv->gpll_hz; 851 break; 852 case HCLK_BUS_PRE: 853 con = readl(&cru->clksel_con[24]); 854 div = (con & BUS_HCLK_DIV_MASK) >> BUS_HCLK_DIV_SHIFT; 855 parent = priv->gpll_hz; 856 break; 857 case PCLK_BUS_PRE: 858 case PCLK_WDT_NS: 859 parent = px30_bus_get_clk(priv, ACLK_BUS_PRE); 860 con = readl(&cru->clksel_con[24]); 861 div = (con & BUS_PCLK_DIV_MASK) >> BUS_PCLK_DIV_SHIFT; 862 break; 863 default: 864 return -ENOENT; 865 } 866 867 return DIV_TO_RATE(parent, div); 868 } 869 870 static ulong px30_bus_set_clk(struct px30_clk_priv *priv, ulong clk_id, 871 ulong hz) 872 { 873 struct px30_cru *cru = priv->cru; 874 int src_clk_div; 875 876 /* 877 * select gpll as pd_bus bus clock source and 878 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 879 */ 880 switch (clk_id) { 881 case ACLK_BUS_PRE: 882 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 883 assert(src_clk_div - 1 <= 31); 884 rk_clrsetreg(&cru->clksel_con[23], 885 BUS_PLL_SEL_MASK | BUS_ACLK_DIV_MASK, 886 BUS_PLL_SEL_GPLL << BUS_PLL_SEL_SHIFT | 887 (src_clk_div - 1) << BUS_ACLK_DIV_SHIFT); 888 break; 889 case HCLK_BUS_PRE: 890 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 891 assert(src_clk_div - 1 <= 31); 892 rk_clrsetreg(&cru->clksel_con[24], 893 BUS_PLL_SEL_MASK | BUS_HCLK_DIV_MASK, 894 BUS_PLL_SEL_GPLL << BUS_PLL_SEL_SHIFT | 895 (src_clk_div - 1) << BUS_HCLK_DIV_SHIFT); 896 break; 897 case PCLK_BUS_PRE: 898 src_clk_div = 899 DIV_ROUND_UP(px30_bus_get_clk(priv, ACLK_BUS_PRE), hz); 900 assert(src_clk_div - 1 <= 3); 901 rk_clrsetreg(&cru->clksel_con[24], 902 BUS_PCLK_DIV_MASK, 903 (src_clk_div - 1) << BUS_PCLK_DIV_SHIFT); 904 break; 905 default: 906 printf("do not support this bus freq\n"); 907 return -EINVAL; 908 } 909 910 return px30_bus_get_clk(priv, clk_id); 911 } 912 913 static ulong px30_peri_get_clk(struct px30_clk_priv *priv, ulong clk_id) 914 { 915 struct px30_cru *cru = priv->cru; 916 u32 div, con, parent; 917 918 switch (clk_id) { 919 case ACLK_PERI_PRE: 920 con = readl(&cru->clksel_con[14]); 921 div = (con & PERI_ACLK_DIV_MASK) >> PERI_ACLK_DIV_SHIFT; 922 parent = priv->gpll_hz; 923 break; 924 case HCLK_PERI_PRE: 925 con = readl(&cru->clksel_con[14]); 926 div = (con & PERI_HCLK_DIV_MASK) >> PERI_HCLK_DIV_SHIFT; 927 parent = priv->gpll_hz; 928 break; 929 default: 930 return -ENOENT; 931 } 932 933 return DIV_TO_RATE(parent, div); 934 } 935 936 static ulong px30_peri_set_clk(struct px30_clk_priv *priv, ulong clk_id, 937 ulong hz) 938 { 939 struct px30_cru *cru = priv->cru; 940 int src_clk_div; 941 942 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 943 assert(src_clk_div - 1 <= 31); 944 945 /* 946 * select gpll as pd_peri bus clock source and 947 * set up dependent divisors for HCLK and ACLK clocks. 948 */ 949 switch (clk_id) { 950 case ACLK_PERI_PRE: 951 rk_clrsetreg(&cru->clksel_con[14], 952 PERI_PLL_SEL_MASK | PERI_ACLK_DIV_MASK, 953 PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT | 954 (src_clk_div - 1) << PERI_ACLK_DIV_SHIFT); 955 break; 956 case HCLK_PERI_PRE: 957 rk_clrsetreg(&cru->clksel_con[14], 958 PERI_PLL_SEL_MASK | PERI_HCLK_DIV_MASK, 959 PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT | 960 (src_clk_div - 1) << PERI_HCLK_DIV_SHIFT); 961 break; 962 default: 963 printf("do not support this peri freq\n"); 964 return -EINVAL; 965 } 966 967 return px30_peri_get_clk(priv, clk_id); 968 } 969 970 #ifndef CONFIG_SPL_BUILD 971 static ulong px30_crypto_get_clk(struct px30_clk_priv *priv, ulong clk_id) 972 { 973 struct px30_cru *cru = priv->cru; 974 u32 div, con, parent; 975 976 switch (clk_id) { 977 case SCLK_CRYPTO: 978 con = readl(&cru->clksel_con[25]); 979 div = (con & CRYPTO_DIV_MASK) >> CRYPTO_DIV_SHIFT; 980 parent = priv->gpll_hz; 981 break; 982 case SCLK_CRYPTO_APK: 983 con = readl(&cru->clksel_con[25]); 984 div = (con & CRYPTO_APK_DIV_MASK) >> CRYPTO_APK_DIV_SHIFT; 985 parent = priv->gpll_hz; 986 break; 987 default: 988 return -ENOENT; 989 } 990 991 return DIV_TO_RATE(parent, div); 992 } 993 994 static ulong px30_crypto_set_clk(struct px30_clk_priv *priv, ulong clk_id, 995 ulong hz) 996 { 997 struct px30_cru *cru = priv->cru; 998 int src_clk_div; 999 1000 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 1001 assert(src_clk_div - 1 <= 31); 1002 1003 /* 1004 * select gpll as crypto clock source and 1005 * set up dependent divisors for crypto clocks. 1006 */ 1007 switch (clk_id) { 1008 case SCLK_CRYPTO: 1009 rk_clrsetreg(&cru->clksel_con[25], 1010 CRYPTO_PLL_SEL_MASK | CRYPTO_DIV_MASK, 1011 CRYPTO_PLL_SEL_GPLL << CRYPTO_PLL_SEL_SHIFT | 1012 (src_clk_div - 1) << CRYPTO_DIV_SHIFT); 1013 break; 1014 case SCLK_CRYPTO_APK: 1015 rk_clrsetreg(&cru->clksel_con[25], 1016 CRYPTO_APK_PLL_SEL_MASK | CRYPTO_APK_DIV_MASK, 1017 CRYPTO_PLL_SEL_GPLL << CRYPTO_APK_SEL_SHIFT | 1018 (src_clk_div - 1) << CRYPTO_APK_DIV_SHIFT); 1019 break; 1020 default: 1021 printf("do not support this peri freq\n"); 1022 return -EINVAL; 1023 } 1024 1025 return px30_crypto_get_clk(priv, clk_id); 1026 } 1027 1028 static ulong px30_i2s1_mclk_get_clk(struct px30_clk_priv *priv, ulong clk_id) 1029 { 1030 struct px30_cru *cru = priv->cru; 1031 u32 con; 1032 1033 con = readl(&cru->clksel_con[30]); 1034 1035 if (!(con & CLK_I2S1_OUT_SEL_MASK)) 1036 return -ENOENT; 1037 1038 return 12000000; 1039 } 1040 1041 static ulong px30_i2s1_mclk_set_clk(struct px30_clk_priv *priv, ulong clk_id, 1042 ulong hz) 1043 { 1044 struct px30_cru *cru = priv->cru; 1045 1046 if (hz != 12000000) { 1047 printf("do not support this i2s1_mclk freq\n"); 1048 return -EINVAL; 1049 } 1050 1051 rk_clrsetreg(&cru->clksel_con[30], CLK_I2S1_OUT_SEL_MASK, 1052 CLK_I2S1_OUT_SEL_OSC); 1053 rk_clrsetreg(&cru->clkgate_con[10], CLK_I2S1_OUT_MCLK_PAD_MASK, 1054 CLK_I2S1_OUT_MCLK_PAD_ENABLE); 1055 1056 return px30_i2s1_mclk_get_clk(priv, clk_id); 1057 } 1058 1059 static ulong px30_mac_set_clk(struct clk *clk, uint hz) 1060 { 1061 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 1062 struct px30_cru *cru = priv->cru; 1063 u32 con = readl(&cru->clksel_con[22]); 1064 ulong pll_rate; 1065 u8 div; 1066 1067 if ((con >> GMAC_PLL_SEL_SHIFT) & GMAC_PLL_SEL_CPLL) 1068 pll_rate = px30_clk_get_pll_rate(priv, CPLL); 1069 else if ((con >> GMAC_PLL_SEL_SHIFT) & GMAC_PLL_SEL_NPLL) 1070 pll_rate = px30_clk_get_pll_rate(priv, NPLL); 1071 else 1072 pll_rate = priv->gpll_hz; 1073 1074 /*default set 50MHZ for gmac*/ 1075 if (!hz) 1076 hz = 50000000; 1077 1078 div = DIV_ROUND_UP(pll_rate, hz) - 1; 1079 assert(div < 32); 1080 rk_clrsetreg(&cru->clksel_con[22], CLK_GMAC_DIV_MASK, 1081 div << CLK_GMAC_DIV_SHIFT); 1082 1083 return DIV_TO_RATE(pll_rate, div); 1084 } 1085 1086 static int px30_mac_set_speed_clk(struct clk *clk, uint hz) 1087 { 1088 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 1089 struct px30_cru *cru = priv->cru; 1090 1091 if (hz != 2500000 && hz != 25000000) { 1092 debug("Unsupported mac speed:%d\n", hz); 1093 return -EINVAL; 1094 } 1095 1096 rk_clrsetreg(&cru->clksel_con[23], RMII_CLK_SEL_MASK, 1097 ((hz == 2500000) ? 0 : 1) << RMII_CLK_SEL_SHIFT); 1098 1099 return 0; 1100 } 1101 1102 #endif 1103 1104 static int px30_clk_get_gpll_rate(ulong *rate) 1105 { 1106 struct udevice *pmucru_dev; 1107 struct px30_pmuclk_priv *priv; 1108 int ret; 1109 1110 ret = uclass_get_device_by_driver(UCLASS_CLK, 1111 DM_GET_DRIVER(rockchip_px30_pmucru), 1112 &pmucru_dev); 1113 if (ret) { 1114 printf("%s: could not find pmucru device\n", __func__); 1115 return ret; 1116 } 1117 priv = dev_get_priv(pmucru_dev); 1118 *rate = priv->gpll_hz; 1119 1120 return 0; 1121 } 1122 1123 static ulong px30_clk_get_pll_rate(struct px30_clk_priv *priv, 1124 enum px30_pll_id pll_id) 1125 { 1126 struct px30_cru *cru = priv->cru; 1127 1128 return rkclk_pll_get_rate(&cru->pll[pll_id], &cru->mode, pll_id); 1129 } 1130 1131 static ulong px30_clk_set_pll_rate(struct px30_clk_priv *priv, 1132 enum px30_pll_id pll_id, ulong hz) 1133 { 1134 struct px30_cru *cru = priv->cru; 1135 1136 if (rkclk_set_pll(&cru->pll[pll_id], &cru->mode, pll_id, hz)) 1137 return -EINVAL; 1138 return rkclk_pll_get_rate(&cru->pll[pll_id], &cru->mode, pll_id); 1139 } 1140 1141 static ulong px30_armclk_set_clk(struct px30_clk_priv *priv, ulong hz) 1142 { 1143 struct px30_cru *cru = priv->cru; 1144 const struct cpu_rate_table *rate; 1145 ulong old_rate; 1146 1147 rate = get_cpu_settings(hz); 1148 if (!rate) { 1149 printf("%s unsupport rate\n", __func__); 1150 return -EINVAL; 1151 } 1152 1153 /* 1154 * select apll as cpu/core clock pll source and 1155 * set up dependent divisors for PERI and ACLK clocks. 1156 * core hz : apll = 1:1 1157 */ 1158 old_rate = px30_clk_get_pll_rate(priv, APLL); 1159 if (old_rate > hz) { 1160 if (rkclk_set_pll(&cru->pll[APLL], &cru->mode, APLL, hz)) 1161 return -EINVAL; 1162 rk_clrsetreg(&cru->clksel_con[0], 1163 CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK | 1164 CORE_ACLK_DIV_MASK | CORE_DBG_DIV_MASK, 1165 rate->aclk_div << CORE_ACLK_DIV_SHIFT | 1166 rate->pclk_div << CORE_DBG_DIV_SHIFT | 1167 CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT | 1168 0 << CORE_DIV_CON_SHIFT); 1169 } else if (old_rate < hz) { 1170 rk_clrsetreg(&cru->clksel_con[0], 1171 CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK | 1172 CORE_ACLK_DIV_MASK | CORE_DBG_DIV_MASK, 1173 rate->aclk_div << CORE_ACLK_DIV_SHIFT | 1174 rate->pclk_div << CORE_DBG_DIV_SHIFT | 1175 CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT | 1176 0 << CORE_DIV_CON_SHIFT); 1177 if (rkclk_set_pll(&cru->pll[APLL], &cru->mode, APLL, hz)) 1178 return -EINVAL; 1179 } 1180 1181 return px30_clk_get_pll_rate(priv, APLL); 1182 } 1183 1184 static ulong px30_clk_get_rate(struct clk *clk) 1185 { 1186 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 1187 ulong rate = 0; 1188 1189 if (!priv->gpll_hz && clk->id > ARMCLK) { 1190 printf("%s gpll=%lu\n", __func__, priv->gpll_hz); 1191 return -ENOENT; 1192 } 1193 1194 debug("%s %ld\n", __func__, clk->id); 1195 switch (clk->id) { 1196 case PLL_APLL: 1197 rate = px30_clk_get_pll_rate(priv, APLL); 1198 break; 1199 case PLL_DPLL: 1200 rate = px30_clk_get_pll_rate(priv, DPLL); 1201 break; 1202 case PLL_CPLL: 1203 rate = px30_clk_get_pll_rate(priv, CPLL); 1204 break; 1205 case PLL_NPLL: 1206 rate = px30_clk_get_pll_rate(priv, NPLL); 1207 break; 1208 case ARMCLK: 1209 rate = px30_clk_get_pll_rate(priv, APLL); 1210 break; 1211 case HCLK_SDMMC: 1212 case HCLK_EMMC: 1213 case SCLK_SDMMC: 1214 case SCLK_EMMC: 1215 case SCLK_EMMC_SAMPLE: 1216 rate = px30_mmc_get_clk(priv, clk->id); 1217 break; 1218 case SCLK_I2C0: 1219 case SCLK_I2C1: 1220 case SCLK_I2C2: 1221 case SCLK_I2C3: 1222 rate = px30_i2c_get_clk(priv, clk->id); 1223 break; 1224 case SCLK_I2S1: 1225 rate = px30_i2s_get_clk(priv, clk->id); 1226 break; 1227 case SCLK_PWM0: 1228 case SCLK_PWM1: 1229 rate = px30_pwm_get_clk(priv, clk->id); 1230 break; 1231 case SCLK_SARADC: 1232 rate = px30_saradc_get_clk(priv); 1233 break; 1234 case SCLK_TSADC: 1235 rate = px30_tsadc_get_clk(priv); 1236 break; 1237 case SCLK_SPI0: 1238 case SCLK_SPI1: 1239 rate = px30_spi_get_clk(priv, clk->id); 1240 break; 1241 case ACLK_VOPB: 1242 case ACLK_VOPL: 1243 case DCLK_VOPB: 1244 case DCLK_VOPL: 1245 rate = px30_vop_get_clk(priv, clk->id); 1246 break; 1247 case ACLK_BUS_PRE: 1248 case HCLK_BUS_PRE: 1249 case PCLK_BUS_PRE: 1250 case PCLK_WDT_NS: 1251 rate = px30_bus_get_clk(priv, clk->id); 1252 break; 1253 case ACLK_PERI_PRE: 1254 case HCLK_PERI_PRE: 1255 rate = px30_peri_get_clk(priv, clk->id); 1256 break; 1257 #ifndef CONFIG_SPL_BUILD 1258 case SCLK_CRYPTO: 1259 case SCLK_CRYPTO_APK: 1260 rate = px30_crypto_get_clk(priv, clk->id); 1261 break; 1262 #endif 1263 default: 1264 return -ENOENT; 1265 } 1266 1267 return rate; 1268 } 1269 1270 static ulong px30_clk_set_rate(struct clk *clk, ulong rate) 1271 { 1272 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 1273 ulong ret = 0; 1274 1275 if (!priv->gpll_hz && clk->id > ARMCLK) { 1276 printf("%s gpll=%lu\n", __func__, priv->gpll_hz); 1277 return -ENOENT; 1278 } 1279 1280 debug("%s %ld %ld\n", __func__, clk->id, rate); 1281 switch (clk->id) { 1282 case PLL_NPLL: 1283 ret = px30_clk_set_pll_rate(priv, NPLL, rate); 1284 break; 1285 case ARMCLK: 1286 if (priv->armclk_hz) 1287 px30_armclk_set_clk(priv, rate); 1288 priv->armclk_hz = rate; 1289 break; 1290 case HCLK_SDMMC: 1291 case HCLK_EMMC: 1292 case SCLK_SDMMC: 1293 case SCLK_EMMC: 1294 ret = px30_mmc_set_clk(priv, clk->id, rate); 1295 break; 1296 case SCLK_I2C0: 1297 case SCLK_I2C1: 1298 case SCLK_I2C2: 1299 case SCLK_I2C3: 1300 ret = px30_i2c_set_clk(priv, clk->id, rate); 1301 break; 1302 case SCLK_I2S1: 1303 ret = px30_i2s_set_clk(priv, clk->id, rate); 1304 break; 1305 case SCLK_PWM0: 1306 case SCLK_PWM1: 1307 ret = px30_pwm_set_clk(priv, clk->id, rate); 1308 break; 1309 case SCLK_SARADC: 1310 ret = px30_saradc_set_clk(priv, rate); 1311 break; 1312 case SCLK_TSADC: 1313 ret = px30_tsadc_set_clk(priv, rate); 1314 break; 1315 case SCLK_SPI0: 1316 case SCLK_SPI1: 1317 ret = px30_spi_set_clk(priv, clk->id, rate); 1318 break; 1319 case ACLK_VOPB: 1320 case ACLK_VOPL: 1321 case DCLK_VOPB: 1322 case DCLK_VOPL: 1323 ret = px30_vop_set_clk(priv, clk->id, rate); 1324 break; 1325 case ACLK_BUS_PRE: 1326 case HCLK_BUS_PRE: 1327 case PCLK_BUS_PRE: 1328 ret = px30_bus_set_clk(priv, clk->id, rate); 1329 break; 1330 case ACLK_PERI_PRE: 1331 case HCLK_PERI_PRE: 1332 ret = px30_peri_set_clk(priv, clk->id, rate); 1333 break; 1334 #ifndef CONFIG_SPL_BUILD 1335 case SCLK_CRYPTO: 1336 case SCLK_CRYPTO_APK: 1337 ret = px30_crypto_set_clk(priv, clk->id, rate); 1338 break; 1339 case SCLK_I2S1_OUT: 1340 ret = px30_i2s1_mclk_set_clk(priv, clk->id, rate); 1341 break; 1342 case SCLK_GMAC: 1343 case SCLK_GMAC_SRC: 1344 ret = px30_mac_set_clk(clk, rate); 1345 break; 1346 case SCLK_GMAC_RMII: 1347 ret = px30_mac_set_speed_clk(clk, rate); 1348 break; 1349 #endif 1350 default: 1351 return -ENOENT; 1352 } 1353 1354 return ret; 1355 } 1356 1357 #define ROCKCHIP_MMC_DELAY_SEL BIT(10) 1358 #define ROCKCHIP_MMC_DEGREE_MASK 0x3 1359 #define ROCKCHIP_MMC_DELAYNUM_OFFSET 2 1360 #define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET) 1361 1362 #define PSECS_PER_SEC 1000000000000LL 1363 /* 1364 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to 1365 * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg. 1366 */ 1367 #define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60 1368 1369 int rockchip_mmc_get_phase(struct clk *clk) 1370 { 1371 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 1372 struct px30_cru *cru = priv->cru; 1373 u32 raw_value, delay_num; 1374 u16 degrees = 0; 1375 ulong rate; 1376 1377 rate = px30_clk_get_rate(clk); 1378 1379 if (rate < 0) 1380 return rate; 1381 1382 if (clk->id == SCLK_EMMC_SAMPLE) 1383 raw_value = readl(&cru->emmc_con[1]); 1384 else 1385 raw_value = readl(&cru->sdmmc_con[1]); 1386 1387 raw_value >>= 1; 1388 degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90; 1389 1390 if (raw_value & ROCKCHIP_MMC_DELAY_SEL) { 1391 /* degrees/delaynum * 10000 */ 1392 unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) * 1393 36 * (rate / 1000000); 1394 1395 delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK); 1396 delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET; 1397 degrees += DIV_ROUND_CLOSEST(delay_num * factor, 10000); 1398 } 1399 1400 return degrees % 360; 1401 } 1402 1403 int rockchip_mmc_set_phase(struct clk *clk, u32 degrees) 1404 { 1405 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 1406 struct px30_cru *cru = priv->cru; 1407 u8 nineties, remainder, delay_num; 1408 u32 raw_value, delay; 1409 ulong rate; 1410 1411 rate = px30_clk_get_rate(clk); 1412 1413 if (rate < 0) 1414 return rate; 1415 1416 nineties = degrees / 90; 1417 remainder = (degrees % 90); 1418 1419 /* 1420 * Convert to delay; do a little extra work to make sure we 1421 * don't overflow 32-bit / 64-bit numbers. 1422 */ 1423 delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */ 1424 delay *= remainder; 1425 delay = DIV_ROUND_CLOSEST(delay, (rate / 1000) * 36 * 1426 (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10)); 1427 1428 delay_num = (u8)min_t(u32, delay, 255); 1429 1430 raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0; 1431 raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET; 1432 raw_value |= nineties; 1433 1434 raw_value <<= 1; 1435 if (clk->id == SCLK_EMMC_SAMPLE) 1436 writel(raw_value | 0xffff0000, &cru->emmc_con[1]); 1437 else 1438 writel(raw_value | 0xffff0000, &cru->sdmmc_con[1]); 1439 1440 debug("mmc set_phase(%d) delay_nums=%u reg=%#x actual_degrees=%d\n", 1441 degrees, delay_num, raw_value, rockchip_mmc_get_phase(clk)); 1442 1443 return 0; 1444 } 1445 1446 static int px30_clk_get_phase(struct clk *clk) 1447 { 1448 int ret; 1449 1450 debug("%s %ld\n", __func__, clk->id); 1451 switch (clk->id) { 1452 case SCLK_EMMC_SAMPLE: 1453 case SCLK_SDMMC_SAMPLE: 1454 ret = rockchip_mmc_get_phase(clk); 1455 break; 1456 default: 1457 return -ENOENT; 1458 } 1459 1460 return ret; 1461 } 1462 1463 static int px30_clk_set_phase(struct clk *clk, int degrees) 1464 { 1465 int ret; 1466 1467 debug("%s %ld\n", __func__, clk->id); 1468 switch (clk->id) { 1469 case SCLK_EMMC_SAMPLE: 1470 case SCLK_SDMMC_SAMPLE: 1471 ret = rockchip_mmc_set_phase(clk, degrees); 1472 break; 1473 default: 1474 return -ENOENT; 1475 } 1476 1477 return ret; 1478 } 1479 1480 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 1481 static int px30_gmac_set_parent(struct clk *clk, struct clk *parent) 1482 { 1483 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 1484 struct px30_cru *cru = priv->cru; 1485 1486 if (parent->id == SCLK_GMAC_SRC) { 1487 debug("%s: switching GAMC to SCLK_GMAC_SRC\n", __func__); 1488 rk_clrsetreg(&cru->clksel_con[23], RMII_EXTCLK_SEL_MASK, 1489 RMII_EXTCLK_SEL_INT << RMII_EXTCLK_SEL_SHIFT); 1490 } else { 1491 debug("%s: switching GMAC to external clock\n", __func__); 1492 rk_clrsetreg(&cru->clksel_con[23], RMII_EXTCLK_SEL_MASK, 1493 RMII_EXTCLK_SEL_EXT << RMII_EXTCLK_SEL_SHIFT); 1494 } 1495 return 0; 1496 } 1497 1498 static int px30_clk_set_parent(struct clk *clk, struct clk *parent) 1499 { 1500 switch (clk->id) { 1501 case SCLK_GMAC: 1502 return px30_gmac_set_parent(clk, parent); 1503 default: 1504 return -ENOENT; 1505 } 1506 } 1507 #endif 1508 1509 static struct clk_ops px30_clk_ops = { 1510 .get_rate = px30_clk_get_rate, 1511 .set_rate = px30_clk_set_rate, 1512 .get_phase = px30_clk_get_phase, 1513 .set_phase = px30_clk_set_phase, 1514 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 1515 .set_parent = px30_clk_set_parent, 1516 #endif 1517 }; 1518 1519 static int px30_clk_probe(struct udevice *dev) 1520 { 1521 struct px30_clk_priv *priv = dev_get_priv(dev); 1522 int ret; 1523 1524 priv->sync_kernel = false; 1525 if (!priv->armclk_enter_hz) { 1526 priv->armclk_enter_hz = px30_clk_get_pll_rate(priv, APLL); 1527 priv->armclk_init_hz = priv->armclk_enter_hz; 1528 } 1529 if (px30_clk_get_pll_rate(priv, APLL) != APLL_HZ) { 1530 ret = px30_armclk_set_clk(priv, APLL_HZ); 1531 if (ret < 0) 1532 printf("%s failed to set armclk rate\n", __func__); 1533 priv->armclk_init_hz = APLL_HZ; 1534 } 1535 1536 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 1537 ret = clk_set_defaults(dev); 1538 if (ret) 1539 debug("%s clk_set_defaults failed %d\n", __func__, ret); 1540 else 1541 priv->sync_kernel = true; 1542 1543 if (!priv->gpll_hz) { 1544 ret = px30_clk_get_gpll_rate(&priv->gpll_hz); 1545 if (ret) { 1546 printf("%s failed to get gpll rate\n", __func__); 1547 return ret; 1548 } 1549 } 1550 1551 return 0; 1552 } 1553 1554 static int px30_clk_ofdata_to_platdata(struct udevice *dev) 1555 { 1556 struct px30_clk_priv *priv = dev_get_priv(dev); 1557 1558 priv->cru = dev_read_addr_ptr(dev); 1559 1560 return 0; 1561 } 1562 1563 static int px30_clk_bind(struct udevice *dev) 1564 { 1565 int ret; 1566 struct udevice *sys_child, *sf_child; 1567 struct sysreset_reg *priv; 1568 struct softreset_reg *sf_priv; 1569 1570 /* The reset driver does not have a device node, so bind it here */ 1571 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", 1572 &sys_child); 1573 if (ret) { 1574 debug("Warning: No sysreset driver: ret=%d\n", ret); 1575 } else { 1576 priv = malloc(sizeof(struct sysreset_reg)); 1577 priv->glb_srst_fst_value = offsetof(struct px30_cru, 1578 glb_srst_fst); 1579 priv->glb_srst_snd_value = offsetof(struct px30_cru, 1580 glb_srst_snd); 1581 sys_child->priv = priv; 1582 } 1583 1584 ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset", 1585 dev_ofnode(dev), &sf_child); 1586 if (ret) { 1587 debug("Warning: No rockchip reset driver: ret=%d\n", ret); 1588 } else { 1589 sf_priv = malloc(sizeof(struct softreset_reg)); 1590 sf_priv->sf_reset_offset = offsetof(struct px30_cru, 1591 softrst_con[0]); 1592 sf_priv->sf_reset_num = 12; 1593 sf_child->priv = sf_priv; 1594 } 1595 1596 return 0; 1597 } 1598 1599 static const struct udevice_id px30_clk_ids[] = { 1600 { .compatible = "rockchip,px30-cru" }, 1601 { } 1602 }; 1603 1604 U_BOOT_DRIVER(rockchip_px30_cru) = { 1605 .name = "rockchip_px30_cru", 1606 .id = UCLASS_CLK, 1607 .of_match = px30_clk_ids, 1608 .priv_auto_alloc_size = sizeof(struct px30_clk_priv), 1609 .ofdata_to_platdata = px30_clk_ofdata_to_platdata, 1610 .ops = &px30_clk_ops, 1611 .bind = px30_clk_bind, 1612 .probe = px30_clk_probe, 1613 }; 1614 1615 static ulong px30_pclk_pmu_get_pmuclk(struct px30_pmuclk_priv *priv) 1616 { 1617 struct px30_pmucru *pmucru = priv->pmucru; 1618 u32 div, con; 1619 1620 con = readl(&pmucru->pmu_clksel_con[0]); 1621 div = (con & CLK_PMU_PCLK_DIV_MASK) >> CLK_PMU_PCLK_DIV_SHIFT; 1622 1623 return DIV_TO_RATE(priv->gpll_hz, div); 1624 } 1625 1626 static ulong px30_pclk_pmu_set_pmuclk(struct px30_pmuclk_priv *priv, ulong hz) 1627 { 1628 struct px30_pmucru *pmucru = priv->pmucru; 1629 int src_clk_div; 1630 1631 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 1632 assert(src_clk_div - 1 <= 31); 1633 1634 rk_clrsetreg(&pmucru->pmu_clksel_con[0], 1635 CLK_PMU_PCLK_DIV_MASK, 1636 (src_clk_div - 1) << CLK_PMU_PCLK_DIV_SHIFT); 1637 1638 return px30_pclk_pmu_get_pmuclk(priv); 1639 } 1640 1641 static ulong px30_gpll_get_pmuclk(struct px30_pmuclk_priv *priv) 1642 { 1643 struct px30_pmucru *pmucru = priv->pmucru; 1644 1645 return rkclk_pll_get_rate(&pmucru->pll, &pmucru->pmu_mode, GPLL); 1646 } 1647 1648 static ulong px30_gpll_set_pmuclk(struct px30_pmuclk_priv *priv, ulong hz) 1649 { 1650 struct udevice *cru_dev; 1651 struct px30_clk_priv *cru_priv; 1652 struct px30_pmucru *pmucru = priv->pmucru; 1653 u32 div; 1654 ulong emmc_rate, sdmmc_rate, nandc_rate; 1655 ulong aclk_bus_rate, hclk_bus_rate, pclk_bus_rate; 1656 ulong aclk_peri_rate, hclk_peri_rate, pclk_pmu_rate; 1657 int ret; 1658 1659 ret = uclass_get_device_by_name(UCLASS_CLK, 1660 "clock-controller@ff2b0000", 1661 &cru_dev); 1662 if (ret) { 1663 printf("%s failed to get cru device\n", __func__); 1664 return ret; 1665 } 1666 cru_priv = dev_get_priv(cru_dev); 1667 1668 if (priv->gpll_hz == hz) 1669 return priv->gpll_hz; 1670 1671 cru_priv->gpll_hz = priv->gpll_hz; 1672 div = DIV_ROUND_UP(hz, priv->gpll_hz); 1673 1674 /* save clock rate */ 1675 aclk_bus_rate = px30_bus_get_clk(cru_priv, ACLK_BUS_PRE); 1676 hclk_bus_rate = px30_bus_get_clk(cru_priv, HCLK_BUS_PRE); 1677 pclk_bus_rate = px30_bus_get_clk(cru_priv, PCLK_BUS_PRE); 1678 aclk_peri_rate = px30_peri_get_clk(cru_priv, ACLK_PERI_PRE); 1679 hclk_peri_rate = px30_peri_get_clk(cru_priv, HCLK_PERI_PRE); 1680 pclk_pmu_rate = px30_pclk_pmu_get_pmuclk(priv); 1681 debug("%s aclk_bus=%lu, hclk_bus=%lu, pclk_bus=%lu\n", __func__, 1682 aclk_bus_rate, hclk_bus_rate, pclk_bus_rate); 1683 debug("%s aclk_peri=%lu, hclk_peri=%lu, pclk_pmu=%lu\n", __func__, 1684 aclk_peri_rate, hclk_peri_rate, pclk_pmu_rate); 1685 emmc_rate = px30_mmc_get_clk(cru_priv, SCLK_EMMC); 1686 sdmmc_rate = px30_mmc_get_clk(cru_priv, SCLK_SDMMC); 1687 nandc_rate = px30_nandc_get_clk(cru_priv); 1688 debug("%s emmc=%lu, sdmmc=%lu, nandc=%lu\n", __func__, 1689 emmc_rate, sdmmc_rate, nandc_rate); 1690 1691 /* avoid rate too large, reduce rate first */ 1692 px30_bus_set_clk(cru_priv, ACLK_BUS_PRE, aclk_bus_rate / div); 1693 px30_bus_set_clk(cru_priv, HCLK_BUS_PRE, hclk_bus_rate / div); 1694 px30_bus_set_clk(cru_priv, PCLK_BUS_PRE, pclk_bus_rate / div); 1695 px30_peri_set_clk(cru_priv, ACLK_PERI_PRE, aclk_peri_rate / div); 1696 px30_peri_set_clk(cru_priv, HCLK_PERI_PRE, hclk_peri_rate / div); 1697 px30_pclk_pmu_set_pmuclk(priv, pclk_pmu_rate / div); 1698 1699 px30_mmc_set_clk(cru_priv, SCLK_EMMC, emmc_rate / div); 1700 px30_mmc_set_clk(cru_priv, SCLK_SDMMC, sdmmc_rate / div); 1701 px30_nandc_set_clk(cru_priv, nandc_rate / div); 1702 1703 /* change gpll rate */ 1704 rkclk_set_pll(&pmucru->pll, &pmucru->pmu_mode, GPLL, hz); 1705 priv->gpll_hz = px30_gpll_get_pmuclk(priv); 1706 cru_priv->gpll_hz = priv->gpll_hz; 1707 1708 /* restore clock rate */ 1709 px30_bus_set_clk(cru_priv, ACLK_BUS_PRE, aclk_bus_rate); 1710 px30_bus_set_clk(cru_priv, HCLK_BUS_PRE, hclk_bus_rate); 1711 px30_bus_set_clk(cru_priv, PCLK_BUS_PRE, pclk_bus_rate); 1712 px30_peri_set_clk(cru_priv, ACLK_PERI_PRE, aclk_peri_rate); 1713 px30_peri_set_clk(cru_priv, HCLK_PERI_PRE, hclk_peri_rate); 1714 px30_pclk_pmu_set_pmuclk(priv, pclk_pmu_rate); 1715 1716 px30_mmc_set_clk(cru_priv, SCLK_EMMC, emmc_rate); 1717 px30_mmc_set_clk(cru_priv, SCLK_SDMMC, sdmmc_rate); 1718 px30_nandc_set_clk(cru_priv, nandc_rate); 1719 1720 return priv->gpll_hz; 1721 } 1722 1723 static ulong px30_pmuclk_get_rate(struct clk *clk) 1724 { 1725 struct px30_pmuclk_priv *priv = dev_get_priv(clk->dev); 1726 ulong rate = 0; 1727 1728 debug("%s %ld\n", __func__, clk->id); 1729 switch (clk->id) { 1730 case PLL_GPLL: 1731 rate = px30_gpll_get_pmuclk(priv); 1732 break; 1733 case PCLK_PMU_PRE: 1734 rate = px30_pclk_pmu_get_pmuclk(priv); 1735 break; 1736 default: 1737 return -ENOENT; 1738 } 1739 1740 return rate; 1741 } 1742 1743 static ulong px30_pmuclk_set_rate(struct clk *clk, ulong rate) 1744 { 1745 struct px30_pmuclk_priv *priv = dev_get_priv(clk->dev); 1746 ulong ret = 0; 1747 1748 debug("%s %ld %ld\n", __func__, clk->id, rate); 1749 switch (clk->id) { 1750 case PLL_GPLL: 1751 ret = px30_gpll_set_pmuclk(priv, rate); 1752 break; 1753 case PCLK_PMU_PRE: 1754 ret = px30_pclk_pmu_set_pmuclk(priv, rate); 1755 break; 1756 default: 1757 return -ENOENT; 1758 } 1759 1760 return ret; 1761 } 1762 1763 static struct clk_ops px30_pmuclk_ops = { 1764 .get_rate = px30_pmuclk_get_rate, 1765 .set_rate = px30_pmuclk_set_rate, 1766 }; 1767 1768 static void px30_clk_init(struct px30_pmuclk_priv *priv) 1769 { 1770 struct udevice *cru_dev; 1771 struct px30_clk_priv *cru_priv; 1772 ulong npll_hz; 1773 int ret; 1774 1775 priv->gpll_hz = px30_gpll_get_pmuclk(priv); 1776 if (priv->gpll_hz != GPLL_HZ) { 1777 ret = px30_gpll_set_pmuclk(priv, GPLL_HZ); 1778 if (ret < 0) 1779 printf("%s failed to set gpll rate\n", __func__); 1780 } 1781 1782 ret = uclass_get_device_by_name(UCLASS_CLK, 1783 "clock-controller@ff2b0000", 1784 &cru_dev); 1785 if (ret) { 1786 printf("%s failed to get cru device\n", __func__); 1787 return; 1788 } 1789 cru_priv = dev_get_priv(cru_dev); 1790 cru_priv->gpll_hz = priv->gpll_hz; 1791 1792 npll_hz = px30_clk_get_pll_rate(cru_priv, NPLL); 1793 if (npll_hz != NPLL_HZ) { 1794 ret = px30_clk_set_pll_rate(cru_priv, NPLL, NPLL_HZ); 1795 if (ret < 0) 1796 printf("%s failed to set npll rate\n", __func__); 1797 } 1798 1799 px30_bus_set_clk(cru_priv, ACLK_BUS_PRE, ACLK_BUS_HZ); 1800 px30_bus_set_clk(cru_priv, HCLK_BUS_PRE, HCLK_BUS_HZ); 1801 px30_bus_set_clk(cru_priv, PCLK_BUS_PRE, PCLK_BUS_HZ); 1802 px30_peri_set_clk(cru_priv, ACLK_PERI_PRE, ACLK_PERI_HZ); 1803 px30_peri_set_clk(cru_priv, HCLK_PERI_PRE, HCLK_PERI_HZ); 1804 px30_pclk_pmu_set_pmuclk(priv, PCLK_PMU_HZ); 1805 } 1806 1807 static int px30_pmuclk_probe(struct udevice *dev) 1808 { 1809 struct px30_pmuclk_priv *priv = dev_get_priv(dev); 1810 int ret; 1811 1812 px30_clk_init(priv); 1813 1814 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 1815 ret = clk_set_defaults(dev); 1816 if (ret) 1817 debug("%s clk_set_defaults failed %d\n", __func__, ret); 1818 1819 return 0; 1820 } 1821 1822 static int px30_pmuclk_ofdata_to_platdata(struct udevice *dev) 1823 { 1824 struct px30_pmuclk_priv *priv = dev_get_priv(dev); 1825 1826 priv->pmucru = dev_read_addr_ptr(dev); 1827 1828 return 0; 1829 } 1830 1831 static const struct udevice_id px30_pmuclk_ids[] = { 1832 { .compatible = "rockchip,px30-pmucru" }, 1833 { } 1834 }; 1835 1836 U_BOOT_DRIVER(rockchip_px30_pmucru) = { 1837 .name = "rockchip_px30_pmucru", 1838 .id = UCLASS_CLK, 1839 .of_match = px30_pmuclk_ids, 1840 .priv_auto_alloc_size = sizeof(struct px30_pmuclk_priv), 1841 .ofdata_to_platdata = px30_pmuclk_ofdata_to_platdata, 1842 .ops = &px30_pmuclk_ops, 1843 .probe = px30_pmuclk_probe, 1844 }; 1845 1846 /** 1847 * soc_clk_dump() - Print clock frequencies 1848 * Returns zero on success 1849 * 1850 * Implementation for the clk dump command. 1851 */ 1852 int soc_clk_dump(void) 1853 { 1854 struct udevice *cru_dev, *pmucru_dev; 1855 struct px30_clk_priv *priv; 1856 const struct px30_clk_info *clk_dump; 1857 struct clk clk; 1858 unsigned long clk_count = ARRAY_SIZE(clks_dump); 1859 unsigned long rate; 1860 int i, ret; 1861 1862 ret = uclass_get_device_by_driver(UCLASS_CLK, 1863 DM_GET_DRIVER(rockchip_px30_cru), 1864 &cru_dev); 1865 if (ret) { 1866 printf("%s failed to get cru device\n", __func__); 1867 return ret; 1868 } 1869 1870 ret = uclass_get_device_by_driver(UCLASS_CLK, 1871 DM_GET_DRIVER(rockchip_px30_pmucru), 1872 &pmucru_dev); 1873 if (ret) { 1874 printf("%s failed to get pmucru device\n", __func__); 1875 return ret; 1876 } 1877 1878 priv = dev_get_priv(cru_dev); 1879 printf("CLK: (%s. arm: enter %lu KHz, init %lu KHz, kernel %lu%s)\n", 1880 priv->sync_kernel ? "sync kernel" : "uboot", 1881 priv->armclk_enter_hz / 1000, 1882 priv->armclk_init_hz / 1000, 1883 priv->set_armclk_rate ? priv->armclk_hz / 1000 : 0, 1884 priv->set_armclk_rate ? " KHz" : "N/A"); 1885 for (i = 0; i < clk_count; i++) { 1886 clk_dump = &clks_dump[i]; 1887 if (clk_dump->name) { 1888 clk.id = clk_dump->id; 1889 if (clk_dump->is_cru) 1890 ret = clk_request(cru_dev, &clk); 1891 else 1892 ret = clk_request(pmucru_dev, &clk); 1893 if (ret < 0) 1894 return ret; 1895 1896 rate = clk_get_rate(&clk); 1897 clk_free(&clk); 1898 if (i == 0) { 1899 if (rate < 0) 1900 printf(" %s %s\n", clk_dump->name, 1901 "unknown"); 1902 else 1903 printf(" %s %lu KHz\n", clk_dump->name, 1904 rate / 1000); 1905 } else { 1906 if (rate < 0) 1907 printf(" %s %s\n", clk_dump->name, 1908 "unknown"); 1909 else 1910 printf(" %s %lu KHz\n", clk_dump->name, 1911 rate / 1000); 1912 } 1913 } 1914 } 1915 1916 return 0; 1917 } 1918