1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <bitfield.h> 9 #include <clk-uclass.h> 10 #include <dm.h> 11 #include <errno.h> 12 #include <syscon.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch/cru_px30.h> 15 #include <asm/arch/hardware.h> 16 #include <asm/io.h> 17 #include <dm/lists.h> 18 #include <dt-bindings/clock/px30-cru.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 enum { 23 VCO_MAX_HZ = 3200U * 1000000, 24 VCO_MIN_HZ = 800 * 1000000, 25 OUTPUT_MAX_HZ = 3200U * 1000000, 26 OUTPUT_MIN_HZ = 24 * 1000000, 27 }; 28 29 #define PX30_VOP_PLL_LIMIT 600000000 30 31 #define PX30_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ 32 _postdiv2, _dsmpd, _frac) \ 33 { \ 34 .rate = _rate##U, \ 35 .fbdiv = _fbdiv, \ 36 .postdiv1 = _postdiv1, \ 37 .refdiv = _refdiv, \ 38 .postdiv2 = _postdiv2, \ 39 .dsmpd = _dsmpd, \ 40 .frac = _frac, \ 41 } 42 43 #define PX30_CPUCLK_RATE(_rate, _aclk_div, _pclk_div) \ 44 { \ 45 .rate = _rate##U, \ 46 .aclk_div = _aclk_div, \ 47 .pclk_div = _pclk_div, \ 48 } 49 50 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 51 52 #define PX30_CLK_DUMP(_id, _name, _iscru) \ 53 { \ 54 .id = _id, \ 55 .name = _name, \ 56 .is_cru = _iscru, \ 57 } 58 59 static struct pll_rate_table px30_pll_rates[] = { 60 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 61 PX30_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), 62 PX30_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), 63 PX30_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), 64 PX30_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 65 PX30_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), 66 PX30_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), 67 PX30_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0), 68 }; 69 70 static const struct px30_clk_info clks_dump[] = { 71 PX30_CLK_DUMP(PLL_APLL, "apll", true), 72 PX30_CLK_DUMP(PLL_DPLL, "dpll", true), 73 PX30_CLK_DUMP(PLL_CPLL, "cpll", true), 74 PX30_CLK_DUMP(PLL_NPLL, "npll", true), 75 PX30_CLK_DUMP(PLL_GPLL, "gpll", false), 76 PX30_CLK_DUMP(ACLK_BUS_PRE, "aclk_bus", true), 77 PX30_CLK_DUMP(HCLK_BUS_PRE, "hclk_bus", true), 78 PX30_CLK_DUMP(PCLK_BUS_PRE, "pclk_bus", true), 79 PX30_CLK_DUMP(ACLK_PERI_PRE, "aclk_peri", true), 80 PX30_CLK_DUMP(HCLK_PERI_PRE, "hclk_peri", true), 81 PX30_CLK_DUMP(PCLK_PMU_PRE, "pclk_pmu", false), 82 }; 83 84 static struct cpu_rate_table px30_cpu_rates[] = { 85 PX30_CPUCLK_RATE(1200000000, 1, 5), 86 PX30_CPUCLK_RATE(1008000000, 1, 5), 87 PX30_CPUCLK_RATE(816000000, 1, 3), 88 PX30_CPUCLK_RATE(600000000, 1, 3), 89 }; 90 91 static u8 pll_mode_shift[PLL_COUNT] = { 92 APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, 93 NPLL_MODE_SHIFT, GPLL_MODE_SHIFT 94 }; 95 static u32 pll_mode_mask[PLL_COUNT] = { 96 APLL_MODE_MASK, DPLL_MODE_MASK, CPLL_MODE_MASK, 97 NPLL_MODE_MASK, GPLL_MODE_MASK 98 }; 99 100 static struct pll_rate_table auto_table; 101 102 static ulong px30_clk_get_pll_rate(struct px30_clk_priv *priv, 103 enum px30_pll_id pll_id); 104 105 static struct pll_rate_table *pll_clk_set_by_auto(u32 drate) 106 { 107 struct pll_rate_table *rate = &auto_table; 108 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; 109 u32 postdiv1, postdiv2 = 1; 110 u32 fref_khz; 111 u32 diff_khz, best_diff_khz; 112 const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16; 113 const u32 max_postdiv1 = 7, max_postdiv2 = 7; 114 u32 vco_khz; 115 u32 rate_khz = drate / KHz; 116 117 if (!drate) { 118 printf("%s: the frequency can't be 0 Hz\n", __func__); 119 return NULL; 120 } 121 122 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, rate_khz); 123 if (postdiv1 > max_postdiv1) { 124 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); 125 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); 126 } 127 128 vco_khz = rate_khz * postdiv1 * postdiv2; 129 130 if (vco_khz < (VCO_MIN_HZ / KHz) || vco_khz > (VCO_MAX_HZ / KHz) || 131 postdiv2 > max_postdiv2) { 132 printf("%s: Cannot find out a supported VCO for Freq (%uHz)\n", 133 __func__, rate_khz); 134 return NULL; 135 } 136 137 rate->postdiv1 = postdiv1; 138 rate->postdiv2 = postdiv2; 139 140 best_diff_khz = vco_khz; 141 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { 142 fref_khz = ref_khz / refdiv; 143 144 fbdiv = vco_khz / fref_khz; 145 if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv)) 146 continue; 147 diff_khz = vco_khz - fbdiv * fref_khz; 148 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) { 149 fbdiv++; 150 diff_khz = fref_khz - diff_khz; 151 } 152 153 if (diff_khz >= best_diff_khz) 154 continue; 155 156 best_diff_khz = diff_khz; 157 rate->refdiv = refdiv; 158 rate->fbdiv = fbdiv; 159 } 160 161 if (best_diff_khz > 4 * (MHz / KHz)) { 162 printf("%s: Failed to match output frequency %u bestis %u Hz\n", 163 __func__, rate_khz, 164 best_diff_khz * KHz); 165 return NULL; 166 } 167 168 return rate; 169 } 170 171 static const struct pll_rate_table *get_pll_settings(unsigned long rate) 172 { 173 unsigned int rate_count = ARRAY_SIZE(px30_pll_rates); 174 int i; 175 176 for (i = 0; i < rate_count; i++) { 177 if (rate == px30_pll_rates[i].rate) 178 return &px30_pll_rates[i]; 179 } 180 181 return pll_clk_set_by_auto(rate); 182 } 183 184 static const struct cpu_rate_table *get_cpu_settings(unsigned long rate) 185 { 186 unsigned int rate_count = ARRAY_SIZE(px30_cpu_rates); 187 int i; 188 189 for (i = 0; i < rate_count; i++) { 190 if (rate == px30_cpu_rates[i].rate) 191 return &px30_cpu_rates[i]; 192 } 193 194 return NULL; 195 } 196 197 /* 198 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63): 199 * Formulas also embedded within the Fractional PLL Verilog model: 200 * If DSMPD = 1 (DSM is disabled, "integer mode") 201 * FOUTVCO = FREF / REFDIV * FBDIV 202 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 203 * Where: 204 * FOUTVCO = Fractional PLL non-divided output frequency 205 * FOUTPOSTDIV = Fractional PLL divided output frequency 206 * (output of second post divider) 207 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input) 208 * REFDIV = Fractional PLL input reference clock divider 209 * FBDIV = Integer value programmed into feedback divide 210 * 211 */ 212 static int rkclk_set_pll(struct px30_pll *pll, unsigned int *mode, 213 enum px30_pll_id pll_id, 214 unsigned long drate) 215 { 216 const struct pll_rate_table *rate; 217 uint vco_hz, output_hz; 218 219 rate = get_pll_settings(drate); 220 if (!rate) { 221 printf("%s unsupport rate\n", __func__); 222 return -EINVAL; 223 } 224 225 /* All PLLs have same VCO and output frequency range restrictions. */ 226 vco_hz = OSC_HZ / 1000 * rate->fbdiv / rate->refdiv * 1000; 227 output_hz = vco_hz / rate->postdiv1 / rate->postdiv2; 228 229 debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n", 230 pll, rate->fbdiv, rate->refdiv, rate->postdiv1, 231 rate->postdiv2, vco_hz, output_hz); 232 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && 233 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ); 234 235 /* 236 * When power on or changing PLL setting, 237 * we must force PLL into slow mode to ensure output stable clock. 238 */ 239 rk_clrsetreg(mode, pll_mode_mask[pll_id], 240 PLLMUX_FROM_XIN24M << pll_mode_shift[pll_id]); 241 242 /* use integer mode */ 243 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); 244 /* Power down */ 245 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); 246 247 rk_clrsetreg(&pll->con0, 248 PLL_POSTDIV1_MASK | PLL_FBDIV_MASK, 249 (rate->postdiv1 << PLL_POSTDIV1_SHIFT) | rate->fbdiv); 250 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, 251 (rate->postdiv2 << PLL_POSTDIV2_SHIFT | 252 rate->refdiv << PLL_REFDIV_SHIFT)); 253 254 /* Power Up */ 255 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); 256 257 /* waiting for pll lock */ 258 while (!(readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))) 259 udelay(1); 260 261 rk_clrsetreg(mode, pll_mode_mask[pll_id], 262 PLLMUX_FROM_PLL << pll_mode_shift[pll_id]); 263 264 return 0; 265 } 266 267 static uint32_t rkclk_pll_get_rate(struct px30_pll *pll, unsigned int *mode, 268 enum px30_pll_id pll_id) 269 { 270 u32 refdiv, fbdiv, postdiv1, postdiv2; 271 u32 con, shift, mask; 272 273 con = readl(mode); 274 shift = pll_mode_shift[pll_id]; 275 mask = pll_mode_mask[pll_id]; 276 277 switch ((con & mask) >> shift) { 278 case PLLMUX_FROM_XIN24M: 279 return OSC_HZ; 280 case PLLMUX_FROM_PLL: 281 /* normal mode */ 282 con = readl(&pll->con0); 283 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; 284 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; 285 con = readl(&pll->con1); 286 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; 287 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; 288 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; 289 case PLLMUX_FROM_RTC32K: 290 default: 291 return 32768; 292 } 293 } 294 295 static ulong px30_i2c_get_clk(struct px30_clk_priv *priv, ulong clk_id) 296 { 297 struct px30_cru *cru = priv->cru; 298 u32 div, con; 299 300 switch (clk_id) { 301 case SCLK_I2C0: 302 con = readl(&cru->clksel_con[49]); 303 div = con >> CLK_I2C0_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; 304 break; 305 case SCLK_I2C1: 306 con = readl(&cru->clksel_con[49]); 307 div = con >> CLK_I2C1_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; 308 break; 309 case SCLK_I2C2: 310 con = readl(&cru->clksel_con[50]); 311 div = con >> CLK_I2C2_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; 312 break; 313 case SCLK_I2C3: 314 con = readl(&cru->clksel_con[50]); 315 div = con >> CLK_I2C3_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; 316 break; 317 default: 318 printf("do not support this i2c bus\n"); 319 return -EINVAL; 320 } 321 322 return DIV_TO_RATE(priv->gpll_hz, div); 323 } 324 325 static ulong px30_i2c_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) 326 { 327 struct px30_cru *cru = priv->cru; 328 int src_clk_div; 329 330 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 331 assert(src_clk_div - 1 <= 127); 332 333 switch (clk_id) { 334 case SCLK_I2C0: 335 rk_clrsetreg(&cru->clksel_con[49], 336 CLK_I2C_DIV_CON_MASK << CLK_I2C0_DIV_CON_SHIFT | 337 CLK_I2C_PLL_SEL_MASK << CLK_I2C0_PLL_SEL_SHIFT, 338 (src_clk_div - 1) << CLK_I2C0_DIV_CON_SHIFT | 339 CLK_I2C_PLL_SEL_GPLL << CLK_I2C0_PLL_SEL_SHIFT); 340 break; 341 case SCLK_I2C1: 342 rk_clrsetreg(&cru->clksel_con[49], 343 CLK_I2C_DIV_CON_MASK << CLK_I2C1_DIV_CON_SHIFT | 344 CLK_I2C_PLL_SEL_MASK << CLK_I2C1_PLL_SEL_SHIFT, 345 (src_clk_div - 1) << CLK_I2C1_DIV_CON_SHIFT | 346 CLK_I2C_PLL_SEL_GPLL << CLK_I2C1_PLL_SEL_SHIFT); 347 break; 348 case SCLK_I2C2: 349 rk_clrsetreg(&cru->clksel_con[50], 350 CLK_I2C_DIV_CON_MASK << CLK_I2C2_DIV_CON_SHIFT | 351 CLK_I2C_PLL_SEL_MASK << CLK_I2C2_PLL_SEL_SHIFT, 352 (src_clk_div - 1) << CLK_I2C2_DIV_CON_SHIFT | 353 CLK_I2C_PLL_SEL_GPLL << CLK_I2C2_PLL_SEL_SHIFT); 354 break; 355 case SCLK_I2C3: 356 rk_clrsetreg(&cru->clksel_con[50], 357 CLK_I2C_DIV_CON_MASK << CLK_I2C3_DIV_CON_SHIFT | 358 CLK_I2C_PLL_SEL_MASK << CLK_I2C3_PLL_SEL_SHIFT, 359 (src_clk_div - 1) << CLK_I2C3_DIV_CON_SHIFT | 360 CLK_I2C_PLL_SEL_GPLL << CLK_I2C3_PLL_SEL_SHIFT); 361 break; 362 default: 363 printf("do not support this i2c bus\n"); 364 return -EINVAL; 365 } 366 367 return px30_i2c_get_clk(priv, clk_id); 368 } 369 370 /* 371 * calculate best rational approximation for a given fraction 372 * taking into account restricted register size, e.g. to find 373 * appropriate values for a pll with 5 bit denominator and 374 * 8 bit numerator register fields, trying to set up with a 375 * frequency ratio of 3.1415, one would say: 376 * 377 * rational_best_approximation(31415, 10000, 378 * (1 << 8) - 1, (1 << 5) - 1, &n, &d); 379 * 380 * you may look at given_numerator as a fixed point number, 381 * with the fractional part size described in given_denominator. 382 * 383 * for theoretical background, see: 384 * http://en.wikipedia.org/wiki/Continued_fraction 385 */ 386 static void rational_best_approximation( 387 unsigned long given_numerator, unsigned long given_denominator, 388 unsigned long max_numerator, unsigned long max_denominator, 389 unsigned long *best_numerator, unsigned long *best_denominator) 390 { 391 unsigned long n, d, n0, d0, n1, d1; 392 393 n = given_numerator; 394 d = given_denominator; 395 n0 = 0; 396 d1 = 0; 397 n1 = 1; 398 d0 = 1; 399 for (;;) { 400 unsigned long t, a; 401 402 if (n1 > max_numerator || d1 > max_denominator) { 403 n1 = n0; 404 d1 = d0; 405 break; 406 } 407 if (d == 0) 408 break; 409 t = d; 410 a = n / d; 411 d = n % d; 412 n = t; 413 t = n0 + a * n1; 414 n0 = n1; 415 n1 = t; 416 t = d0 + a * d1; 417 d0 = d1; 418 d1 = t; 419 } 420 *best_numerator = n1; 421 *best_denominator = d1; 422 } 423 424 static ulong px30_i2s_get_clk(struct px30_clk_priv *priv, ulong clk_id) 425 { 426 u32 con, fracdiv, gate; 427 u32 clk_src = GPLL_HZ / 2; 428 unsigned long m, n; 429 struct px30_cru *cru = priv->cru; 430 431 switch (clk_id) { 432 case SCLK_I2S1: 433 con = readl(&cru->clksel_con[30]); 434 fracdiv = readl(&cru->clksel_con[31]); 435 gate = readl(&cru->clkgate_con[10]); 436 m = fracdiv & CLK_I2S1_FRAC_NUMERATOR_MASK; 437 m >>= CLK_I2S1_FRAC_NUMERATOR_SHIFT; 438 n = fracdiv & CLK_I2S1_FRAC_DENOMINATOR_MASK; 439 n >>= CLK_I2S1_FRAC_DENOMINATOR_SHIFT; 440 debug("con30: 0x%x, gate: 0x%x, frac: 0x%x\n", 441 con, gate, fracdiv); 442 break; 443 default: 444 printf("do not support this i2s bus\n"); 445 return -EINVAL; 446 } 447 448 return clk_src * n / m; 449 } 450 451 static ulong px30_i2s_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) 452 { 453 u32 clk_src; 454 unsigned long m, n, val; 455 struct px30_cru *cru = priv->cru; 456 457 clk_src = GPLL_HZ / 2; 458 rational_best_approximation(hz, clk_src, 459 GENMASK(16 - 1, 0), 460 GENMASK(16 - 1, 0), 461 &m, &n); 462 switch (clk_id) { 463 case SCLK_I2S1: 464 rk_clrsetreg(&cru->clksel_con[30], 465 CLK_I2S1_PLL_SEL_MASK, CLK_I2S1_PLL_SEL_GPLL); 466 rk_clrsetreg(&cru->clksel_con[30], 467 CLK_I2S1_DIV_CON_MASK, 0x1); 468 rk_clrsetreg(&cru->clksel_con[30], 469 CLK_I2S1_SEL_MASK, CLK_I2S1_SEL_FRAC); 470 val = m << CLK_I2S1_FRAC_NUMERATOR_SHIFT | n; 471 writel(val, &cru->clksel_con[31]); 472 rk_clrsetreg(&cru->clkgate_con[10], 473 CLK_I2S1_OUT_MCLK_PAD_MASK, 474 CLK_I2S1_OUT_MCLK_PAD_ENABLE); 475 break; 476 default: 477 printf("do not support this i2s bus\n"); 478 return -EINVAL; 479 } 480 481 return px30_i2s_get_clk(priv, clk_id); 482 } 483 484 static ulong px30_nandc_get_clk(struct px30_clk_priv *priv) 485 { 486 struct px30_cru *cru = priv->cru; 487 u32 div, con; 488 489 con = readl(&cru->clksel_con[15]); 490 div = (con & NANDC_DIV_MASK) >> NANDC_DIV_SHIFT; 491 492 return DIV_TO_RATE(priv->gpll_hz, div); 493 } 494 495 static ulong px30_nandc_set_clk(struct px30_clk_priv *priv, 496 ulong set_rate) 497 { 498 struct px30_cru *cru = priv->cru; 499 int src_clk_div; 500 501 /* Select nandc source from GPLL by default */ 502 /* nandc clock defaulg div 2 internal, need provide double in cru */ 503 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, set_rate); 504 assert(src_clk_div - 1 <= 31); 505 506 rk_clrsetreg(&cru->clksel_con[15], 507 NANDC_CLK_SEL_MASK | NANDC_PLL_MASK | 508 NANDC_DIV_MASK, 509 NANDC_CLK_SEL_NANDC << NANDC_CLK_SEL_SHIFT | 510 NANDC_SEL_GPLL << NANDC_PLL_SHIFT | 511 (src_clk_div - 1) << NANDC_DIV_SHIFT); 512 513 return px30_nandc_get_clk(priv); 514 } 515 516 static ulong px30_mmc_get_clk(struct px30_clk_priv *priv, uint clk_id) 517 { 518 struct px30_cru *cru = priv->cru; 519 u32 div, con, con_id; 520 521 switch (clk_id) { 522 case HCLK_SDMMC: 523 case SCLK_SDMMC: 524 con_id = 16; 525 break; 526 case HCLK_EMMC: 527 case SCLK_EMMC: 528 case SCLK_EMMC_SAMPLE: 529 con_id = 20; 530 break; 531 default: 532 return -EINVAL; 533 } 534 535 con = readl(&cru->clksel_con[con_id]); 536 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; 537 538 if ((con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT 539 == EMMC_SEL_24M) 540 return DIV_TO_RATE(OSC_HZ, div) / 2; 541 else 542 return DIV_TO_RATE(priv->gpll_hz, div) / 2; 543 544 } 545 546 static ulong px30_mmc_set_clk(struct px30_clk_priv *priv, 547 ulong clk_id, ulong set_rate) 548 { 549 struct px30_cru *cru = priv->cru; 550 int src_clk_div; 551 u32 con_id; 552 553 switch (clk_id) { 554 case HCLK_SDMMC: 555 case SCLK_SDMMC: 556 con_id = 16; 557 break; 558 case HCLK_EMMC: 559 case SCLK_EMMC: 560 con_id = 20; 561 break; 562 default: 563 return -EINVAL; 564 } 565 566 /* Select clk_sdmmc/emmc source from GPLL by default */ 567 /* mmc clock defaulg div 2 internal, need provide double in cru */ 568 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, set_rate); 569 570 if (src_clk_div > 127) { 571 /* use 24MHz source for 400KHz clock */ 572 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); 573 rk_clrsetreg(&cru->clksel_con[con_id], 574 EMMC_PLL_MASK | EMMC_DIV_MASK, 575 EMMC_SEL_24M << EMMC_PLL_SHIFT | 576 (src_clk_div - 1) << EMMC_DIV_SHIFT); 577 } else { 578 rk_clrsetreg(&cru->clksel_con[con_id], 579 EMMC_PLL_MASK | EMMC_DIV_MASK, 580 EMMC_SEL_GPLL << EMMC_PLL_SHIFT | 581 (src_clk_div - 1) << EMMC_DIV_SHIFT); 582 } 583 rk_clrsetreg(&cru->clksel_con[con_id +1], EMMC_CLK_SEL_MASK, 584 EMMC_CLK_SEL_EMMC); 585 586 return px30_mmc_get_clk(priv, clk_id); 587 } 588 589 static ulong px30_pwm_get_clk(struct px30_clk_priv *priv, ulong clk_id) 590 { 591 struct px30_cru *cru = priv->cru; 592 u32 div, con; 593 594 switch (clk_id) { 595 case SCLK_PWM0: 596 con = readl(&cru->clksel_con[52]); 597 div = con >> CLK_PWM0_DIV_CON_SHIFT & CLK_PWM_DIV_CON_MASK; 598 break; 599 case SCLK_PWM1: 600 con = readl(&cru->clksel_con[52]); 601 div = con >> CLK_PWM1_DIV_CON_SHIFT & CLK_PWM_DIV_CON_MASK; 602 break; 603 default: 604 printf("do not support this pwm bus\n"); 605 return -EINVAL; 606 } 607 608 return DIV_TO_RATE(priv->gpll_hz, div); 609 } 610 611 static ulong px30_pwm_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) 612 { 613 struct px30_cru *cru = priv->cru; 614 int src_clk_div; 615 616 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 617 assert(src_clk_div - 1 <= 127); 618 619 switch (clk_id) { 620 case SCLK_PWM0: 621 rk_clrsetreg(&cru->clksel_con[52], 622 CLK_PWM_DIV_CON_MASK << CLK_PWM0_DIV_CON_SHIFT | 623 CLK_PWM_PLL_SEL_MASK << CLK_PWM0_PLL_SEL_SHIFT, 624 (src_clk_div - 1) << CLK_PWM0_DIV_CON_SHIFT | 625 CLK_PWM_PLL_SEL_GPLL << CLK_PWM0_PLL_SEL_SHIFT); 626 break; 627 case SCLK_PWM1: 628 rk_clrsetreg(&cru->clksel_con[52], 629 CLK_PWM_DIV_CON_MASK << CLK_PWM1_DIV_CON_SHIFT | 630 CLK_PWM_PLL_SEL_MASK << CLK_PWM1_PLL_SEL_SHIFT, 631 (src_clk_div - 1) << CLK_PWM1_DIV_CON_SHIFT | 632 CLK_PWM_PLL_SEL_GPLL << CLK_PWM1_PLL_SEL_SHIFT); 633 break; 634 default: 635 printf("do not support this pwm bus\n"); 636 return -EINVAL; 637 } 638 639 return px30_pwm_get_clk(priv, clk_id); 640 } 641 642 static ulong px30_saradc_get_clk(struct px30_clk_priv *priv) 643 { 644 struct px30_cru *cru = priv->cru; 645 u32 div, con; 646 647 con = readl(&cru->clksel_con[55]); 648 div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK; 649 650 return DIV_TO_RATE(OSC_HZ, div); 651 } 652 653 static ulong px30_saradc_set_clk(struct px30_clk_priv *priv, uint hz) 654 { 655 struct px30_cru *cru = priv->cru; 656 int src_clk_div; 657 658 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); 659 assert(src_clk_div - 1 <= 2047); 660 661 rk_clrsetreg(&cru->clksel_con[55], 662 CLK_SARADC_DIV_CON_MASK, 663 (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT); 664 665 return px30_saradc_get_clk(priv); 666 } 667 668 static ulong px30_spi_get_clk(struct px30_clk_priv *priv, ulong clk_id) 669 { 670 struct px30_cru *cru = priv->cru; 671 u32 div, con; 672 673 switch (clk_id) { 674 case SCLK_SPI0: 675 con = readl(&cru->clksel_con[53]); 676 div = con >> CLK_SPI0_DIV_CON_SHIFT & CLK_SPI_DIV_CON_MASK; 677 break; 678 case SCLK_SPI1: 679 con = readl(&cru->clksel_con[53]); 680 div = con >> CLK_SPI1_DIV_CON_SHIFT & CLK_SPI_DIV_CON_MASK; 681 break; 682 default: 683 printf("do not support this pwm bus\n"); 684 return -EINVAL; 685 } 686 687 return DIV_TO_RATE(priv->gpll_hz, div); 688 } 689 690 static ulong px30_spi_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) 691 { 692 struct px30_cru *cru = priv->cru; 693 int src_clk_div; 694 695 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 696 assert(src_clk_div - 1 <= 127); 697 698 switch (clk_id) { 699 case SCLK_SPI0: 700 rk_clrsetreg(&cru->clksel_con[53], 701 CLK_SPI_DIV_CON_MASK << CLK_SPI0_DIV_CON_SHIFT | 702 CLK_SPI_PLL_SEL_MASK << CLK_SPI0_PLL_SEL_SHIFT, 703 (src_clk_div - 1) << CLK_SPI0_DIV_CON_SHIFT | 704 CLK_SPI_PLL_SEL_GPLL << CLK_SPI0_PLL_SEL_SHIFT); 705 break; 706 case SCLK_SPI1: 707 rk_clrsetreg(&cru->clksel_con[53], 708 CLK_SPI_DIV_CON_MASK << CLK_SPI1_DIV_CON_SHIFT | 709 CLK_SPI_PLL_SEL_MASK << CLK_SPI1_PLL_SEL_SHIFT, 710 (src_clk_div - 1) << CLK_SPI1_DIV_CON_SHIFT | 711 CLK_SPI_PLL_SEL_GPLL << CLK_SPI1_PLL_SEL_SHIFT); 712 break; 713 default: 714 printf("do not support this pwm bus\n"); 715 return -EINVAL; 716 } 717 718 return px30_spi_get_clk(priv, clk_id); 719 } 720 721 static ulong px30_vop_get_clk(struct px30_clk_priv *priv, ulong clk_id) 722 { 723 struct px30_cru *cru = priv->cru; 724 u32 div, con, parent; 725 726 switch (clk_id) { 727 case ACLK_VOPB: 728 case ACLK_VOPL: 729 con = readl(&cru->clksel_con[3]); 730 div = con & ACLK_VO_DIV_MASK; 731 parent = priv->gpll_hz; 732 break; 733 case DCLK_VOPB: 734 con = readl(&cru->clksel_con[5]); 735 div = con & DCLK_VOPB_DIV_MASK; 736 parent = rkclk_pll_get_rate(&cru->pll[CPLL], &cru->mode, CPLL); 737 break; 738 case DCLK_VOPL: 739 con = readl(&cru->clksel_con[8]); 740 div = con & DCLK_VOPL_DIV_MASK; 741 parent = rkclk_pll_get_rate(&cru->pll[NPLL], &cru->mode, NPLL); 742 break; 743 default: 744 return -ENOENT; 745 } 746 747 return DIV_TO_RATE(parent, div); 748 } 749 750 static ulong px30_vop_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) 751 { 752 struct px30_cru *cru = priv->cru; 753 ulong npll_hz; 754 int src_clk_div; 755 756 switch (clk_id) { 757 case ACLK_VOPB: 758 case ACLK_VOPL: 759 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 760 assert(src_clk_div - 1 <= 31); 761 rk_clrsetreg(&cru->clksel_con[3], 762 ACLK_VO_PLL_MASK | ACLK_VO_DIV_MASK, 763 ACLK_VO_SEL_GPLL << ACLK_VO_PLL_SHIFT | 764 (src_clk_div - 1) << ACLK_VO_DIV_SHIFT); 765 break; 766 case DCLK_VOPB: 767 if (hz < PX30_VOP_PLL_LIMIT) 768 src_clk_div = DIV_ROUND_UP(PX30_VOP_PLL_LIMIT, hz); 769 else 770 src_clk_div = 1; 771 assert(src_clk_div - 1 <= 255); 772 rkclk_set_pll(&cru->pll[CPLL], &cru->mode, CPLL, hz * src_clk_div); 773 rk_clrsetreg(&cru->clksel_con[5], 774 DCLK_VOPB_SEL_MASK | DCLK_VOPB_PLL_SEL_MASK | 775 DCLK_VOPB_DIV_MASK, 776 DCLK_VOPB_SEL_DIVOUT << DCLK_VOPB_SEL_SHIFT | 777 DCLK_VOPB_PLL_SEL_CPLL << DCLK_VOPB_PLL_SEL_SHIFT | 778 (src_clk_div - 1) << DCLK_VOPB_DIV_SHIFT); 779 break; 780 case DCLK_VOPL: 781 npll_hz = px30_clk_get_pll_rate(priv, NPLL); 782 if (npll_hz >= PX30_VOP_PLL_LIMIT && npll_hz >= hz && npll_hz % hz == 0) { 783 src_clk_div = npll_hz / hz; 784 assert(src_clk_div - 1 <= 255); 785 } else { 786 if (hz < PX30_VOP_PLL_LIMIT) 787 src_clk_div = DIV_ROUND_UP(PX30_VOP_PLL_LIMIT, hz); 788 else 789 src_clk_div = 1; 790 assert(src_clk_div - 1 <= 255); 791 rkclk_set_pll(&cru->pll[NPLL], &cru->mode, NPLL, hz * src_clk_div); 792 } 793 rk_clrsetreg(&cru->clksel_con[8], 794 DCLK_VOPL_SEL_MASK | DCLK_VOPL_PLL_SEL_MASK | 795 DCLK_VOPL_DIV_MASK, 796 DCLK_VOPL_SEL_DIVOUT << DCLK_VOPL_SEL_SHIFT | 797 DCLK_VOPL_PLL_SEL_NPLL << DCLK_VOPL_PLL_SEL_SHIFT | 798 (src_clk_div - 1) << DCLK_VOPL_DIV_SHIFT); 799 break; 800 default: 801 printf("do not support this vop freq\n"); 802 return -EINVAL; 803 } 804 805 return px30_vop_get_clk(priv, clk_id); 806 } 807 808 static ulong px30_bus_get_clk(struct px30_clk_priv *priv, ulong clk_id) 809 { 810 struct px30_cru *cru = priv->cru; 811 u32 div, con, parent; 812 813 switch (clk_id) { 814 case ACLK_BUS_PRE: 815 con = readl(&cru->clksel_con[23]); 816 div = (con & BUS_ACLK_DIV_MASK) >> BUS_ACLK_DIV_SHIFT; 817 parent = priv->gpll_hz; 818 break; 819 case HCLK_BUS_PRE: 820 con = readl(&cru->clksel_con[24]); 821 div = (con & BUS_HCLK_DIV_MASK) >> BUS_HCLK_DIV_SHIFT; 822 parent = priv->gpll_hz; 823 break; 824 case PCLK_BUS_PRE: 825 parent = px30_bus_get_clk(priv, ACLK_BUS_PRE); 826 con = readl(&cru->clksel_con[24]); 827 div = (con & BUS_PCLK_DIV_MASK) >> BUS_PCLK_DIV_SHIFT; 828 break; 829 default: 830 return -ENOENT; 831 } 832 833 return DIV_TO_RATE(parent, div); 834 } 835 836 static ulong px30_bus_set_clk(struct px30_clk_priv *priv, ulong clk_id, 837 ulong hz) 838 { 839 struct px30_cru *cru = priv->cru; 840 int src_clk_div; 841 842 /* 843 * select gpll as pd_bus bus clock source and 844 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 845 */ 846 switch (clk_id) { 847 case ACLK_BUS_PRE: 848 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 849 assert(src_clk_div - 1 <= 31); 850 rk_clrsetreg(&cru->clksel_con[23], 851 BUS_PLL_SEL_MASK | BUS_ACLK_DIV_MASK, 852 BUS_PLL_SEL_GPLL << BUS_PLL_SEL_SHIFT | 853 (src_clk_div - 1) << BUS_ACLK_DIV_SHIFT); 854 break; 855 case HCLK_BUS_PRE: 856 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 857 assert(src_clk_div - 1 <= 31); 858 rk_clrsetreg(&cru->clksel_con[24], 859 BUS_PLL_SEL_MASK | BUS_HCLK_DIV_MASK, 860 BUS_PLL_SEL_GPLL << BUS_PLL_SEL_SHIFT | 861 (src_clk_div - 1) << BUS_HCLK_DIV_SHIFT); 862 break; 863 case PCLK_BUS_PRE: 864 src_clk_div = 865 DIV_ROUND_UP(px30_bus_get_clk(priv, ACLK_BUS_PRE), hz); 866 assert(src_clk_div - 1 <= 3); 867 rk_clrsetreg(&cru->clksel_con[24], 868 BUS_PCLK_DIV_MASK, 869 (src_clk_div - 1) << BUS_PCLK_DIV_SHIFT); 870 break; 871 default: 872 printf("do not support this bus freq\n"); 873 return -EINVAL; 874 } 875 876 return px30_bus_get_clk(priv, clk_id); 877 } 878 879 static ulong px30_peri_get_clk(struct px30_clk_priv *priv, ulong clk_id) 880 { 881 struct px30_cru *cru = priv->cru; 882 u32 div, con, parent; 883 884 switch (clk_id) { 885 case ACLK_PERI_PRE: 886 con = readl(&cru->clksel_con[14]); 887 div = (con & PERI_ACLK_DIV_MASK) >> PERI_ACLK_DIV_SHIFT; 888 parent = priv->gpll_hz; 889 break; 890 case HCLK_PERI_PRE: 891 con = readl(&cru->clksel_con[14]); 892 div = (con & PERI_HCLK_DIV_MASK) >> PERI_HCLK_DIV_SHIFT; 893 parent = priv->gpll_hz; 894 break; 895 default: 896 return -ENOENT; 897 } 898 899 return DIV_TO_RATE(parent, div); 900 } 901 902 static ulong px30_peri_set_clk(struct px30_clk_priv *priv, ulong clk_id, 903 ulong hz) 904 { 905 struct px30_cru *cru = priv->cru; 906 int src_clk_div; 907 908 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 909 assert(src_clk_div - 1 <= 31); 910 911 /* 912 * select gpll as pd_peri bus clock source and 913 * set up dependent divisors for HCLK and ACLK clocks. 914 */ 915 switch (clk_id) { 916 case ACLK_PERI_PRE: 917 rk_clrsetreg(&cru->clksel_con[14], 918 PERI_PLL_SEL_MASK | PERI_ACLK_DIV_MASK, 919 PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT | 920 (src_clk_div - 1) << PERI_ACLK_DIV_SHIFT); 921 break; 922 case HCLK_PERI_PRE: 923 rk_clrsetreg(&cru->clksel_con[14], 924 PERI_PLL_SEL_MASK | PERI_HCLK_DIV_MASK, 925 PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT | 926 (src_clk_div - 1) << PERI_HCLK_DIV_SHIFT); 927 break; 928 default: 929 printf("do not support this peri freq\n"); 930 return -EINVAL; 931 } 932 933 return px30_peri_get_clk(priv, clk_id); 934 } 935 936 static int px30_clk_get_gpll_rate(ulong *rate) 937 { 938 struct udevice *pmucru_dev; 939 struct px30_pmuclk_priv *priv; 940 int ret; 941 942 ret = uclass_get_device_by_driver(UCLASS_CLK, 943 DM_GET_DRIVER(rockchip_px30_pmucru), 944 &pmucru_dev); 945 if (ret) { 946 printf("%s: could not find pmucru device\n", __func__); 947 return ret; 948 } 949 priv = dev_get_priv(pmucru_dev); 950 *rate = priv->gpll_hz; 951 952 return 0; 953 } 954 955 static ulong px30_clk_get_pll_rate(struct px30_clk_priv *priv, 956 enum px30_pll_id pll_id) 957 { 958 struct px30_cru *cru = priv->cru; 959 960 return rkclk_pll_get_rate(&cru->pll[pll_id], &cru->mode, pll_id); 961 } 962 963 static ulong px30_clk_set_pll_rate(struct px30_clk_priv *priv, 964 enum px30_pll_id pll_id, ulong hz) 965 { 966 struct px30_cru *cru = priv->cru; 967 968 if (rkclk_set_pll(&cru->pll[pll_id], &cru->mode, pll_id, hz)) 969 return -EINVAL; 970 return rkclk_pll_get_rate(&cru->pll[pll_id], &cru->mode, pll_id); 971 } 972 973 static ulong px30_armclk_set_clk(struct px30_clk_priv *priv, ulong hz) 974 { 975 struct px30_cru *cru = priv->cru; 976 const struct cpu_rate_table *rate; 977 ulong old_rate; 978 979 rate = get_cpu_settings(hz); 980 if (!rate) { 981 printf("%s unsupport rate\n", __func__); 982 return -EINVAL; 983 } 984 985 /* 986 * select apll as cpu/core clock pll source and 987 * set up dependent divisors for PERI and ACLK clocks. 988 * core hz : apll = 1:1 989 */ 990 old_rate = px30_clk_get_pll_rate(priv, APLL); 991 if (old_rate > hz) { 992 if (rkclk_set_pll(&cru->pll[APLL], &cru->mode, APLL, hz)) 993 return -EINVAL; 994 rk_clrsetreg(&cru->clksel_con[0], 995 CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK | 996 CORE_ACLK_DIV_MASK | CORE_DBG_DIV_MASK, 997 rate->aclk_div << CORE_ACLK_DIV_SHIFT | 998 rate->pclk_div << CORE_DBG_DIV_SHIFT | 999 CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT | 1000 0 << CORE_DIV_CON_SHIFT); 1001 } else if (old_rate < hz) { 1002 rk_clrsetreg(&cru->clksel_con[0], 1003 CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK | 1004 CORE_ACLK_DIV_MASK | CORE_DBG_DIV_MASK, 1005 rate->aclk_div << CORE_ACLK_DIV_SHIFT | 1006 rate->pclk_div << CORE_DBG_DIV_SHIFT | 1007 CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT | 1008 0 << CORE_DIV_CON_SHIFT); 1009 if (rkclk_set_pll(&cru->pll[APLL], &cru->mode, APLL, hz)) 1010 return -EINVAL; 1011 } 1012 1013 return px30_clk_get_pll_rate(priv, APLL); 1014 } 1015 1016 static ulong px30_clk_get_rate(struct clk *clk) 1017 { 1018 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 1019 ulong rate = 0; 1020 1021 if (!priv->gpll_hz && clk->id > ARMCLK) { 1022 printf("%s gpll=%lu\n", __func__, priv->gpll_hz); 1023 return -ENOENT; 1024 } 1025 1026 debug("%s %ld\n", __func__, clk->id); 1027 switch (clk->id) { 1028 case PLL_APLL: 1029 rate = px30_clk_get_pll_rate(priv, APLL); 1030 break; 1031 case PLL_DPLL: 1032 rate = px30_clk_get_pll_rate(priv, DPLL); 1033 break; 1034 case PLL_CPLL: 1035 rate = px30_clk_get_pll_rate(priv, CPLL); 1036 break; 1037 case PLL_NPLL: 1038 rate = px30_clk_get_pll_rate(priv, NPLL); 1039 break; 1040 case ARMCLK: 1041 rate = px30_clk_get_pll_rate(priv, APLL); 1042 break; 1043 case HCLK_SDMMC: 1044 case HCLK_EMMC: 1045 case SCLK_SDMMC: 1046 case SCLK_EMMC: 1047 case SCLK_EMMC_SAMPLE: 1048 rate = px30_mmc_get_clk(priv, clk->id); 1049 break; 1050 case SCLK_I2C0: 1051 case SCLK_I2C1: 1052 case SCLK_I2C2: 1053 case SCLK_I2C3: 1054 rate = px30_i2c_get_clk(priv, clk->id); 1055 break; 1056 case SCLK_I2S1: 1057 rate = px30_i2s_get_clk(priv, clk->id); 1058 break; 1059 case SCLK_PWM0: 1060 case SCLK_PWM1: 1061 rate = px30_pwm_get_clk(priv, clk->id); 1062 break; 1063 case SCLK_SARADC: 1064 rate = px30_saradc_get_clk(priv); 1065 break; 1066 case SCLK_SPI0: 1067 case SCLK_SPI1: 1068 rate = px30_spi_get_clk(priv, clk->id); 1069 break; 1070 case ACLK_VOPB: 1071 case ACLK_VOPL: 1072 case DCLK_VOPB: 1073 case DCLK_VOPL: 1074 rate = px30_vop_get_clk(priv, clk->id); 1075 break; 1076 case ACLK_BUS_PRE: 1077 case HCLK_BUS_PRE: 1078 case PCLK_BUS_PRE: 1079 rate = px30_bus_get_clk(priv, clk->id); 1080 break; 1081 case ACLK_PERI_PRE: 1082 case HCLK_PERI_PRE: 1083 rate = px30_peri_get_clk(priv, clk->id); 1084 break; 1085 default: 1086 return -ENOENT; 1087 } 1088 1089 return rate; 1090 } 1091 1092 static ulong px30_clk_set_rate(struct clk *clk, ulong rate) 1093 { 1094 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 1095 ulong ret = 0; 1096 1097 if (!priv->gpll_hz && clk->id > ARMCLK) { 1098 printf("%s gpll=%lu\n", __func__, priv->gpll_hz); 1099 return -ENOENT; 1100 } 1101 1102 debug("%s %ld %ld\n", __func__, clk->id, rate); 1103 switch (clk->id) { 1104 case PLL_NPLL: 1105 ret = px30_clk_set_pll_rate(priv, NPLL, rate); 1106 break; 1107 case ARMCLK: 1108 if (priv->armclk_hz) 1109 px30_armclk_set_clk(priv, rate); 1110 priv->armclk_hz = rate; 1111 break; 1112 case HCLK_SDMMC: 1113 case HCLK_EMMC: 1114 case SCLK_SDMMC: 1115 case SCLK_EMMC: 1116 ret = px30_mmc_set_clk(priv, clk->id, rate); 1117 break; 1118 case SCLK_I2C0: 1119 case SCLK_I2C1: 1120 case SCLK_I2C2: 1121 case SCLK_I2C3: 1122 ret = px30_i2c_set_clk(priv, clk->id, rate); 1123 break; 1124 case SCLK_I2S1: 1125 ret = px30_i2s_set_clk(priv, clk->id, rate); 1126 break; 1127 case SCLK_PWM0: 1128 case SCLK_PWM1: 1129 ret = px30_pwm_set_clk(priv, clk->id, rate); 1130 break; 1131 case SCLK_SARADC: 1132 ret = px30_saradc_set_clk(priv, rate); 1133 break; 1134 case SCLK_SPI0: 1135 case SCLK_SPI1: 1136 ret = px30_spi_set_clk(priv, clk->id, rate); 1137 break; 1138 case ACLK_VOPB: 1139 case ACLK_VOPL: 1140 case DCLK_VOPB: 1141 case DCLK_VOPL: 1142 ret = px30_vop_set_clk(priv, clk->id, rate); 1143 break; 1144 case ACLK_BUS_PRE: 1145 case HCLK_BUS_PRE: 1146 case PCLK_BUS_PRE: 1147 ret = px30_bus_set_clk(priv, clk->id, rate); 1148 break; 1149 case ACLK_PERI_PRE: 1150 case HCLK_PERI_PRE: 1151 ret = px30_peri_set_clk(priv, clk->id, rate); 1152 break; 1153 default: 1154 return -ENOENT; 1155 } 1156 1157 return ret; 1158 } 1159 1160 #define ROCKCHIP_MMC_DELAY_SEL BIT(10) 1161 #define ROCKCHIP_MMC_DEGREE_MASK 0x3 1162 #define ROCKCHIP_MMC_DELAYNUM_OFFSET 2 1163 #define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET) 1164 1165 #define PSECS_PER_SEC 1000000000000LL 1166 /* 1167 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to 1168 * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg. 1169 */ 1170 #define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60 1171 1172 int rockchip_mmc_get_phase(struct clk *clk) 1173 { 1174 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 1175 struct px30_cru *cru = priv->cru; 1176 u32 raw_value, delay_num; 1177 u16 degrees = 0; 1178 ulong rate; 1179 1180 rate = px30_clk_get_rate(clk); 1181 1182 if (rate < 0) 1183 return rate; 1184 1185 if (clk->id == SCLK_EMMC_SAMPLE) 1186 raw_value = readl(&cru->emmc_con[1]); 1187 else 1188 raw_value = readl(&cru->sdmmc_con[1]); 1189 1190 raw_value >>= 1; 1191 degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90; 1192 1193 if (raw_value & ROCKCHIP_MMC_DELAY_SEL) { 1194 /* degrees/delaynum * 10000 */ 1195 unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) * 1196 36 * (rate / 1000000); 1197 1198 delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK); 1199 delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET; 1200 degrees += DIV_ROUND_CLOSEST(delay_num * factor, 10000); 1201 } 1202 1203 return degrees % 360; 1204 } 1205 1206 int rockchip_mmc_set_phase(struct clk *clk, u32 degrees) 1207 { 1208 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 1209 struct px30_cru *cru = priv->cru; 1210 u8 nineties, remainder, delay_num; 1211 u32 raw_value, delay; 1212 ulong rate; 1213 1214 rate = px30_clk_get_rate(clk); 1215 1216 if (rate < 0) 1217 return rate; 1218 1219 nineties = degrees / 90; 1220 remainder = (degrees % 90); 1221 1222 /* 1223 * Convert to delay; do a little extra work to make sure we 1224 * don't overflow 32-bit / 64-bit numbers. 1225 */ 1226 delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */ 1227 delay *= remainder; 1228 delay = DIV_ROUND_CLOSEST(delay, (rate / 1000) * 36 * 1229 (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10)); 1230 1231 delay_num = (u8)min_t(u32, delay, 255); 1232 1233 raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0; 1234 raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET; 1235 raw_value |= nineties; 1236 1237 raw_value <<= 1; 1238 if (clk->id == SCLK_EMMC_SAMPLE) 1239 writel(raw_value | 0xffff0000, &cru->emmc_con[1]); 1240 else 1241 writel(raw_value | 0xffff0000, &cru->sdmmc_con[1]); 1242 1243 debug("mmc set_phase(%d) delay_nums=%u reg=%#x actual_degrees=%d\n", 1244 degrees, delay_num, raw_value, rockchip_mmc_get_phase(clk)); 1245 1246 return 0; 1247 } 1248 1249 static int px30_clk_get_phase(struct clk *clk) 1250 { 1251 int ret; 1252 1253 debug("%s %ld\n", __func__, clk->id); 1254 switch (clk->id) { 1255 case SCLK_EMMC_SAMPLE: 1256 case SCLK_SDMMC_SAMPLE: 1257 ret = rockchip_mmc_get_phase(clk); 1258 break; 1259 default: 1260 return -ENOENT; 1261 } 1262 1263 return ret; 1264 } 1265 1266 static int px30_clk_set_phase(struct clk *clk, int degrees) 1267 { 1268 int ret; 1269 1270 debug("%s %ld\n", __func__, clk->id); 1271 switch (clk->id) { 1272 case SCLK_EMMC_SAMPLE: 1273 case SCLK_SDMMC_SAMPLE: 1274 ret = rockchip_mmc_set_phase(clk, degrees); 1275 break; 1276 default: 1277 return -ENOENT; 1278 } 1279 1280 return ret; 1281 } 1282 1283 static struct clk_ops px30_clk_ops = { 1284 .get_rate = px30_clk_get_rate, 1285 .set_rate = px30_clk_set_rate, 1286 .get_phase = px30_clk_get_phase, 1287 .set_phase = px30_clk_set_phase, 1288 }; 1289 1290 static int px30_clk_probe(struct udevice *dev) 1291 { 1292 struct px30_clk_priv *priv = dev_get_priv(dev); 1293 int ret; 1294 1295 if (px30_clk_get_pll_rate(priv, APLL) != APLL_HZ) { 1296 ret = px30_armclk_set_clk(priv, APLL_HZ); 1297 if (ret < 0) 1298 printf("%s failed to set armclk rate\n", __func__); 1299 } 1300 1301 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 1302 ret = clk_set_defaults(dev); 1303 if (ret) 1304 debug("%s clk_set_defaults failed %d\n", __func__, ret); 1305 1306 if (!priv->gpll_hz) { 1307 ret = px30_clk_get_gpll_rate(&priv->gpll_hz); 1308 if (ret) { 1309 printf("%s failed to get gpll rate\n", __func__); 1310 return ret; 1311 } 1312 } 1313 1314 return 0; 1315 } 1316 1317 static int px30_clk_ofdata_to_platdata(struct udevice *dev) 1318 { 1319 struct px30_clk_priv *priv = dev_get_priv(dev); 1320 1321 priv->cru = dev_read_addr_ptr(dev); 1322 1323 return 0; 1324 } 1325 1326 static int px30_clk_bind(struct udevice *dev) 1327 { 1328 int ret; 1329 struct udevice *sys_child, *sf_child; 1330 struct sysreset_reg *priv; 1331 struct softreset_reg *sf_priv; 1332 1333 /* The reset driver does not have a device node, so bind it here */ 1334 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", 1335 &sys_child); 1336 if (ret) { 1337 debug("Warning: No sysreset driver: ret=%d\n", ret); 1338 } else { 1339 priv = malloc(sizeof(struct sysreset_reg)); 1340 priv->glb_srst_fst_value = offsetof(struct px30_cru, 1341 glb_srst_fst); 1342 priv->glb_srst_snd_value = offsetof(struct px30_cru, 1343 glb_srst_snd); 1344 sys_child->priv = priv; 1345 } 1346 1347 ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset", 1348 dev_ofnode(dev), &sf_child); 1349 if (ret) { 1350 debug("Warning: No rockchip reset driver: ret=%d\n", ret); 1351 } else { 1352 sf_priv = malloc(sizeof(struct softreset_reg)); 1353 sf_priv->sf_reset_offset = offsetof(struct px30_cru, 1354 softrst_con[0]); 1355 sf_priv->sf_reset_num = 12; 1356 sf_child->priv = sf_priv; 1357 } 1358 1359 return 0; 1360 } 1361 1362 static const struct udevice_id px30_clk_ids[] = { 1363 { .compatible = "rockchip,px30-cru" }, 1364 { } 1365 }; 1366 1367 U_BOOT_DRIVER(rockchip_px30_cru) = { 1368 .name = "rockchip_px30_cru", 1369 .id = UCLASS_CLK, 1370 .of_match = px30_clk_ids, 1371 .priv_auto_alloc_size = sizeof(struct px30_clk_priv), 1372 .ofdata_to_platdata = px30_clk_ofdata_to_platdata, 1373 .ops = &px30_clk_ops, 1374 .bind = px30_clk_bind, 1375 .probe = px30_clk_probe, 1376 }; 1377 1378 static ulong px30_pclk_pmu_get_pmuclk(struct px30_pmuclk_priv *priv) 1379 { 1380 struct px30_pmucru *pmucru = priv->pmucru; 1381 u32 div, con; 1382 1383 con = readl(&pmucru->pmu_clksel_con[0]); 1384 div = (con & CLK_PMU_PCLK_DIV_MASK) >> CLK_PMU_PCLK_DIV_SHIFT; 1385 1386 return DIV_TO_RATE(priv->gpll_hz, div); 1387 } 1388 1389 static ulong px30_pclk_pmu_set_pmuclk(struct px30_pmuclk_priv *priv, ulong hz) 1390 { 1391 struct px30_pmucru *pmucru = priv->pmucru; 1392 int src_clk_div; 1393 1394 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 1395 assert(src_clk_div - 1 <= 31); 1396 1397 rk_clrsetreg(&pmucru->pmu_clksel_con[0], 1398 CLK_PMU_PCLK_DIV_MASK, 1399 (src_clk_div - 1) << CLK_PMU_PCLK_DIV_SHIFT); 1400 1401 return px30_pclk_pmu_get_pmuclk(priv); 1402 } 1403 1404 static ulong px30_gpll_get_pmuclk(struct px30_pmuclk_priv *priv) 1405 { 1406 struct px30_pmucru *pmucru = priv->pmucru; 1407 1408 return rkclk_pll_get_rate(&pmucru->pll, &pmucru->pmu_mode, GPLL); 1409 } 1410 1411 static ulong px30_gpll_set_pmuclk(struct px30_pmuclk_priv *priv, ulong hz) 1412 { 1413 struct udevice *cru_dev; 1414 struct px30_clk_priv *cru_priv; 1415 struct px30_pmucru *pmucru = priv->pmucru; 1416 u32 div; 1417 ulong emmc_rate, sdmmc_rate, nandc_rate; 1418 ulong aclk_bus_rate, hclk_bus_rate, pclk_bus_rate; 1419 ulong aclk_peri_rate, hclk_peri_rate, pclk_pmu_rate; 1420 int ret; 1421 1422 ret = uclass_get_device_by_name(UCLASS_CLK, 1423 "clock-controller@ff2b0000", 1424 &cru_dev); 1425 if (ret) { 1426 printf("%s failed to get cru device\n", __func__); 1427 return ret; 1428 } 1429 cru_priv = dev_get_priv(cru_dev); 1430 1431 if (priv->gpll_hz == hz) 1432 return priv->gpll_hz; 1433 1434 cru_priv->gpll_hz = priv->gpll_hz; 1435 div = DIV_ROUND_UP(hz, priv->gpll_hz); 1436 1437 /* save clock rate */ 1438 aclk_bus_rate = px30_bus_get_clk(cru_priv, ACLK_BUS_PRE); 1439 hclk_bus_rate = px30_bus_get_clk(cru_priv, HCLK_BUS_PRE); 1440 pclk_bus_rate = px30_bus_get_clk(cru_priv, PCLK_BUS_PRE); 1441 aclk_peri_rate = px30_peri_get_clk(cru_priv, ACLK_PERI_PRE); 1442 hclk_peri_rate = px30_peri_get_clk(cru_priv, HCLK_PERI_PRE); 1443 pclk_pmu_rate = px30_pclk_pmu_get_pmuclk(priv); 1444 debug("%s aclk_bus=%lu, hclk_bus=%lu, pclk_bus=%lu\n", __func__, 1445 aclk_bus_rate, hclk_bus_rate, pclk_bus_rate); 1446 debug("%s aclk_peri=%lu, hclk_peri=%lu, pclk_pmu=%lu\n", __func__, 1447 aclk_peri_rate, hclk_peri_rate, pclk_pmu_rate); 1448 emmc_rate = px30_mmc_get_clk(cru_priv, SCLK_EMMC); 1449 sdmmc_rate = px30_mmc_get_clk(cru_priv, SCLK_SDMMC); 1450 nandc_rate = px30_nandc_get_clk(cru_priv); 1451 debug("%s emmc=%lu, sdmmc=%lu, nandc=%lu\n", __func__, 1452 emmc_rate, sdmmc_rate, nandc_rate); 1453 1454 /* avoid rate too large, reduce rate first */ 1455 px30_bus_set_clk(cru_priv, ACLK_BUS_PRE, aclk_bus_rate / div); 1456 px30_bus_set_clk(cru_priv, HCLK_BUS_PRE, hclk_bus_rate / div); 1457 px30_bus_set_clk(cru_priv, PCLK_BUS_PRE, pclk_bus_rate / div); 1458 px30_peri_set_clk(cru_priv, ACLK_PERI_PRE, aclk_peri_rate / div); 1459 px30_peri_set_clk(cru_priv, HCLK_PERI_PRE, hclk_peri_rate / div); 1460 px30_pclk_pmu_set_pmuclk(priv, pclk_pmu_rate / div); 1461 1462 px30_mmc_set_clk(cru_priv, SCLK_EMMC, emmc_rate / div); 1463 px30_mmc_set_clk(cru_priv, SCLK_SDMMC, sdmmc_rate / div); 1464 px30_nandc_set_clk(cru_priv, nandc_rate / div); 1465 1466 /* change gpll rate */ 1467 rkclk_set_pll(&pmucru->pll, &pmucru->pmu_mode, GPLL, hz); 1468 priv->gpll_hz = px30_gpll_get_pmuclk(priv); 1469 cru_priv->gpll_hz = priv->gpll_hz; 1470 1471 /* restore clock rate */ 1472 px30_bus_set_clk(cru_priv, ACLK_BUS_PRE, aclk_bus_rate); 1473 px30_bus_set_clk(cru_priv, HCLK_BUS_PRE, hclk_bus_rate); 1474 px30_bus_set_clk(cru_priv, PCLK_BUS_PRE, pclk_bus_rate); 1475 px30_peri_set_clk(cru_priv, ACLK_PERI_PRE, aclk_peri_rate); 1476 px30_peri_set_clk(cru_priv, HCLK_PERI_PRE, hclk_peri_rate); 1477 px30_pclk_pmu_set_pmuclk(priv, pclk_pmu_rate); 1478 1479 px30_mmc_set_clk(cru_priv, SCLK_EMMC, emmc_rate); 1480 px30_mmc_set_clk(cru_priv, SCLK_SDMMC, sdmmc_rate); 1481 px30_nandc_set_clk(cru_priv, nandc_rate); 1482 1483 return priv->gpll_hz; 1484 } 1485 1486 static ulong px30_pmuclk_get_rate(struct clk *clk) 1487 { 1488 struct px30_pmuclk_priv *priv = dev_get_priv(clk->dev); 1489 ulong rate = 0; 1490 1491 debug("%s %ld\n", __func__, clk->id); 1492 switch (clk->id) { 1493 case PLL_GPLL: 1494 rate = px30_gpll_get_pmuclk(priv); 1495 break; 1496 case PCLK_PMU_PRE: 1497 rate = px30_pclk_pmu_get_pmuclk(priv); 1498 break; 1499 default: 1500 return -ENOENT; 1501 } 1502 1503 return rate; 1504 } 1505 1506 static ulong px30_pmuclk_set_rate(struct clk *clk, ulong rate) 1507 { 1508 struct px30_pmuclk_priv *priv = dev_get_priv(clk->dev); 1509 ulong ret = 0; 1510 1511 debug("%s %ld %ld\n", __func__, clk->id, rate); 1512 switch (clk->id) { 1513 case PLL_GPLL: 1514 ret = px30_gpll_set_pmuclk(priv, rate); 1515 break; 1516 case PCLK_PMU_PRE: 1517 ret = px30_pclk_pmu_set_pmuclk(priv, rate); 1518 break; 1519 default: 1520 return -ENOENT; 1521 } 1522 1523 return ret; 1524 } 1525 1526 static struct clk_ops px30_pmuclk_ops = { 1527 .get_rate = px30_pmuclk_get_rate, 1528 .set_rate = px30_pmuclk_set_rate, 1529 }; 1530 1531 static void px30_clk_init(struct px30_pmuclk_priv *priv) 1532 { 1533 struct udevice *cru_dev; 1534 struct px30_clk_priv *cru_priv; 1535 ulong npll_hz; 1536 int ret; 1537 1538 priv->gpll_hz = px30_gpll_get_pmuclk(priv); 1539 if (priv->gpll_hz != GPLL_HZ) { 1540 ret = px30_gpll_set_pmuclk(priv, GPLL_HZ); 1541 if (ret < 0) 1542 printf("%s failed to set gpll rate\n", __func__); 1543 } 1544 1545 ret = uclass_get_device_by_name(UCLASS_CLK, 1546 "clock-controller@ff2b0000", 1547 &cru_dev); 1548 if (ret) { 1549 printf("%s failed to get cru device\n", __func__); 1550 return; 1551 } 1552 cru_priv = dev_get_priv(cru_dev); 1553 cru_priv->gpll_hz = priv->gpll_hz; 1554 1555 npll_hz = px30_clk_get_pll_rate(cru_priv, NPLL); 1556 if (npll_hz != NPLL_HZ) { 1557 ret = px30_clk_set_pll_rate(cru_priv, NPLL, NPLL_HZ); 1558 if (ret < 0) 1559 printf("%s failed to set npll rate\n", __func__); 1560 } 1561 1562 px30_bus_set_clk(cru_priv, ACLK_BUS_PRE, ACLK_BUS_HZ); 1563 px30_bus_set_clk(cru_priv, HCLK_BUS_PRE, HCLK_BUS_HZ); 1564 px30_bus_set_clk(cru_priv, PCLK_BUS_PRE, PCLK_BUS_HZ); 1565 px30_peri_set_clk(cru_priv, ACLK_PERI_PRE, ACLK_PERI_HZ); 1566 px30_peri_set_clk(cru_priv, HCLK_PERI_PRE, HCLK_PERI_HZ); 1567 px30_pclk_pmu_set_pmuclk(priv, PCLK_PMU_HZ); 1568 } 1569 1570 static int px30_pmuclk_probe(struct udevice *dev) 1571 { 1572 struct px30_pmuclk_priv *priv = dev_get_priv(dev); 1573 int ret; 1574 1575 px30_clk_init(priv); 1576 1577 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 1578 ret = clk_set_defaults(dev); 1579 if (ret) 1580 debug("%s clk_set_defaults failed %d\n", __func__, ret); 1581 1582 return 0; 1583 } 1584 1585 static int px30_pmuclk_ofdata_to_platdata(struct udevice *dev) 1586 { 1587 struct px30_pmuclk_priv *priv = dev_get_priv(dev); 1588 1589 priv->pmucru = dev_read_addr_ptr(dev); 1590 1591 return 0; 1592 } 1593 1594 static const struct udevice_id px30_pmuclk_ids[] = { 1595 { .compatible = "rockchip,px30-pmucru" }, 1596 { } 1597 }; 1598 1599 U_BOOT_DRIVER(rockchip_px30_pmucru) = { 1600 .name = "rockchip_px30_pmucru", 1601 .id = UCLASS_CLK, 1602 .of_match = px30_pmuclk_ids, 1603 .priv_auto_alloc_size = sizeof(struct px30_pmuclk_priv), 1604 .ofdata_to_platdata = px30_pmuclk_ofdata_to_platdata, 1605 .ops = &px30_pmuclk_ops, 1606 .probe = px30_pmuclk_probe, 1607 }; 1608 1609 /** 1610 * soc_clk_dump() - Print clock frequencies 1611 * Returns zero on success 1612 * 1613 * Implementation for the clk dump command. 1614 */ 1615 int soc_clk_dump(void) 1616 { 1617 struct udevice *cru_dev, *pmucru_dev; 1618 const struct px30_clk_info *clk_dump; 1619 struct clk clk; 1620 unsigned long clk_count = ARRAY_SIZE(clks_dump); 1621 unsigned long rate; 1622 int i, ret; 1623 1624 ret = uclass_get_device_by_driver(UCLASS_CLK, 1625 DM_GET_DRIVER(rockchip_px30_cru), 1626 &cru_dev); 1627 if (ret) { 1628 printf("%s failed to get cru device\n", __func__); 1629 return ret; 1630 } 1631 1632 ret = uclass_get_device_by_driver(UCLASS_CLK, 1633 DM_GET_DRIVER(rockchip_px30_pmucru), 1634 &pmucru_dev); 1635 if (ret) { 1636 printf("%s failed to get pmucru device\n", __func__); 1637 return ret; 1638 } 1639 1640 printf("CLK:\n"); 1641 for (i = 0; i < clk_count; i++) { 1642 clk_dump = &clks_dump[i]; 1643 if (clk_dump->name) { 1644 clk.id = clk_dump->id; 1645 if (clk_dump->is_cru) 1646 ret = clk_request(cru_dev, &clk); 1647 else 1648 ret = clk_request(pmucru_dev, &clk); 1649 if (ret < 0) 1650 return ret; 1651 1652 rate = clk_get_rate(&clk); 1653 clk_free(&clk); 1654 if (i == 0) { 1655 if (rate < 0) 1656 printf("%s %s\n", clk_dump->name, 1657 "unknown"); 1658 else 1659 printf("%s %lu KHz\n", clk_dump->name, 1660 rate / 1000); 1661 } else { 1662 if (rate < 0) 1663 printf("%s %s\n", clk_dump->name, 1664 "unknown"); 1665 else 1666 printf("%s %lu KHz\n", clk_dump->name, 1667 rate / 1000); 1668 } 1669 } 1670 } 1671 1672 return 0; 1673 } 1674