1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <bitfield.h> 9 #include <clk-uclass.h> 10 #include <dm.h> 11 #include <errno.h> 12 #include <syscon.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch/cru_px30.h> 15 #include <asm/arch/hardware.h> 16 #include <asm/io.h> 17 #include <dm/lists.h> 18 #include <dt-bindings/clock/px30-cru.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 enum { 23 VCO_MAX_HZ = 3200U * 1000000, 24 VCO_MIN_HZ = 800 * 1000000, 25 OUTPUT_MAX_HZ = 3200U * 1000000, 26 OUTPUT_MIN_HZ = 24 * 1000000, 27 }; 28 29 #define PX30_VOP_PLL_LIMIT 600000000 30 31 #define PX30_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ 32 _postdiv2, _dsmpd, _frac) \ 33 { \ 34 .rate = _rate##U, \ 35 .fbdiv = _fbdiv, \ 36 .postdiv1 = _postdiv1, \ 37 .refdiv = _refdiv, \ 38 .postdiv2 = _postdiv2, \ 39 .dsmpd = _dsmpd, \ 40 .frac = _frac, \ 41 } 42 43 #define PX30_CPUCLK_RATE(_rate, _aclk_div, _pclk_div) \ 44 { \ 45 .rate = _rate##U, \ 46 .aclk_div = _aclk_div, \ 47 .pclk_div = _pclk_div, \ 48 } 49 50 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 51 52 #define PX30_CLK_DUMP(_id, _name, _iscru) \ 53 { \ 54 .id = _id, \ 55 .name = _name, \ 56 .is_cru = _iscru, \ 57 } 58 59 static struct pll_rate_table px30_pll_rates[] = { 60 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 61 PX30_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), 62 PX30_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), 63 PX30_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), 64 PX30_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 65 PX30_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), 66 PX30_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), 67 PX30_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0), 68 }; 69 70 static const struct px30_clk_info clks_dump[] = { 71 PX30_CLK_DUMP(PLL_APLL, "apll", true), 72 PX30_CLK_DUMP(PLL_DPLL, "dpll", true), 73 PX30_CLK_DUMP(PLL_CPLL, "cpll", true), 74 PX30_CLK_DUMP(PLL_NPLL, "npll", true), 75 PX30_CLK_DUMP(PLL_GPLL, "gpll", false), 76 PX30_CLK_DUMP(ACLK_BUS_PRE, "aclk_bus", true), 77 PX30_CLK_DUMP(HCLK_BUS_PRE, "hclk_bus", true), 78 PX30_CLK_DUMP(PCLK_BUS_PRE, "pclk_bus", true), 79 PX30_CLK_DUMP(ACLK_PERI_PRE, "aclk_peri", true), 80 PX30_CLK_DUMP(HCLK_PERI_PRE, "hclk_peri", true), 81 PX30_CLK_DUMP(PCLK_PMU_PRE, "pclk_pmu", false), 82 }; 83 84 static struct cpu_rate_table px30_cpu_rates[] = { 85 PX30_CPUCLK_RATE(1200000000, 1, 5), 86 PX30_CPUCLK_RATE(1008000000, 1, 5), 87 PX30_CPUCLK_RATE(816000000, 1, 3), 88 PX30_CPUCLK_RATE(600000000, 1, 3), 89 }; 90 91 static u8 pll_mode_shift[PLL_COUNT] = { 92 APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, 93 NPLL_MODE_SHIFT, GPLL_MODE_SHIFT 94 }; 95 static u32 pll_mode_mask[PLL_COUNT] = { 96 APLL_MODE_MASK, DPLL_MODE_MASK, CPLL_MODE_MASK, 97 NPLL_MODE_MASK, GPLL_MODE_MASK 98 }; 99 100 static struct pll_rate_table auto_table; 101 102 static ulong px30_clk_get_pll_rate(struct px30_clk_priv *priv, 103 enum px30_pll_id pll_id); 104 105 static struct pll_rate_table *pll_clk_set_by_auto(u32 drate) 106 { 107 struct pll_rate_table *rate = &auto_table; 108 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; 109 u32 postdiv1, postdiv2 = 1; 110 u32 fref_khz; 111 u32 diff_khz, best_diff_khz; 112 const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16; 113 const u32 max_postdiv1 = 7, max_postdiv2 = 7; 114 u32 vco_khz; 115 u32 rate_khz = drate / KHz; 116 117 if (!drate) { 118 printf("%s: the frequency can't be 0 Hz\n", __func__); 119 return NULL; 120 } 121 122 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, rate_khz); 123 if (postdiv1 > max_postdiv1) { 124 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); 125 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); 126 } 127 128 vco_khz = rate_khz * postdiv1 * postdiv2; 129 130 if (vco_khz < (VCO_MIN_HZ / KHz) || vco_khz > (VCO_MAX_HZ / KHz) || 131 postdiv2 > max_postdiv2) { 132 printf("%s: Cannot find out a supported VCO for Freq (%uHz)\n", 133 __func__, rate_khz); 134 return NULL; 135 } 136 137 rate->postdiv1 = postdiv1; 138 rate->postdiv2 = postdiv2; 139 140 best_diff_khz = vco_khz; 141 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { 142 fref_khz = ref_khz / refdiv; 143 144 fbdiv = vco_khz / fref_khz; 145 if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv)) 146 continue; 147 diff_khz = vco_khz - fbdiv * fref_khz; 148 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) { 149 fbdiv++; 150 diff_khz = fref_khz - diff_khz; 151 } 152 153 if (diff_khz >= best_diff_khz) 154 continue; 155 156 best_diff_khz = diff_khz; 157 rate->refdiv = refdiv; 158 rate->fbdiv = fbdiv; 159 } 160 161 if (best_diff_khz > 4 * (MHz / KHz)) { 162 printf("%s: Failed to match output frequency %u bestis %u Hz\n", 163 __func__, rate_khz, 164 best_diff_khz * KHz); 165 return NULL; 166 } 167 168 return rate; 169 } 170 171 static const struct pll_rate_table *get_pll_settings(unsigned long rate) 172 { 173 unsigned int rate_count = ARRAY_SIZE(px30_pll_rates); 174 int i; 175 176 for (i = 0; i < rate_count; i++) { 177 if (rate == px30_pll_rates[i].rate) 178 return &px30_pll_rates[i]; 179 } 180 181 return pll_clk_set_by_auto(rate); 182 } 183 184 static const struct cpu_rate_table *get_cpu_settings(unsigned long rate) 185 { 186 unsigned int rate_count = ARRAY_SIZE(px30_cpu_rates); 187 int i; 188 189 for (i = 0; i < rate_count; i++) { 190 if (rate == px30_cpu_rates[i].rate) 191 return &px30_cpu_rates[i]; 192 } 193 194 return NULL; 195 } 196 197 /* 198 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63): 199 * Formulas also embedded within the Fractional PLL Verilog model: 200 * If DSMPD = 1 (DSM is disabled, "integer mode") 201 * FOUTVCO = FREF / REFDIV * FBDIV 202 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 203 * Where: 204 * FOUTVCO = Fractional PLL non-divided output frequency 205 * FOUTPOSTDIV = Fractional PLL divided output frequency 206 * (output of second post divider) 207 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input) 208 * REFDIV = Fractional PLL input reference clock divider 209 * FBDIV = Integer value programmed into feedback divide 210 * 211 */ 212 static int rkclk_set_pll(struct px30_pll *pll, unsigned int *mode, 213 enum px30_pll_id pll_id, 214 unsigned long drate) 215 { 216 const struct pll_rate_table *rate; 217 uint vco_hz, output_hz; 218 219 rate = get_pll_settings(drate); 220 if (!rate) { 221 printf("%s unsupport rate\n", __func__); 222 return -EINVAL; 223 } 224 225 /* All PLLs have same VCO and output frequency range restrictions. */ 226 vco_hz = OSC_HZ / 1000 * rate->fbdiv / rate->refdiv * 1000; 227 output_hz = vco_hz / rate->postdiv1 / rate->postdiv2; 228 229 debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n", 230 pll, rate->fbdiv, rate->refdiv, rate->postdiv1, 231 rate->postdiv2, vco_hz, output_hz); 232 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && 233 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ); 234 235 /* 236 * When power on or changing PLL setting, 237 * we must force PLL into slow mode to ensure output stable clock. 238 */ 239 rk_clrsetreg(mode, pll_mode_mask[pll_id], 240 PLLMUX_FROM_XIN24M << pll_mode_shift[pll_id]); 241 242 /* use integer mode */ 243 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); 244 /* Power down */ 245 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); 246 247 rk_clrsetreg(&pll->con0, 248 PLL_POSTDIV1_MASK | PLL_FBDIV_MASK, 249 (rate->postdiv1 << PLL_POSTDIV1_SHIFT) | rate->fbdiv); 250 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, 251 (rate->postdiv2 << PLL_POSTDIV2_SHIFT | 252 rate->refdiv << PLL_REFDIV_SHIFT)); 253 254 /* Power Up */ 255 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); 256 257 /* waiting for pll lock */ 258 while (!(readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))) 259 udelay(1); 260 261 rk_clrsetreg(mode, pll_mode_mask[pll_id], 262 PLLMUX_FROM_PLL << pll_mode_shift[pll_id]); 263 264 return 0; 265 } 266 267 static uint32_t rkclk_pll_get_rate(struct px30_pll *pll, unsigned int *mode, 268 enum px30_pll_id pll_id) 269 { 270 u32 refdiv, fbdiv, postdiv1, postdiv2; 271 u32 con, shift, mask; 272 273 con = readl(mode); 274 shift = pll_mode_shift[pll_id]; 275 mask = pll_mode_mask[pll_id]; 276 277 switch ((con & mask) >> shift) { 278 case PLLMUX_FROM_XIN24M: 279 return OSC_HZ; 280 case PLLMUX_FROM_PLL: 281 /* normal mode */ 282 con = readl(&pll->con0); 283 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; 284 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; 285 con = readl(&pll->con1); 286 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; 287 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; 288 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; 289 case PLLMUX_FROM_RTC32K: 290 default: 291 return 32768; 292 } 293 } 294 295 static ulong px30_i2c_get_clk(struct px30_clk_priv *priv, ulong clk_id) 296 { 297 struct px30_cru *cru = priv->cru; 298 u32 div, con; 299 300 switch (clk_id) { 301 case SCLK_I2C0: 302 con = readl(&cru->clksel_con[49]); 303 div = con >> CLK_I2C0_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; 304 break; 305 case SCLK_I2C1: 306 con = readl(&cru->clksel_con[49]); 307 div = con >> CLK_I2C1_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; 308 break; 309 case SCLK_I2C2: 310 con = readl(&cru->clksel_con[50]); 311 div = con >> CLK_I2C2_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; 312 break; 313 case SCLK_I2C3: 314 con = readl(&cru->clksel_con[50]); 315 div = con >> CLK_I2C3_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; 316 break; 317 default: 318 printf("do not support this i2c bus\n"); 319 return -EINVAL; 320 } 321 322 return DIV_TO_RATE(priv->gpll_hz, div); 323 } 324 325 static ulong px30_i2c_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) 326 { 327 struct px30_cru *cru = priv->cru; 328 int src_clk_div; 329 330 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 331 assert(src_clk_div - 1 <= 127); 332 333 switch (clk_id) { 334 case SCLK_I2C0: 335 rk_clrsetreg(&cru->clksel_con[49], 336 CLK_I2C_DIV_CON_MASK << CLK_I2C0_DIV_CON_SHIFT | 337 CLK_I2C_PLL_SEL_MASK << CLK_I2C0_PLL_SEL_SHIFT, 338 (src_clk_div - 1) << CLK_I2C0_DIV_CON_SHIFT | 339 CLK_I2C_PLL_SEL_GPLL << CLK_I2C0_PLL_SEL_SHIFT); 340 break; 341 case SCLK_I2C1: 342 rk_clrsetreg(&cru->clksel_con[49], 343 CLK_I2C_DIV_CON_MASK << CLK_I2C1_DIV_CON_SHIFT | 344 CLK_I2C_PLL_SEL_MASK << CLK_I2C1_PLL_SEL_SHIFT, 345 (src_clk_div - 1) << CLK_I2C1_DIV_CON_SHIFT | 346 CLK_I2C_PLL_SEL_GPLL << CLK_I2C1_PLL_SEL_SHIFT); 347 break; 348 case SCLK_I2C2: 349 rk_clrsetreg(&cru->clksel_con[50], 350 CLK_I2C_DIV_CON_MASK << CLK_I2C2_DIV_CON_SHIFT | 351 CLK_I2C_PLL_SEL_MASK << CLK_I2C2_PLL_SEL_SHIFT, 352 (src_clk_div - 1) << CLK_I2C2_DIV_CON_SHIFT | 353 CLK_I2C_PLL_SEL_GPLL << CLK_I2C2_PLL_SEL_SHIFT); 354 break; 355 case SCLK_I2C3: 356 rk_clrsetreg(&cru->clksel_con[50], 357 CLK_I2C_DIV_CON_MASK << CLK_I2C3_DIV_CON_SHIFT | 358 CLK_I2C_PLL_SEL_MASK << CLK_I2C3_PLL_SEL_SHIFT, 359 (src_clk_div - 1) << CLK_I2C3_DIV_CON_SHIFT | 360 CLK_I2C_PLL_SEL_GPLL << CLK_I2C3_PLL_SEL_SHIFT); 361 break; 362 default: 363 printf("do not support this i2c bus\n"); 364 return -EINVAL; 365 } 366 367 return px30_i2c_get_clk(priv, clk_id); 368 } 369 370 /* 371 * calculate best rational approximation for a given fraction 372 * taking into account restricted register size, e.g. to find 373 * appropriate values for a pll with 5 bit denominator and 374 * 8 bit numerator register fields, trying to set up with a 375 * frequency ratio of 3.1415, one would say: 376 * 377 * rational_best_approximation(31415, 10000, 378 * (1 << 8) - 1, (1 << 5) - 1, &n, &d); 379 * 380 * you may look at given_numerator as a fixed point number, 381 * with the fractional part size described in given_denominator. 382 * 383 * for theoretical background, see: 384 * http://en.wikipedia.org/wiki/Continued_fraction 385 */ 386 static void rational_best_approximation( 387 unsigned long given_numerator, unsigned long given_denominator, 388 unsigned long max_numerator, unsigned long max_denominator, 389 unsigned long *best_numerator, unsigned long *best_denominator) 390 { 391 unsigned long n, d, n0, d0, n1, d1; 392 393 n = given_numerator; 394 d = given_denominator; 395 n0 = 0; 396 d1 = 0; 397 n1 = 1; 398 d0 = 1; 399 for (;;) { 400 unsigned long t, a; 401 402 if (n1 > max_numerator || d1 > max_denominator) { 403 n1 = n0; 404 d1 = d0; 405 break; 406 } 407 if (d == 0) 408 break; 409 t = d; 410 a = n / d; 411 d = n % d; 412 n = t; 413 t = n0 + a * n1; 414 n0 = n1; 415 n1 = t; 416 t = d0 + a * d1; 417 d0 = d1; 418 d1 = t; 419 } 420 *best_numerator = n1; 421 *best_denominator = d1; 422 } 423 424 static ulong px30_i2s_get_clk(struct px30_clk_priv *priv, ulong clk_id) 425 { 426 u32 con, fracdiv, gate; 427 u32 clk_src = GPLL_HZ / 2; 428 unsigned long m, n; 429 struct px30_cru *cru = priv->cru; 430 431 switch (clk_id) { 432 case SCLK_I2S1: 433 con = readl(&cru->clksel_con[30]); 434 fracdiv = readl(&cru->clksel_con[31]); 435 gate = readl(&cru->clkgate_con[10]); 436 m = fracdiv & CLK_I2S1_FRAC_NUMERATOR_MASK; 437 m >>= CLK_I2S1_FRAC_NUMERATOR_SHIFT; 438 n = fracdiv & CLK_I2S1_FRAC_DENOMINATOR_MASK; 439 n >>= CLK_I2S1_FRAC_DENOMINATOR_SHIFT; 440 debug("con30: 0x%x, gate: 0x%x, frac: 0x%x\n", 441 con, gate, fracdiv); 442 break; 443 default: 444 printf("do not support this i2s bus\n"); 445 return -EINVAL; 446 } 447 448 return clk_src * n / m; 449 } 450 451 static ulong px30_i2s_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) 452 { 453 u32 clk_src; 454 unsigned long m, n, val; 455 struct px30_cru *cru = priv->cru; 456 457 clk_src = GPLL_HZ / 2; 458 rational_best_approximation(hz, clk_src, 459 GENMASK(16 - 1, 0), 460 GENMASK(16 - 1, 0), 461 &m, &n); 462 switch (clk_id) { 463 case SCLK_I2S1: 464 rk_clrsetreg(&cru->clksel_con[30], 465 CLK_I2S1_PLL_SEL_MASK, CLK_I2S1_PLL_SEL_GPLL); 466 rk_clrsetreg(&cru->clksel_con[30], 467 CLK_I2S1_DIV_CON_MASK, 0x1); 468 rk_clrsetreg(&cru->clksel_con[30], 469 CLK_I2S1_SEL_MASK, CLK_I2S1_SEL_FRAC); 470 val = m << CLK_I2S1_FRAC_NUMERATOR_SHIFT | n; 471 writel(val, &cru->clksel_con[31]); 472 rk_clrsetreg(&cru->clkgate_con[10], 473 CLK_I2S1_OUT_MCLK_PAD_MASK, 474 CLK_I2S1_OUT_MCLK_PAD_ENABLE); 475 break; 476 default: 477 printf("do not support this i2s bus\n"); 478 return -EINVAL; 479 } 480 481 return px30_i2s_get_clk(priv, clk_id); 482 } 483 484 static ulong px30_nandc_get_clk(struct px30_clk_priv *priv) 485 { 486 struct px30_cru *cru = priv->cru; 487 u32 div, con; 488 489 con = readl(&cru->clksel_con[15]); 490 div = (con & NANDC_DIV_MASK) >> NANDC_DIV_SHIFT; 491 492 return DIV_TO_RATE(priv->gpll_hz, div); 493 } 494 495 static ulong px30_nandc_set_clk(struct px30_clk_priv *priv, 496 ulong set_rate) 497 { 498 struct px30_cru *cru = priv->cru; 499 int src_clk_div; 500 501 /* Select nandc source from GPLL by default */ 502 /* nandc clock defaulg div 2 internal, need provide double in cru */ 503 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, set_rate); 504 assert(src_clk_div - 1 <= 31); 505 506 rk_clrsetreg(&cru->clksel_con[15], 507 NANDC_CLK_SEL_MASK | NANDC_PLL_MASK | 508 NANDC_DIV_MASK, 509 NANDC_CLK_SEL_NANDC << NANDC_CLK_SEL_SHIFT | 510 NANDC_SEL_GPLL << NANDC_PLL_SHIFT | 511 (src_clk_div - 1) << NANDC_DIV_SHIFT); 512 513 return px30_nandc_get_clk(priv); 514 } 515 516 static ulong px30_mmc_get_clk(struct px30_clk_priv *priv, uint clk_id) 517 { 518 struct px30_cru *cru = priv->cru; 519 u32 div, con, con_id; 520 521 switch (clk_id) { 522 case HCLK_SDMMC: 523 case SCLK_SDMMC: 524 con_id = 16; 525 break; 526 case HCLK_EMMC: 527 case SCLK_EMMC: 528 case SCLK_EMMC_SAMPLE: 529 con_id = 20; 530 break; 531 default: 532 return -EINVAL; 533 } 534 535 con = readl(&cru->clksel_con[con_id]); 536 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; 537 538 if ((con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT 539 == EMMC_SEL_24M) 540 return DIV_TO_RATE(OSC_HZ, div) / 2; 541 else 542 return DIV_TO_RATE(priv->gpll_hz, div) / 2; 543 544 } 545 546 static ulong px30_mmc_set_clk(struct px30_clk_priv *priv, 547 ulong clk_id, ulong set_rate) 548 { 549 struct px30_cru *cru = priv->cru; 550 int src_clk_div; 551 u32 con_id; 552 553 switch (clk_id) { 554 case HCLK_SDMMC: 555 case SCLK_SDMMC: 556 con_id = 16; 557 break; 558 case HCLK_EMMC: 559 case SCLK_EMMC: 560 con_id = 20; 561 break; 562 default: 563 return -EINVAL; 564 } 565 566 /* Select clk_sdmmc/emmc source from GPLL by default */ 567 /* mmc clock defaulg div 2 internal, need provide double in cru */ 568 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, set_rate); 569 570 if (src_clk_div > 127) { 571 /* use 24MHz source for 400KHz clock */ 572 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); 573 rk_clrsetreg(&cru->clksel_con[con_id], 574 EMMC_PLL_MASK | EMMC_DIV_MASK, 575 EMMC_SEL_24M << EMMC_PLL_SHIFT | 576 (src_clk_div - 1) << EMMC_DIV_SHIFT); 577 } else { 578 rk_clrsetreg(&cru->clksel_con[con_id], 579 EMMC_PLL_MASK | EMMC_DIV_MASK, 580 EMMC_SEL_GPLL << EMMC_PLL_SHIFT | 581 (src_clk_div - 1) << EMMC_DIV_SHIFT); 582 } 583 rk_clrsetreg(&cru->clksel_con[con_id +1], EMMC_CLK_SEL_MASK, 584 EMMC_CLK_SEL_EMMC); 585 586 return px30_mmc_get_clk(priv, clk_id); 587 } 588 589 static ulong px30_pwm_get_clk(struct px30_clk_priv *priv, ulong clk_id) 590 { 591 struct px30_cru *cru = priv->cru; 592 u32 div, con; 593 594 switch (clk_id) { 595 case SCLK_PWM0: 596 con = readl(&cru->clksel_con[52]); 597 div = con >> CLK_PWM0_DIV_CON_SHIFT & CLK_PWM_DIV_CON_MASK; 598 break; 599 case SCLK_PWM1: 600 con = readl(&cru->clksel_con[52]); 601 div = con >> CLK_PWM1_DIV_CON_SHIFT & CLK_PWM_DIV_CON_MASK; 602 break; 603 default: 604 printf("do not support this pwm bus\n"); 605 return -EINVAL; 606 } 607 608 return DIV_TO_RATE(priv->gpll_hz, div); 609 } 610 611 static ulong px30_pwm_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) 612 { 613 struct px30_cru *cru = priv->cru; 614 int src_clk_div; 615 616 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 617 assert(src_clk_div - 1 <= 127); 618 619 switch (clk_id) { 620 case SCLK_PWM0: 621 rk_clrsetreg(&cru->clksel_con[52], 622 CLK_PWM_DIV_CON_MASK << CLK_PWM0_DIV_CON_SHIFT | 623 CLK_PWM_PLL_SEL_MASK << CLK_PWM0_PLL_SEL_SHIFT, 624 (src_clk_div - 1) << CLK_PWM0_DIV_CON_SHIFT | 625 CLK_PWM_PLL_SEL_GPLL << CLK_PWM0_PLL_SEL_SHIFT); 626 break; 627 case SCLK_PWM1: 628 rk_clrsetreg(&cru->clksel_con[52], 629 CLK_PWM_DIV_CON_MASK << CLK_PWM1_DIV_CON_SHIFT | 630 CLK_PWM_PLL_SEL_MASK << CLK_PWM1_PLL_SEL_SHIFT, 631 (src_clk_div - 1) << CLK_PWM1_DIV_CON_SHIFT | 632 CLK_PWM_PLL_SEL_GPLL << CLK_PWM1_PLL_SEL_SHIFT); 633 break; 634 default: 635 printf("do not support this pwm bus\n"); 636 return -EINVAL; 637 } 638 639 return px30_pwm_get_clk(priv, clk_id); 640 } 641 642 static ulong px30_saradc_get_clk(struct px30_clk_priv *priv) 643 { 644 struct px30_cru *cru = priv->cru; 645 u32 div, con; 646 647 con = readl(&cru->clksel_con[55]); 648 div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK; 649 650 return DIV_TO_RATE(OSC_HZ, div); 651 } 652 653 static ulong px30_saradc_set_clk(struct px30_clk_priv *priv, uint hz) 654 { 655 struct px30_cru *cru = priv->cru; 656 int src_clk_div; 657 658 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); 659 assert(src_clk_div - 1 <= 2047); 660 661 rk_clrsetreg(&cru->clksel_con[55], 662 CLK_SARADC_DIV_CON_MASK, 663 (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT); 664 665 return px30_saradc_get_clk(priv); 666 } 667 668 static ulong px30_tsadc_get_clk(struct px30_clk_priv *priv) 669 { 670 struct px30_cru *cru = priv->cru; 671 u32 div, con; 672 673 con = readl(&cru->clksel_con[54]); 674 div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK; 675 676 return DIV_TO_RATE(OSC_HZ, div); 677 } 678 679 static ulong px30_tsadc_set_clk(struct px30_clk_priv *priv, uint hz) 680 { 681 struct px30_cru *cru = priv->cru; 682 int src_clk_div; 683 684 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); 685 assert(src_clk_div - 1 <= 2047); 686 687 rk_clrsetreg(&cru->clksel_con[54], 688 CLK_SARADC_DIV_CON_MASK, 689 (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT); 690 691 return px30_tsadc_get_clk(priv); 692 } 693 694 static ulong px30_spi_get_clk(struct px30_clk_priv *priv, ulong clk_id) 695 { 696 struct px30_cru *cru = priv->cru; 697 u32 div, con; 698 699 switch (clk_id) { 700 case SCLK_SPI0: 701 con = readl(&cru->clksel_con[53]); 702 div = con >> CLK_SPI0_DIV_CON_SHIFT & CLK_SPI_DIV_CON_MASK; 703 break; 704 case SCLK_SPI1: 705 con = readl(&cru->clksel_con[53]); 706 div = con >> CLK_SPI1_DIV_CON_SHIFT & CLK_SPI_DIV_CON_MASK; 707 break; 708 default: 709 printf("do not support this pwm bus\n"); 710 return -EINVAL; 711 } 712 713 return DIV_TO_RATE(priv->gpll_hz, div); 714 } 715 716 static ulong px30_spi_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) 717 { 718 struct px30_cru *cru = priv->cru; 719 int src_clk_div; 720 721 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 722 assert(src_clk_div - 1 <= 127); 723 724 switch (clk_id) { 725 case SCLK_SPI0: 726 rk_clrsetreg(&cru->clksel_con[53], 727 CLK_SPI_DIV_CON_MASK << CLK_SPI0_DIV_CON_SHIFT | 728 CLK_SPI_PLL_SEL_MASK << CLK_SPI0_PLL_SEL_SHIFT, 729 (src_clk_div - 1) << CLK_SPI0_DIV_CON_SHIFT | 730 CLK_SPI_PLL_SEL_GPLL << CLK_SPI0_PLL_SEL_SHIFT); 731 break; 732 case SCLK_SPI1: 733 rk_clrsetreg(&cru->clksel_con[53], 734 CLK_SPI_DIV_CON_MASK << CLK_SPI1_DIV_CON_SHIFT | 735 CLK_SPI_PLL_SEL_MASK << CLK_SPI1_PLL_SEL_SHIFT, 736 (src_clk_div - 1) << CLK_SPI1_DIV_CON_SHIFT | 737 CLK_SPI_PLL_SEL_GPLL << CLK_SPI1_PLL_SEL_SHIFT); 738 break; 739 default: 740 printf("do not support this pwm bus\n"); 741 return -EINVAL; 742 } 743 744 return px30_spi_get_clk(priv, clk_id); 745 } 746 747 static ulong px30_vop_get_clk(struct px30_clk_priv *priv, ulong clk_id) 748 { 749 struct px30_cru *cru = priv->cru; 750 u32 div, con, parent; 751 752 switch (clk_id) { 753 case ACLK_VOPB: 754 case ACLK_VOPL: 755 con = readl(&cru->clksel_con[3]); 756 div = con & ACLK_VO_DIV_MASK; 757 parent = priv->gpll_hz; 758 break; 759 case DCLK_VOPB: 760 con = readl(&cru->clksel_con[5]); 761 div = con & DCLK_VOPB_DIV_MASK; 762 parent = rkclk_pll_get_rate(&cru->pll[CPLL], &cru->mode, CPLL); 763 break; 764 case DCLK_VOPL: 765 con = readl(&cru->clksel_con[8]); 766 div = con & DCLK_VOPL_DIV_MASK; 767 parent = rkclk_pll_get_rate(&cru->pll[NPLL], &cru->mode, NPLL); 768 break; 769 default: 770 return -ENOENT; 771 } 772 773 return DIV_TO_RATE(parent, div); 774 } 775 776 static ulong px30_vop_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) 777 { 778 struct px30_cru *cru = priv->cru; 779 ulong npll_hz; 780 int src_clk_div; 781 782 switch (clk_id) { 783 case ACLK_VOPB: 784 case ACLK_VOPL: 785 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 786 assert(src_clk_div - 1 <= 31); 787 rk_clrsetreg(&cru->clksel_con[3], 788 ACLK_VO_PLL_MASK | ACLK_VO_DIV_MASK, 789 ACLK_VO_SEL_GPLL << ACLK_VO_PLL_SHIFT | 790 (src_clk_div - 1) << ACLK_VO_DIV_SHIFT); 791 break; 792 case DCLK_VOPB: 793 if (hz < PX30_VOP_PLL_LIMIT) 794 src_clk_div = DIV_ROUND_UP(PX30_VOP_PLL_LIMIT, hz); 795 else 796 src_clk_div = 1; 797 assert(src_clk_div - 1 <= 255); 798 rkclk_set_pll(&cru->pll[CPLL], &cru->mode, CPLL, hz * src_clk_div); 799 rk_clrsetreg(&cru->clksel_con[5], 800 DCLK_VOPB_SEL_MASK | DCLK_VOPB_PLL_SEL_MASK | 801 DCLK_VOPB_DIV_MASK, 802 DCLK_VOPB_SEL_DIVOUT << DCLK_VOPB_SEL_SHIFT | 803 DCLK_VOPB_PLL_SEL_CPLL << DCLK_VOPB_PLL_SEL_SHIFT | 804 (src_clk_div - 1) << DCLK_VOPB_DIV_SHIFT); 805 break; 806 case DCLK_VOPL: 807 npll_hz = px30_clk_get_pll_rate(priv, NPLL); 808 if (npll_hz >= PX30_VOP_PLL_LIMIT && npll_hz >= hz && npll_hz % hz == 0) { 809 src_clk_div = npll_hz / hz; 810 assert(src_clk_div - 1 <= 255); 811 } else { 812 if (hz < PX30_VOP_PLL_LIMIT) 813 src_clk_div = DIV_ROUND_UP(PX30_VOP_PLL_LIMIT, hz); 814 else 815 src_clk_div = 1; 816 assert(src_clk_div - 1 <= 255); 817 rkclk_set_pll(&cru->pll[NPLL], &cru->mode, NPLL, hz * src_clk_div); 818 } 819 rk_clrsetreg(&cru->clksel_con[8], 820 DCLK_VOPL_SEL_MASK | DCLK_VOPL_PLL_SEL_MASK | 821 DCLK_VOPL_DIV_MASK, 822 DCLK_VOPL_SEL_DIVOUT << DCLK_VOPL_SEL_SHIFT | 823 DCLK_VOPL_PLL_SEL_NPLL << DCLK_VOPL_PLL_SEL_SHIFT | 824 (src_clk_div - 1) << DCLK_VOPL_DIV_SHIFT); 825 break; 826 default: 827 printf("do not support this vop freq\n"); 828 return -EINVAL; 829 } 830 831 return px30_vop_get_clk(priv, clk_id); 832 } 833 834 static ulong px30_bus_get_clk(struct px30_clk_priv *priv, ulong clk_id) 835 { 836 struct px30_cru *cru = priv->cru; 837 u32 div, con, parent; 838 839 switch (clk_id) { 840 case ACLK_BUS_PRE: 841 con = readl(&cru->clksel_con[23]); 842 div = (con & BUS_ACLK_DIV_MASK) >> BUS_ACLK_DIV_SHIFT; 843 parent = priv->gpll_hz; 844 break; 845 case HCLK_BUS_PRE: 846 con = readl(&cru->clksel_con[24]); 847 div = (con & BUS_HCLK_DIV_MASK) >> BUS_HCLK_DIV_SHIFT; 848 parent = priv->gpll_hz; 849 break; 850 case PCLK_BUS_PRE: 851 parent = px30_bus_get_clk(priv, ACLK_BUS_PRE); 852 con = readl(&cru->clksel_con[24]); 853 div = (con & BUS_PCLK_DIV_MASK) >> BUS_PCLK_DIV_SHIFT; 854 break; 855 default: 856 return -ENOENT; 857 } 858 859 return DIV_TO_RATE(parent, div); 860 } 861 862 static ulong px30_bus_set_clk(struct px30_clk_priv *priv, ulong clk_id, 863 ulong hz) 864 { 865 struct px30_cru *cru = priv->cru; 866 int src_clk_div; 867 868 /* 869 * select gpll as pd_bus bus clock source and 870 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 871 */ 872 switch (clk_id) { 873 case ACLK_BUS_PRE: 874 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 875 assert(src_clk_div - 1 <= 31); 876 rk_clrsetreg(&cru->clksel_con[23], 877 BUS_PLL_SEL_MASK | BUS_ACLK_DIV_MASK, 878 BUS_PLL_SEL_GPLL << BUS_PLL_SEL_SHIFT | 879 (src_clk_div - 1) << BUS_ACLK_DIV_SHIFT); 880 break; 881 case HCLK_BUS_PRE: 882 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 883 assert(src_clk_div - 1 <= 31); 884 rk_clrsetreg(&cru->clksel_con[24], 885 BUS_PLL_SEL_MASK | BUS_HCLK_DIV_MASK, 886 BUS_PLL_SEL_GPLL << BUS_PLL_SEL_SHIFT | 887 (src_clk_div - 1) << BUS_HCLK_DIV_SHIFT); 888 break; 889 case PCLK_BUS_PRE: 890 src_clk_div = 891 DIV_ROUND_UP(px30_bus_get_clk(priv, ACLK_BUS_PRE), hz); 892 assert(src_clk_div - 1 <= 3); 893 rk_clrsetreg(&cru->clksel_con[24], 894 BUS_PCLK_DIV_MASK, 895 (src_clk_div - 1) << BUS_PCLK_DIV_SHIFT); 896 break; 897 default: 898 printf("do not support this bus freq\n"); 899 return -EINVAL; 900 } 901 902 return px30_bus_get_clk(priv, clk_id); 903 } 904 905 static ulong px30_peri_get_clk(struct px30_clk_priv *priv, ulong clk_id) 906 { 907 struct px30_cru *cru = priv->cru; 908 u32 div, con, parent; 909 910 switch (clk_id) { 911 case ACLK_PERI_PRE: 912 con = readl(&cru->clksel_con[14]); 913 div = (con & PERI_ACLK_DIV_MASK) >> PERI_ACLK_DIV_SHIFT; 914 parent = priv->gpll_hz; 915 break; 916 case HCLK_PERI_PRE: 917 con = readl(&cru->clksel_con[14]); 918 div = (con & PERI_HCLK_DIV_MASK) >> PERI_HCLK_DIV_SHIFT; 919 parent = priv->gpll_hz; 920 break; 921 default: 922 return -ENOENT; 923 } 924 925 return DIV_TO_RATE(parent, div); 926 } 927 928 static ulong px30_peri_set_clk(struct px30_clk_priv *priv, ulong clk_id, 929 ulong hz) 930 { 931 struct px30_cru *cru = priv->cru; 932 int src_clk_div; 933 934 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 935 assert(src_clk_div - 1 <= 31); 936 937 /* 938 * select gpll as pd_peri bus clock source and 939 * set up dependent divisors for HCLK and ACLK clocks. 940 */ 941 switch (clk_id) { 942 case ACLK_PERI_PRE: 943 rk_clrsetreg(&cru->clksel_con[14], 944 PERI_PLL_SEL_MASK | PERI_ACLK_DIV_MASK, 945 PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT | 946 (src_clk_div - 1) << PERI_ACLK_DIV_SHIFT); 947 break; 948 case HCLK_PERI_PRE: 949 rk_clrsetreg(&cru->clksel_con[14], 950 PERI_PLL_SEL_MASK | PERI_HCLK_DIV_MASK, 951 PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT | 952 (src_clk_div - 1) << PERI_HCLK_DIV_SHIFT); 953 break; 954 default: 955 printf("do not support this peri freq\n"); 956 return -EINVAL; 957 } 958 959 return px30_peri_get_clk(priv, clk_id); 960 } 961 962 static int px30_clk_get_gpll_rate(ulong *rate) 963 { 964 struct udevice *pmucru_dev; 965 struct px30_pmuclk_priv *priv; 966 int ret; 967 968 ret = uclass_get_device_by_driver(UCLASS_CLK, 969 DM_GET_DRIVER(rockchip_px30_pmucru), 970 &pmucru_dev); 971 if (ret) { 972 printf("%s: could not find pmucru device\n", __func__); 973 return ret; 974 } 975 priv = dev_get_priv(pmucru_dev); 976 *rate = priv->gpll_hz; 977 978 return 0; 979 } 980 981 static ulong px30_clk_get_pll_rate(struct px30_clk_priv *priv, 982 enum px30_pll_id pll_id) 983 { 984 struct px30_cru *cru = priv->cru; 985 986 return rkclk_pll_get_rate(&cru->pll[pll_id], &cru->mode, pll_id); 987 } 988 989 static ulong px30_clk_set_pll_rate(struct px30_clk_priv *priv, 990 enum px30_pll_id pll_id, ulong hz) 991 { 992 struct px30_cru *cru = priv->cru; 993 994 if (rkclk_set_pll(&cru->pll[pll_id], &cru->mode, pll_id, hz)) 995 return -EINVAL; 996 return rkclk_pll_get_rate(&cru->pll[pll_id], &cru->mode, pll_id); 997 } 998 999 static ulong px30_armclk_set_clk(struct px30_clk_priv *priv, ulong hz) 1000 { 1001 struct px30_cru *cru = priv->cru; 1002 const struct cpu_rate_table *rate; 1003 ulong old_rate; 1004 1005 rate = get_cpu_settings(hz); 1006 if (!rate) { 1007 printf("%s unsupport rate\n", __func__); 1008 return -EINVAL; 1009 } 1010 1011 /* 1012 * select apll as cpu/core clock pll source and 1013 * set up dependent divisors for PERI and ACLK clocks. 1014 * core hz : apll = 1:1 1015 */ 1016 old_rate = px30_clk_get_pll_rate(priv, APLL); 1017 if (old_rate > hz) { 1018 if (rkclk_set_pll(&cru->pll[APLL], &cru->mode, APLL, hz)) 1019 return -EINVAL; 1020 rk_clrsetreg(&cru->clksel_con[0], 1021 CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK | 1022 CORE_ACLK_DIV_MASK | CORE_DBG_DIV_MASK, 1023 rate->aclk_div << CORE_ACLK_DIV_SHIFT | 1024 rate->pclk_div << CORE_DBG_DIV_SHIFT | 1025 CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT | 1026 0 << CORE_DIV_CON_SHIFT); 1027 } else if (old_rate < hz) { 1028 rk_clrsetreg(&cru->clksel_con[0], 1029 CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK | 1030 CORE_ACLK_DIV_MASK | CORE_DBG_DIV_MASK, 1031 rate->aclk_div << CORE_ACLK_DIV_SHIFT | 1032 rate->pclk_div << CORE_DBG_DIV_SHIFT | 1033 CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT | 1034 0 << CORE_DIV_CON_SHIFT); 1035 if (rkclk_set_pll(&cru->pll[APLL], &cru->mode, APLL, hz)) 1036 return -EINVAL; 1037 } 1038 1039 return px30_clk_get_pll_rate(priv, APLL); 1040 } 1041 1042 static ulong px30_clk_get_rate(struct clk *clk) 1043 { 1044 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 1045 ulong rate = 0; 1046 1047 if (!priv->gpll_hz && clk->id > ARMCLK) { 1048 printf("%s gpll=%lu\n", __func__, priv->gpll_hz); 1049 return -ENOENT; 1050 } 1051 1052 debug("%s %ld\n", __func__, clk->id); 1053 switch (clk->id) { 1054 case PLL_APLL: 1055 rate = px30_clk_get_pll_rate(priv, APLL); 1056 break; 1057 case PLL_DPLL: 1058 rate = px30_clk_get_pll_rate(priv, DPLL); 1059 break; 1060 case PLL_CPLL: 1061 rate = px30_clk_get_pll_rate(priv, CPLL); 1062 break; 1063 case PLL_NPLL: 1064 rate = px30_clk_get_pll_rate(priv, NPLL); 1065 break; 1066 case ARMCLK: 1067 rate = px30_clk_get_pll_rate(priv, APLL); 1068 break; 1069 case HCLK_SDMMC: 1070 case HCLK_EMMC: 1071 case SCLK_SDMMC: 1072 case SCLK_EMMC: 1073 case SCLK_EMMC_SAMPLE: 1074 rate = px30_mmc_get_clk(priv, clk->id); 1075 break; 1076 case SCLK_I2C0: 1077 case SCLK_I2C1: 1078 case SCLK_I2C2: 1079 case SCLK_I2C3: 1080 rate = px30_i2c_get_clk(priv, clk->id); 1081 break; 1082 case SCLK_I2S1: 1083 rate = px30_i2s_get_clk(priv, clk->id); 1084 break; 1085 case SCLK_PWM0: 1086 case SCLK_PWM1: 1087 rate = px30_pwm_get_clk(priv, clk->id); 1088 break; 1089 case SCLK_SARADC: 1090 rate = px30_saradc_get_clk(priv); 1091 break; 1092 case SCLK_TSADC: 1093 rate = px30_tsadc_get_clk(priv); 1094 break; 1095 case SCLK_SPI0: 1096 case SCLK_SPI1: 1097 rate = px30_spi_get_clk(priv, clk->id); 1098 break; 1099 case ACLK_VOPB: 1100 case ACLK_VOPL: 1101 case DCLK_VOPB: 1102 case DCLK_VOPL: 1103 rate = px30_vop_get_clk(priv, clk->id); 1104 break; 1105 case ACLK_BUS_PRE: 1106 case HCLK_BUS_PRE: 1107 case PCLK_BUS_PRE: 1108 rate = px30_bus_get_clk(priv, clk->id); 1109 break; 1110 case ACLK_PERI_PRE: 1111 case HCLK_PERI_PRE: 1112 rate = px30_peri_get_clk(priv, clk->id); 1113 break; 1114 default: 1115 return -ENOENT; 1116 } 1117 1118 return rate; 1119 } 1120 1121 static ulong px30_clk_set_rate(struct clk *clk, ulong rate) 1122 { 1123 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 1124 ulong ret = 0; 1125 1126 if (!priv->gpll_hz && clk->id > ARMCLK) { 1127 printf("%s gpll=%lu\n", __func__, priv->gpll_hz); 1128 return -ENOENT; 1129 } 1130 1131 debug("%s %ld %ld\n", __func__, clk->id, rate); 1132 switch (clk->id) { 1133 case PLL_NPLL: 1134 ret = px30_clk_set_pll_rate(priv, NPLL, rate); 1135 break; 1136 case ARMCLK: 1137 if (priv->armclk_hz) 1138 px30_armclk_set_clk(priv, rate); 1139 priv->armclk_hz = rate; 1140 break; 1141 case HCLK_SDMMC: 1142 case HCLK_EMMC: 1143 case SCLK_SDMMC: 1144 case SCLK_EMMC: 1145 ret = px30_mmc_set_clk(priv, clk->id, rate); 1146 break; 1147 case SCLK_I2C0: 1148 case SCLK_I2C1: 1149 case SCLK_I2C2: 1150 case SCLK_I2C3: 1151 ret = px30_i2c_set_clk(priv, clk->id, rate); 1152 break; 1153 case SCLK_I2S1: 1154 ret = px30_i2s_set_clk(priv, clk->id, rate); 1155 break; 1156 case SCLK_PWM0: 1157 case SCLK_PWM1: 1158 ret = px30_pwm_set_clk(priv, clk->id, rate); 1159 break; 1160 case SCLK_SARADC: 1161 ret = px30_saradc_set_clk(priv, rate); 1162 break; 1163 case SCLK_TSADC: 1164 ret = px30_tsadc_set_clk(priv, rate); 1165 break; 1166 case SCLK_SPI0: 1167 case SCLK_SPI1: 1168 ret = px30_spi_set_clk(priv, clk->id, rate); 1169 break; 1170 case ACLK_VOPB: 1171 case ACLK_VOPL: 1172 case DCLK_VOPB: 1173 case DCLK_VOPL: 1174 ret = px30_vop_set_clk(priv, clk->id, rate); 1175 break; 1176 case ACLK_BUS_PRE: 1177 case HCLK_BUS_PRE: 1178 case PCLK_BUS_PRE: 1179 ret = px30_bus_set_clk(priv, clk->id, rate); 1180 break; 1181 case ACLK_PERI_PRE: 1182 case HCLK_PERI_PRE: 1183 ret = px30_peri_set_clk(priv, clk->id, rate); 1184 break; 1185 default: 1186 return -ENOENT; 1187 } 1188 1189 return ret; 1190 } 1191 1192 #define ROCKCHIP_MMC_DELAY_SEL BIT(10) 1193 #define ROCKCHIP_MMC_DEGREE_MASK 0x3 1194 #define ROCKCHIP_MMC_DELAYNUM_OFFSET 2 1195 #define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET) 1196 1197 #define PSECS_PER_SEC 1000000000000LL 1198 /* 1199 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to 1200 * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg. 1201 */ 1202 #define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60 1203 1204 int rockchip_mmc_get_phase(struct clk *clk) 1205 { 1206 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 1207 struct px30_cru *cru = priv->cru; 1208 u32 raw_value, delay_num; 1209 u16 degrees = 0; 1210 ulong rate; 1211 1212 rate = px30_clk_get_rate(clk); 1213 1214 if (rate < 0) 1215 return rate; 1216 1217 if (clk->id == SCLK_EMMC_SAMPLE) 1218 raw_value = readl(&cru->emmc_con[1]); 1219 else 1220 raw_value = readl(&cru->sdmmc_con[1]); 1221 1222 raw_value >>= 1; 1223 degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90; 1224 1225 if (raw_value & ROCKCHIP_MMC_DELAY_SEL) { 1226 /* degrees/delaynum * 10000 */ 1227 unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) * 1228 36 * (rate / 1000000); 1229 1230 delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK); 1231 delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET; 1232 degrees += DIV_ROUND_CLOSEST(delay_num * factor, 10000); 1233 } 1234 1235 return degrees % 360; 1236 } 1237 1238 int rockchip_mmc_set_phase(struct clk *clk, u32 degrees) 1239 { 1240 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 1241 struct px30_cru *cru = priv->cru; 1242 u8 nineties, remainder, delay_num; 1243 u32 raw_value, delay; 1244 ulong rate; 1245 1246 rate = px30_clk_get_rate(clk); 1247 1248 if (rate < 0) 1249 return rate; 1250 1251 nineties = degrees / 90; 1252 remainder = (degrees % 90); 1253 1254 /* 1255 * Convert to delay; do a little extra work to make sure we 1256 * don't overflow 32-bit / 64-bit numbers. 1257 */ 1258 delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */ 1259 delay *= remainder; 1260 delay = DIV_ROUND_CLOSEST(delay, (rate / 1000) * 36 * 1261 (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10)); 1262 1263 delay_num = (u8)min_t(u32, delay, 255); 1264 1265 raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0; 1266 raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET; 1267 raw_value |= nineties; 1268 1269 raw_value <<= 1; 1270 if (clk->id == SCLK_EMMC_SAMPLE) 1271 writel(raw_value | 0xffff0000, &cru->emmc_con[1]); 1272 else 1273 writel(raw_value | 0xffff0000, &cru->sdmmc_con[1]); 1274 1275 debug("mmc set_phase(%d) delay_nums=%u reg=%#x actual_degrees=%d\n", 1276 degrees, delay_num, raw_value, rockchip_mmc_get_phase(clk)); 1277 1278 return 0; 1279 } 1280 1281 static int px30_clk_get_phase(struct clk *clk) 1282 { 1283 int ret; 1284 1285 debug("%s %ld\n", __func__, clk->id); 1286 switch (clk->id) { 1287 case SCLK_EMMC_SAMPLE: 1288 case SCLK_SDMMC_SAMPLE: 1289 ret = rockchip_mmc_get_phase(clk); 1290 break; 1291 default: 1292 return -ENOENT; 1293 } 1294 1295 return ret; 1296 } 1297 1298 static int px30_clk_set_phase(struct clk *clk, int degrees) 1299 { 1300 int ret; 1301 1302 debug("%s %ld\n", __func__, clk->id); 1303 switch (clk->id) { 1304 case SCLK_EMMC_SAMPLE: 1305 case SCLK_SDMMC_SAMPLE: 1306 ret = rockchip_mmc_set_phase(clk, degrees); 1307 break; 1308 default: 1309 return -ENOENT; 1310 } 1311 1312 return ret; 1313 } 1314 1315 static struct clk_ops px30_clk_ops = { 1316 .get_rate = px30_clk_get_rate, 1317 .set_rate = px30_clk_set_rate, 1318 .get_phase = px30_clk_get_phase, 1319 .set_phase = px30_clk_set_phase, 1320 }; 1321 1322 static int px30_clk_probe(struct udevice *dev) 1323 { 1324 struct px30_clk_priv *priv = dev_get_priv(dev); 1325 int ret; 1326 1327 if (px30_clk_get_pll_rate(priv, APLL) != APLL_HZ) { 1328 ret = px30_armclk_set_clk(priv, APLL_HZ); 1329 if (ret < 0) 1330 printf("%s failed to set armclk rate\n", __func__); 1331 } 1332 1333 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 1334 ret = clk_set_defaults(dev); 1335 if (ret) 1336 debug("%s clk_set_defaults failed %d\n", __func__, ret); 1337 1338 if (!priv->gpll_hz) { 1339 ret = px30_clk_get_gpll_rate(&priv->gpll_hz); 1340 if (ret) { 1341 printf("%s failed to get gpll rate\n", __func__); 1342 return ret; 1343 } 1344 } 1345 1346 return 0; 1347 } 1348 1349 static int px30_clk_ofdata_to_platdata(struct udevice *dev) 1350 { 1351 struct px30_clk_priv *priv = dev_get_priv(dev); 1352 1353 priv->cru = dev_read_addr_ptr(dev); 1354 1355 return 0; 1356 } 1357 1358 static int px30_clk_bind(struct udevice *dev) 1359 { 1360 int ret; 1361 struct udevice *sys_child, *sf_child; 1362 struct sysreset_reg *priv; 1363 struct softreset_reg *sf_priv; 1364 1365 /* The reset driver does not have a device node, so bind it here */ 1366 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", 1367 &sys_child); 1368 if (ret) { 1369 debug("Warning: No sysreset driver: ret=%d\n", ret); 1370 } else { 1371 priv = malloc(sizeof(struct sysreset_reg)); 1372 priv->glb_srst_fst_value = offsetof(struct px30_cru, 1373 glb_srst_fst); 1374 priv->glb_srst_snd_value = offsetof(struct px30_cru, 1375 glb_srst_snd); 1376 sys_child->priv = priv; 1377 } 1378 1379 ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset", 1380 dev_ofnode(dev), &sf_child); 1381 if (ret) { 1382 debug("Warning: No rockchip reset driver: ret=%d\n", ret); 1383 } else { 1384 sf_priv = malloc(sizeof(struct softreset_reg)); 1385 sf_priv->sf_reset_offset = offsetof(struct px30_cru, 1386 softrst_con[0]); 1387 sf_priv->sf_reset_num = 12; 1388 sf_child->priv = sf_priv; 1389 } 1390 1391 return 0; 1392 } 1393 1394 static const struct udevice_id px30_clk_ids[] = { 1395 { .compatible = "rockchip,px30-cru" }, 1396 { } 1397 }; 1398 1399 U_BOOT_DRIVER(rockchip_px30_cru) = { 1400 .name = "rockchip_px30_cru", 1401 .id = UCLASS_CLK, 1402 .of_match = px30_clk_ids, 1403 .priv_auto_alloc_size = sizeof(struct px30_clk_priv), 1404 .ofdata_to_platdata = px30_clk_ofdata_to_platdata, 1405 .ops = &px30_clk_ops, 1406 .bind = px30_clk_bind, 1407 .probe = px30_clk_probe, 1408 }; 1409 1410 static ulong px30_pclk_pmu_get_pmuclk(struct px30_pmuclk_priv *priv) 1411 { 1412 struct px30_pmucru *pmucru = priv->pmucru; 1413 u32 div, con; 1414 1415 con = readl(&pmucru->pmu_clksel_con[0]); 1416 div = (con & CLK_PMU_PCLK_DIV_MASK) >> CLK_PMU_PCLK_DIV_SHIFT; 1417 1418 return DIV_TO_RATE(priv->gpll_hz, div); 1419 } 1420 1421 static ulong px30_pclk_pmu_set_pmuclk(struct px30_pmuclk_priv *priv, ulong hz) 1422 { 1423 struct px30_pmucru *pmucru = priv->pmucru; 1424 int src_clk_div; 1425 1426 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 1427 assert(src_clk_div - 1 <= 31); 1428 1429 rk_clrsetreg(&pmucru->pmu_clksel_con[0], 1430 CLK_PMU_PCLK_DIV_MASK, 1431 (src_clk_div - 1) << CLK_PMU_PCLK_DIV_SHIFT); 1432 1433 return px30_pclk_pmu_get_pmuclk(priv); 1434 } 1435 1436 static ulong px30_gpll_get_pmuclk(struct px30_pmuclk_priv *priv) 1437 { 1438 struct px30_pmucru *pmucru = priv->pmucru; 1439 1440 return rkclk_pll_get_rate(&pmucru->pll, &pmucru->pmu_mode, GPLL); 1441 } 1442 1443 static ulong px30_gpll_set_pmuclk(struct px30_pmuclk_priv *priv, ulong hz) 1444 { 1445 struct udevice *cru_dev; 1446 struct px30_clk_priv *cru_priv; 1447 struct px30_pmucru *pmucru = priv->pmucru; 1448 u32 div; 1449 ulong emmc_rate, sdmmc_rate, nandc_rate; 1450 ulong aclk_bus_rate, hclk_bus_rate, pclk_bus_rate; 1451 ulong aclk_peri_rate, hclk_peri_rate, pclk_pmu_rate; 1452 int ret; 1453 1454 ret = uclass_get_device_by_name(UCLASS_CLK, 1455 "clock-controller@ff2b0000", 1456 &cru_dev); 1457 if (ret) { 1458 printf("%s failed to get cru device\n", __func__); 1459 return ret; 1460 } 1461 cru_priv = dev_get_priv(cru_dev); 1462 1463 if (priv->gpll_hz == hz) 1464 return priv->gpll_hz; 1465 1466 cru_priv->gpll_hz = priv->gpll_hz; 1467 div = DIV_ROUND_UP(hz, priv->gpll_hz); 1468 1469 /* save clock rate */ 1470 aclk_bus_rate = px30_bus_get_clk(cru_priv, ACLK_BUS_PRE); 1471 hclk_bus_rate = px30_bus_get_clk(cru_priv, HCLK_BUS_PRE); 1472 pclk_bus_rate = px30_bus_get_clk(cru_priv, PCLK_BUS_PRE); 1473 aclk_peri_rate = px30_peri_get_clk(cru_priv, ACLK_PERI_PRE); 1474 hclk_peri_rate = px30_peri_get_clk(cru_priv, HCLK_PERI_PRE); 1475 pclk_pmu_rate = px30_pclk_pmu_get_pmuclk(priv); 1476 debug("%s aclk_bus=%lu, hclk_bus=%lu, pclk_bus=%lu\n", __func__, 1477 aclk_bus_rate, hclk_bus_rate, pclk_bus_rate); 1478 debug("%s aclk_peri=%lu, hclk_peri=%lu, pclk_pmu=%lu\n", __func__, 1479 aclk_peri_rate, hclk_peri_rate, pclk_pmu_rate); 1480 emmc_rate = px30_mmc_get_clk(cru_priv, SCLK_EMMC); 1481 sdmmc_rate = px30_mmc_get_clk(cru_priv, SCLK_SDMMC); 1482 nandc_rate = px30_nandc_get_clk(cru_priv); 1483 debug("%s emmc=%lu, sdmmc=%lu, nandc=%lu\n", __func__, 1484 emmc_rate, sdmmc_rate, nandc_rate); 1485 1486 /* avoid rate too large, reduce rate first */ 1487 px30_bus_set_clk(cru_priv, ACLK_BUS_PRE, aclk_bus_rate / div); 1488 px30_bus_set_clk(cru_priv, HCLK_BUS_PRE, hclk_bus_rate / div); 1489 px30_bus_set_clk(cru_priv, PCLK_BUS_PRE, pclk_bus_rate / div); 1490 px30_peri_set_clk(cru_priv, ACLK_PERI_PRE, aclk_peri_rate / div); 1491 px30_peri_set_clk(cru_priv, HCLK_PERI_PRE, hclk_peri_rate / div); 1492 px30_pclk_pmu_set_pmuclk(priv, pclk_pmu_rate / div); 1493 1494 px30_mmc_set_clk(cru_priv, SCLK_EMMC, emmc_rate / div); 1495 px30_mmc_set_clk(cru_priv, SCLK_SDMMC, sdmmc_rate / div); 1496 px30_nandc_set_clk(cru_priv, nandc_rate / div); 1497 1498 /* change gpll rate */ 1499 rkclk_set_pll(&pmucru->pll, &pmucru->pmu_mode, GPLL, hz); 1500 priv->gpll_hz = px30_gpll_get_pmuclk(priv); 1501 cru_priv->gpll_hz = priv->gpll_hz; 1502 1503 /* restore clock rate */ 1504 px30_bus_set_clk(cru_priv, ACLK_BUS_PRE, aclk_bus_rate); 1505 px30_bus_set_clk(cru_priv, HCLK_BUS_PRE, hclk_bus_rate); 1506 px30_bus_set_clk(cru_priv, PCLK_BUS_PRE, pclk_bus_rate); 1507 px30_peri_set_clk(cru_priv, ACLK_PERI_PRE, aclk_peri_rate); 1508 px30_peri_set_clk(cru_priv, HCLK_PERI_PRE, hclk_peri_rate); 1509 px30_pclk_pmu_set_pmuclk(priv, pclk_pmu_rate); 1510 1511 px30_mmc_set_clk(cru_priv, SCLK_EMMC, emmc_rate); 1512 px30_mmc_set_clk(cru_priv, SCLK_SDMMC, sdmmc_rate); 1513 px30_nandc_set_clk(cru_priv, nandc_rate); 1514 1515 return priv->gpll_hz; 1516 } 1517 1518 static ulong px30_pmuclk_get_rate(struct clk *clk) 1519 { 1520 struct px30_pmuclk_priv *priv = dev_get_priv(clk->dev); 1521 ulong rate = 0; 1522 1523 debug("%s %ld\n", __func__, clk->id); 1524 switch (clk->id) { 1525 case PLL_GPLL: 1526 rate = px30_gpll_get_pmuclk(priv); 1527 break; 1528 case PCLK_PMU_PRE: 1529 rate = px30_pclk_pmu_get_pmuclk(priv); 1530 break; 1531 default: 1532 return -ENOENT; 1533 } 1534 1535 return rate; 1536 } 1537 1538 static ulong px30_pmuclk_set_rate(struct clk *clk, ulong rate) 1539 { 1540 struct px30_pmuclk_priv *priv = dev_get_priv(clk->dev); 1541 ulong ret = 0; 1542 1543 debug("%s %ld %ld\n", __func__, clk->id, rate); 1544 switch (clk->id) { 1545 case PLL_GPLL: 1546 ret = px30_gpll_set_pmuclk(priv, rate); 1547 break; 1548 case PCLK_PMU_PRE: 1549 ret = px30_pclk_pmu_set_pmuclk(priv, rate); 1550 break; 1551 default: 1552 return -ENOENT; 1553 } 1554 1555 return ret; 1556 } 1557 1558 static struct clk_ops px30_pmuclk_ops = { 1559 .get_rate = px30_pmuclk_get_rate, 1560 .set_rate = px30_pmuclk_set_rate, 1561 }; 1562 1563 static void px30_clk_init(struct px30_pmuclk_priv *priv) 1564 { 1565 struct udevice *cru_dev; 1566 struct px30_clk_priv *cru_priv; 1567 ulong npll_hz; 1568 int ret; 1569 1570 priv->gpll_hz = px30_gpll_get_pmuclk(priv); 1571 if (priv->gpll_hz != GPLL_HZ) { 1572 ret = px30_gpll_set_pmuclk(priv, GPLL_HZ); 1573 if (ret < 0) 1574 printf("%s failed to set gpll rate\n", __func__); 1575 } 1576 1577 ret = uclass_get_device_by_name(UCLASS_CLK, 1578 "clock-controller@ff2b0000", 1579 &cru_dev); 1580 if (ret) { 1581 printf("%s failed to get cru device\n", __func__); 1582 return; 1583 } 1584 cru_priv = dev_get_priv(cru_dev); 1585 cru_priv->gpll_hz = priv->gpll_hz; 1586 1587 npll_hz = px30_clk_get_pll_rate(cru_priv, NPLL); 1588 if (npll_hz != NPLL_HZ) { 1589 ret = px30_clk_set_pll_rate(cru_priv, NPLL, NPLL_HZ); 1590 if (ret < 0) 1591 printf("%s failed to set npll rate\n", __func__); 1592 } 1593 1594 px30_bus_set_clk(cru_priv, ACLK_BUS_PRE, ACLK_BUS_HZ); 1595 px30_bus_set_clk(cru_priv, HCLK_BUS_PRE, HCLK_BUS_HZ); 1596 px30_bus_set_clk(cru_priv, PCLK_BUS_PRE, PCLK_BUS_HZ); 1597 px30_peri_set_clk(cru_priv, ACLK_PERI_PRE, ACLK_PERI_HZ); 1598 px30_peri_set_clk(cru_priv, HCLK_PERI_PRE, HCLK_PERI_HZ); 1599 px30_pclk_pmu_set_pmuclk(priv, PCLK_PMU_HZ); 1600 } 1601 1602 static int px30_pmuclk_probe(struct udevice *dev) 1603 { 1604 struct px30_pmuclk_priv *priv = dev_get_priv(dev); 1605 int ret; 1606 1607 px30_clk_init(priv); 1608 1609 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 1610 ret = clk_set_defaults(dev); 1611 if (ret) 1612 debug("%s clk_set_defaults failed %d\n", __func__, ret); 1613 1614 return 0; 1615 } 1616 1617 static int px30_pmuclk_ofdata_to_platdata(struct udevice *dev) 1618 { 1619 struct px30_pmuclk_priv *priv = dev_get_priv(dev); 1620 1621 priv->pmucru = dev_read_addr_ptr(dev); 1622 1623 return 0; 1624 } 1625 1626 static const struct udevice_id px30_pmuclk_ids[] = { 1627 { .compatible = "rockchip,px30-pmucru" }, 1628 { } 1629 }; 1630 1631 U_BOOT_DRIVER(rockchip_px30_pmucru) = { 1632 .name = "rockchip_px30_pmucru", 1633 .id = UCLASS_CLK, 1634 .of_match = px30_pmuclk_ids, 1635 .priv_auto_alloc_size = sizeof(struct px30_pmuclk_priv), 1636 .ofdata_to_platdata = px30_pmuclk_ofdata_to_platdata, 1637 .ops = &px30_pmuclk_ops, 1638 .probe = px30_pmuclk_probe, 1639 }; 1640 1641 /** 1642 * soc_clk_dump() - Print clock frequencies 1643 * Returns zero on success 1644 * 1645 * Implementation for the clk dump command. 1646 */ 1647 int soc_clk_dump(void) 1648 { 1649 struct udevice *cru_dev, *pmucru_dev; 1650 const struct px30_clk_info *clk_dump; 1651 struct clk clk; 1652 unsigned long clk_count = ARRAY_SIZE(clks_dump); 1653 unsigned long rate; 1654 int i, ret; 1655 1656 ret = uclass_get_device_by_driver(UCLASS_CLK, 1657 DM_GET_DRIVER(rockchip_px30_cru), 1658 &cru_dev); 1659 if (ret) { 1660 printf("%s failed to get cru device\n", __func__); 1661 return ret; 1662 } 1663 1664 ret = uclass_get_device_by_driver(UCLASS_CLK, 1665 DM_GET_DRIVER(rockchip_px30_pmucru), 1666 &pmucru_dev); 1667 if (ret) { 1668 printf("%s failed to get pmucru device\n", __func__); 1669 return ret; 1670 } 1671 1672 printf("CLK:\n"); 1673 for (i = 0; i < clk_count; i++) { 1674 clk_dump = &clks_dump[i]; 1675 if (clk_dump->name) { 1676 clk.id = clk_dump->id; 1677 if (clk_dump->is_cru) 1678 ret = clk_request(cru_dev, &clk); 1679 else 1680 ret = clk_request(pmucru_dev, &clk); 1681 if (ret < 0) 1682 return ret; 1683 1684 rate = clk_get_rate(&clk); 1685 clk_free(&clk); 1686 if (i == 0) { 1687 if (rate < 0) 1688 printf("%s %s\n", clk_dump->name, 1689 "unknown"); 1690 else 1691 printf("%s %lu KHz\n", clk_dump->name, 1692 rate / 1000); 1693 } else { 1694 if (rate < 0) 1695 printf("%s %s\n", clk_dump->name, 1696 "unknown"); 1697 else 1698 printf("%s %lu KHz\n", clk_dump->name, 1699 rate / 1000); 1700 } 1701 } 1702 } 1703 1704 return 0; 1705 } 1706