1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 #include <common.h> 7 #include <bitfield.h> 8 #include <clk-uclass.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <asm/io.h> 12 #include <asm/arch/clock.h> 13 #include <asm/arch/hardware.h> 14 #include <div64.h> 15 16 static struct rockchip_pll_rate_table rockchip_auto_table; 17 18 #define PLL_MODE_MASK 0x3 19 #define PLL_RK3328_MODE_MASK 0x1 20 21 #define RK3036_PLLCON0_FBDIV_MASK 0xfff 22 #define RK3036_PLLCON0_FBDIV_SHIFT 0 23 #define RK3036_PLLCON0_POSTDIV1_MASK 0x7 << 12 24 #define RK3036_PLLCON0_POSTDIV1_SHIFT 12 25 #define RK3036_PLLCON1_REFDIV_MASK 0x3f 26 #define RK3036_PLLCON1_REFDIV_SHIFT 0 27 #define RK3036_PLLCON1_POSTDIV2_MASK 0x7 << 6 28 #define RK3036_PLLCON1_POSTDIV2_SHIFT 6 29 #define RK3036_PLLCON1_DSMPD_MASK 0x1 << 12 30 #define RK3036_PLLCON1_DSMPD_SHIFT 12 31 #define RK3036_PLLCON2_FRAC_MASK 0xffffff 32 #define RK3036_PLLCON2_FRAC_SHIFT 0 33 #define RK3036_PLLCON1_PWRDOWN_SHIT 13 34 35 #define MHZ 1000000 36 #define KHZ 1000 37 38 #define OSC_HZ (24UL * MHZ) 39 #define VCO_MAX_HZ (3200UL * MHZ) 40 #define VCO_MIN_HZ (800UL * MHZ) 41 #define OUTPUT_MAX_HZ (3200UL * MHZ) 42 #define OUTPUT_MIN_HZ (24UL * MHZ) 43 #define MIN_FOUTVCO_FREQ (800UL * MHZ) 44 #define MAX_FOUTVCO_FREQ (2000UL * MHZ) 45 46 #define RK3588_VCO_MIN_HZ (2250UL * MHZ) 47 #define RK3588_VCO_MAX_HZ (4500UL * MHZ) 48 #define RK3588_FOUT_MIN_HZ (37UL * MHZ) 49 #define RK3588_FOUT_MAX_HZ (4500UL * MHZ) 50 51 int gcd(int m, int n) 52 { 53 int t; 54 55 while (m > 0) { 56 if (n > m) { 57 t = m; 58 m = n; 59 n = t; 60 } /* swap */ 61 m -= n; 62 } 63 return n; 64 } 65 66 /* 67 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63): 68 * Formulas also embedded within the Fractional PLL Verilog model: 69 * If DSMPD = 1 (DSM is disabled, "integer mode") 70 * FOUTVCO = FREF / REFDIV * FBDIV 71 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 72 * Where: 73 * FOUTVCO = Fractional PLL non-divided output frequency 74 * FOUTPOSTDIV = Fractional PLL divided output frequency 75 * (output of second post divider) 76 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input) 77 * REFDIV = Fractional PLL input reference clock divider 78 * FBDIV = Integer value programmed into feedback divide 79 * 80 */ 81 82 static int rockchip_pll_clk_set_postdiv(ulong fout_hz, 83 u32 *postdiv1, 84 u32 *postdiv2, 85 u32 *foutvco) 86 { 87 ulong freq; 88 89 if (fout_hz < MIN_FOUTVCO_FREQ) { 90 for (*postdiv1 = 1; *postdiv1 <= 7; (*postdiv1)++) { 91 for (*postdiv2 = 1; *postdiv2 <= 7; (*postdiv2)++) { 92 freq = fout_hz * (*postdiv1) * (*postdiv2); 93 if (freq >= MIN_FOUTVCO_FREQ && 94 freq <= MAX_FOUTVCO_FREQ) { 95 *foutvco = freq; 96 return 0; 97 } 98 } 99 } 100 printf("Can't FIND postdiv1/2 to make fout=%lu in 800~2000M.\n", 101 fout_hz); 102 } else { 103 *postdiv1 = 1; 104 *postdiv2 = 1; 105 } 106 return 0; 107 } 108 109 static struct rockchip_pll_rate_table * 110 rockchip_pll_clk_set_by_auto(ulong fin_hz, 111 ulong fout_hz) 112 { 113 struct rockchip_pll_rate_table *rate_table = &rockchip_auto_table; 114 /* FIXME set postdiv1/2 always 1*/ 115 u32 foutvco = fout_hz; 116 ulong fin_64, frac_64; 117 u32 f_frac, postdiv1, postdiv2; 118 ulong clk_gcd = 0; 119 120 if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz) 121 return NULL; 122 123 rockchip_pll_clk_set_postdiv(fout_hz, &postdiv1, &postdiv2, &foutvco); 124 rate_table->postdiv1 = postdiv1; 125 rate_table->postdiv2 = postdiv2; 126 rate_table->dsmpd = 1; 127 128 if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MHZ == fout_hz) { 129 fin_hz /= MHZ; 130 foutvco /= MHZ; 131 clk_gcd = gcd(fin_hz, foutvco); 132 rate_table->refdiv = fin_hz / clk_gcd; 133 rate_table->fbdiv = foutvco / clk_gcd; 134 135 rate_table->frac = 0; 136 137 debug("fin = %ld, fout = %ld, clk_gcd = %ld,\n", 138 fin_hz, fout_hz, clk_gcd); 139 debug("refdiv= %d,fbdiv= %d,postdiv1= %d,postdiv2= %d\n", 140 rate_table->refdiv, 141 rate_table->fbdiv, rate_table->postdiv1, 142 rate_table->postdiv2); 143 } else { 144 debug("frac div,fin_hz = %ld,fout_hz = %ld\n", 145 fin_hz, fout_hz); 146 debug("frac get postdiv1 = %d, postdiv2 = %d, foutvco = %d\n", 147 rate_table->postdiv1, rate_table->postdiv2, foutvco); 148 clk_gcd = gcd(fin_hz / MHZ, foutvco / MHZ); 149 rate_table->refdiv = fin_hz / MHZ / clk_gcd; 150 rate_table->fbdiv = foutvco / MHZ / clk_gcd; 151 debug("frac get refdiv = %d, fbdiv = %d\n", 152 rate_table->refdiv, rate_table->fbdiv); 153 154 rate_table->frac = 0; 155 156 f_frac = (foutvco % MHZ); 157 fin_64 = fin_hz; 158 fin_64 = fin_64 / rate_table->refdiv; 159 frac_64 = f_frac << 24; 160 frac_64 = frac_64 / fin_64; 161 rate_table->frac = frac_64; 162 if (rate_table->frac > 0) 163 rate_table->dsmpd = 0; 164 debug("frac = %x\n", rate_table->frac); 165 } 166 return rate_table; 167 } 168 169 static u32 170 rockchip_rk3588_pll_k_get(u32 m, u32 p, u32 s, u64 fin_hz, u64 fvco) 171 { 172 u64 fref, fout, ffrac; 173 u32 k = 0; 174 175 fref = fin_hz / p; 176 ffrac = fvco - (m * fref); 177 fout = ffrac * 65536; 178 k = fout / fref; 179 if (k > 32767) { 180 fref = fin_hz / p; 181 ffrac = ((m + 1) * fref) - fvco; 182 fout = ffrac * 65536; 183 k = ((fout * 10 / fref) + 7) / 10; 184 if (k > 32767) 185 k = 0; 186 else 187 k = ~k + 1; 188 } 189 return k; 190 } 191 192 static struct rockchip_pll_rate_table * 193 rockchip_rk3588_pll_frac_by_auto(unsigned long fin_hz, unsigned long fout_hz) 194 { 195 struct rockchip_pll_rate_table *rate_table = &rockchip_auto_table; 196 u32 p, m, s, k; 197 u64 fvco; 198 199 for (s = 0; s <= 6; s++) { 200 fvco = (u64)fout_hz << s; 201 if (fvco < RK3588_VCO_MIN_HZ || fvco > RK3588_VCO_MAX_HZ) 202 continue; 203 for (p = 1; p <= 4; p++) { 204 for (m = 64; m <= 1023; m++) { 205 if ((fvco >= m * fin_hz / p) && 206 (fvco < (m + 1) * fin_hz / p)) { 207 k = rockchip_rk3588_pll_k_get(m, p, s, 208 fin_hz, 209 fvco); 210 if (!k) 211 continue; 212 rate_table->p = p; 213 rate_table->s = s; 214 rate_table->k = k; 215 if (k > 32767) 216 rate_table->m = m + 1; 217 else 218 rate_table->m = m; 219 return rate_table; 220 } 221 } 222 } 223 } 224 return NULL; 225 } 226 227 static struct rockchip_pll_rate_table * 228 rk3588_pll_clk_set_by_auto(unsigned long fin_hz, 229 unsigned long fout_hz) 230 { 231 struct rockchip_pll_rate_table *rate_table = &rockchip_auto_table; 232 u32 p, m, s; 233 ulong fvco; 234 235 if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz) 236 return NULL; 237 238 if (fout_hz > RK3588_FOUT_MAX_HZ || fout_hz < RK3588_FOUT_MIN_HZ) 239 return NULL; 240 241 if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MHZ == fout_hz) { 242 for (s = 0; s <= 6; s++) { 243 fvco = fout_hz << s; 244 if (fvco < RK3588_VCO_MIN_HZ || 245 fvco > RK3588_VCO_MAX_HZ) 246 continue; 247 for (p = 2; p <= 4; p++) { 248 for (m = 64; m <= 1023; m++) { 249 if (fvco == m * fin_hz / p) { 250 rate_table->p = p; 251 rate_table->m = m; 252 rate_table->s = s; 253 rate_table->k = 0; 254 return rate_table; 255 } 256 } 257 } 258 } 259 pr_err("CANNOT FIND Fout by auto,fout = %lu\n", fout_hz); 260 } else { 261 rate_table = rockchip_rk3588_pll_frac_by_auto(fin_hz, fout_hz); 262 if (!rate_table) 263 pr_err("CANNOT FIND Fout by auto,fout = %lu\n", 264 fout_hz); 265 else 266 return rate_table; 267 } 268 return NULL; 269 } 270 271 static const struct rockchip_pll_rate_table * 272 rockchip_get_pll_settings(struct rockchip_pll_clock *pll, ulong rate) 273 { 274 struct rockchip_pll_rate_table *rate_table = pll->rate_table; 275 276 while (rate_table->rate) { 277 if (rate_table->rate == rate) 278 break; 279 rate_table++; 280 } 281 if (rate_table->rate != rate) { 282 if (pll->type == pll_rk3588) 283 return rk3588_pll_clk_set_by_auto(24 * MHZ, rate); 284 else 285 return rockchip_pll_clk_set_by_auto(24 * MHZ, rate); 286 } else { 287 return rate_table; 288 } 289 } 290 291 static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll, 292 void __iomem *base, ulong pll_id, 293 ulong drate) 294 { 295 const struct rockchip_pll_rate_table *rate; 296 int timeout = 100; 297 298 rate = rockchip_get_pll_settings(pll, drate); 299 if (!rate) { 300 printf("%s unsupport rate\n", __func__); 301 return -EINVAL; 302 } 303 304 debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d\n", 305 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv); 306 debug("%s: rate settings for %lu postdiv2: %d, dsmpd: %d, frac: %d\n", 307 __func__, rate->rate, rate->postdiv2, rate->dsmpd, rate->frac); 308 309 /* 310 * When power on or changing PLL setting, 311 * we must force PLL into slow mode to ensure output stable clock. 312 */ 313 if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) { 314 rk_clrsetreg(base + pll->mode_offset, 315 pll->mode_mask << pll->mode_shift, 316 RKCLK_PLL_MODE_SLOW << pll->mode_shift); 317 } 318 319 /* Power down */ 320 rk_setreg(base + pll->con_offset + 0x4, 321 1 << RK3036_PLLCON1_PWRDOWN_SHIT); 322 323 rk_clrsetreg(base + pll->con_offset, 324 (RK3036_PLLCON0_POSTDIV1_MASK | 325 RK3036_PLLCON0_FBDIV_MASK), 326 (rate->postdiv1 << RK3036_PLLCON0_POSTDIV1_SHIFT) | 327 rate->fbdiv); 328 rk_clrsetreg(base + pll->con_offset + 0x4, 329 (RK3036_PLLCON1_POSTDIV2_MASK | 330 RK3036_PLLCON1_REFDIV_MASK), 331 (rate->postdiv2 << RK3036_PLLCON1_POSTDIV2_SHIFT | 332 rate->refdiv << RK3036_PLLCON1_REFDIV_SHIFT)); 333 if (!rate->dsmpd) { 334 rk_clrsetreg(base + pll->con_offset + 0x4, 335 RK3036_PLLCON1_DSMPD_MASK, 336 rate->dsmpd << RK3036_PLLCON1_DSMPD_SHIFT); 337 writel((readl(base + pll->con_offset + 0x8) & 338 (~RK3036_PLLCON2_FRAC_MASK)) | 339 (rate->frac << RK3036_PLLCON2_FRAC_SHIFT), 340 base + pll->con_offset + 0x8); 341 } 342 343 /* Power Up */ 344 rk_clrreg(base + pll->con_offset + 0x4, 345 1 << RK3036_PLLCON1_PWRDOWN_SHIT); 346 347 /* waiting for pll lock */ 348 while ((timeout > 0) && !(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift))) { 349 udelay(1); 350 timeout--; 351 } 352 353 if (!(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift))) 354 printf("%s: wait pll lock timeout! pll_id=%ld\n", __func__, pll_id); 355 356 if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) { 357 rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift, 358 RKCLK_PLL_MODE_NORMAL << pll->mode_shift); 359 } 360 361 debug("PLL at %p: con0=%x con1= %x con2= %x mode= %x\n", 362 pll, readl(base + pll->con_offset), 363 readl(base + pll->con_offset + 0x4), 364 readl(base + pll->con_offset + 0x8), 365 readl(base + pll->mode_offset)); 366 367 return 0; 368 } 369 370 static ulong rk3036_pll_get_rate(struct rockchip_pll_clock *pll, 371 void __iomem *base, ulong pll_id) 372 { 373 u32 refdiv, fbdiv, postdiv1, postdiv2, dsmpd, frac; 374 u32 con = 0, shift, mask; 375 ulong rate; 376 int mode; 377 378 con = readl(base + pll->mode_offset); 379 shift = pll->mode_shift; 380 mask = pll->mode_mask << shift; 381 382 if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) 383 mode = (con & mask) >> shift; 384 else 385 mode = RKCLK_PLL_MODE_NORMAL; 386 387 switch (mode) { 388 case RKCLK_PLL_MODE_SLOW: 389 return OSC_HZ; 390 case RKCLK_PLL_MODE_NORMAL: 391 /* normal mode */ 392 con = readl(base + pll->con_offset); 393 postdiv1 = (con & RK3036_PLLCON0_POSTDIV1_MASK) >> 394 RK3036_PLLCON0_POSTDIV1_SHIFT; 395 fbdiv = (con & RK3036_PLLCON0_FBDIV_MASK) >> 396 RK3036_PLLCON0_FBDIV_SHIFT; 397 con = readl(base + pll->con_offset + 0x4); 398 postdiv2 = (con & RK3036_PLLCON1_POSTDIV2_MASK) >> 399 RK3036_PLLCON1_POSTDIV2_SHIFT; 400 refdiv = (con & RK3036_PLLCON1_REFDIV_MASK) >> 401 RK3036_PLLCON1_REFDIV_SHIFT; 402 dsmpd = (con & RK3036_PLLCON1_DSMPD_MASK) >> 403 RK3036_PLLCON1_DSMPD_SHIFT; 404 con = readl(base + pll->con_offset + 0x8); 405 frac = (con & RK3036_PLLCON2_FRAC_MASK) >> 406 RK3036_PLLCON2_FRAC_SHIFT; 407 rate = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; 408 if (dsmpd == 0) { 409 u64 frac_rate = OSC_HZ * (u64)frac; 410 411 do_div(frac_rate, refdiv); 412 frac_rate >>= 24; 413 do_div(frac_rate, postdiv1); 414 do_div(frac_rate, postdiv1); 415 rate += frac_rate; 416 } 417 return rate; 418 case RKCLK_PLL_MODE_DEEP: 419 default: 420 return 32768; 421 } 422 } 423 424 #define RK3588_PLLCON(i) ((i) * 0x4) 425 #define RK3588_PLLCON0_M_MASK 0x3ff << 0 426 #define RK3588_PLLCON0_M_SHIFT 0 427 #define RK3588_PLLCON1_P_MASK 0x3f << 0 428 #define RK3588_PLLCON1_P_SHIFT 0 429 #define RK3588_PLLCON1_S_MASK 0x7 << 6 430 #define RK3588_PLLCON1_S_SHIFT 6 431 #define RK3588_PLLCON2_K_MASK 0xffff 432 #define RK3588_PLLCON2_K_SHIFT 0 433 #define RK3588_PLLCON1_PWRDOWN BIT(13) 434 #define RK3588_PLLCON6_LOCK_STATUS BIT(15) 435 #define RK3588_B0PLL_CLKSEL_CON(i) ((i) * 0x4 + 0x50000 + 0x300) 436 #define RK3588_B1PLL_CLKSEL_CON(i) ((i) * 0x4 + 0x52000 + 0x300) 437 #define RK3588_LPLL_CLKSEL_CON(i) ((i) * 0x4 + 0x58000 + 0x300) 438 #define RK3588_CORE_DIV_MASK 0x1f 439 #define RK3588_CORE_L02_DIV_SHIFT 0 440 #define RK3588_CORE_L13_DIV_SHIFT 7 441 #define RK3588_CORE_B02_DIV_SHIFT 8 442 #define RK3588_CORE_B13_DIV_SHIFT 0 443 444 static int rk3588_pll_set_rate(struct rockchip_pll_clock *pll, 445 void __iomem *base, ulong pll_id, 446 ulong drate) 447 { 448 const struct rockchip_pll_rate_table *rate; 449 450 rate = rockchip_get_pll_settings(pll, drate); 451 if (!rate) { 452 printf("%s unsupported rate\n", __func__); 453 return -EINVAL; 454 } 455 456 debug("%s: rate settings for %lu p: %d, m: %d, s: %d, k: %d\n", 457 __func__, rate->rate, rate->p, rate->m, rate->s, rate->k); 458 459 /* 460 * When power on or changing PLL setting, 461 * we must force PLL into slow mode to ensure output stable clock. 462 */ 463 if (pll_id == 3) 464 rk_clrsetreg(base + 0x84c, 0x1 << 1, 0x1 << 1); 465 466 rk_clrsetreg(base + pll->mode_offset, 467 pll->mode_mask << pll->mode_shift, 468 RKCLK_PLL_MODE_SLOW << pll->mode_shift); 469 if (pll_id == 0) 470 rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(0), 471 pll->mode_mask << 6, 472 RKCLK_PLL_MODE_SLOW << 6); 473 else if (pll_id == 1) 474 rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(0), 475 pll->mode_mask << 6, 476 RKCLK_PLL_MODE_SLOW << 6); 477 else if (pll_id == 2) 478 rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(5), 479 pll->mode_mask << 14, 480 RKCLK_PLL_MODE_SLOW << 14); 481 482 /* Power down */ 483 rk_setreg(base + pll->con_offset + RK3588_PLLCON(1), 484 RK3588_PLLCON1_PWRDOWN); 485 486 rk_clrsetreg(base + pll->con_offset, 487 RK3588_PLLCON0_M_MASK, 488 (rate->m << RK3588_PLLCON0_M_SHIFT)); 489 rk_clrsetreg(base + pll->con_offset + RK3588_PLLCON(1), 490 (RK3588_PLLCON1_P_MASK | 491 RK3588_PLLCON1_S_MASK), 492 (rate->p << RK3588_PLLCON1_P_SHIFT | 493 rate->s << RK3588_PLLCON1_S_SHIFT)); 494 if (rate->k) { 495 rk_clrsetreg(base + pll->con_offset + RK3588_PLLCON(2), 496 RK3588_PLLCON2_K_MASK, 497 rate->k << RK3588_PLLCON2_K_SHIFT); 498 } 499 /* Power up */ 500 rk_clrreg(base + pll->con_offset + RK3588_PLLCON(1), 501 RK3588_PLLCON1_PWRDOWN); 502 503 /* waiting for pll lock */ 504 while (!(readl(base + pll->con_offset + RK3588_PLLCON(6)) & 505 RK3588_PLLCON6_LOCK_STATUS)) { 506 udelay(1); 507 debug("%s: wait pll lock, pll_id=%ld\n", __func__, pll_id); 508 } 509 510 rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift, 511 RKCLK_PLL_MODE_NORMAL << pll->mode_shift); 512 if (pll_id == 0) { 513 rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(0), 514 pll->mode_mask << 6, 515 2 << 6); 516 rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(0), 517 RK3588_CORE_DIV_MASK << RK3588_CORE_B02_DIV_SHIFT, 518 0 << RK3588_CORE_B02_DIV_SHIFT); 519 rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(1), 520 RK3588_CORE_DIV_MASK << RK3588_CORE_B13_DIV_SHIFT, 521 0 << RK3588_CORE_B13_DIV_SHIFT); 522 } else if (pll_id == 1) { 523 rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(0), 524 pll->mode_mask << 6, 525 2 << 6); 526 rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(0), 527 RK3588_CORE_DIV_MASK << RK3588_CORE_B02_DIV_SHIFT, 528 0 << RK3588_CORE_B02_DIV_SHIFT); 529 rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(1), 530 RK3588_CORE_DIV_MASK << RK3588_CORE_B13_DIV_SHIFT, 531 0 << RK3588_CORE_B13_DIV_SHIFT); 532 } else if (pll_id == 2) { 533 rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(5), 534 pll->mode_mask << 14, 535 2 << 14); 536 rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(6), 537 RK3588_CORE_DIV_MASK << RK3588_CORE_L13_DIV_SHIFT, 538 0 << RK3588_CORE_L13_DIV_SHIFT); 539 rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(6), 540 RK3588_CORE_DIV_MASK << RK3588_CORE_L02_DIV_SHIFT, 541 0 << RK3588_CORE_L02_DIV_SHIFT); 542 rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(7), 543 RK3588_CORE_DIV_MASK << RK3588_CORE_L13_DIV_SHIFT, 544 0 << RK3588_CORE_L13_DIV_SHIFT); 545 rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(7), 546 RK3588_CORE_DIV_MASK << RK3588_CORE_L02_DIV_SHIFT, 547 0 << RK3588_CORE_L02_DIV_SHIFT); 548 } 549 550 if (pll_id == 3) 551 rk_clrsetreg(base + 0x84c, 0x1 << 1, 0); 552 553 debug("PLL at %p: con0=%x con1= %x con2= %x mode= %x\n", 554 pll, readl(base + pll->con_offset), 555 readl(base + pll->con_offset + 0x4), 556 readl(base + pll->con_offset + 0x8), 557 readl(base + pll->mode_offset)); 558 559 return 0; 560 } 561 562 static ulong rk3588_pll_get_rate(struct rockchip_pll_clock *pll, 563 void __iomem *base, ulong pll_id) 564 { 565 u32 m, p, s, k; 566 u32 con = 0, shift, mode; 567 u64 rate, postdiv; 568 569 con = readl(base + pll->mode_offset); 570 shift = pll->mode_shift; 571 if (pll_id == 8) 572 mode = RKCLK_PLL_MODE_NORMAL; 573 else 574 mode = (con & (pll->mode_mask << shift)) >> shift; 575 switch (mode) { 576 case RKCLK_PLL_MODE_SLOW: 577 return OSC_HZ; 578 case RKCLK_PLL_MODE_NORMAL: 579 /* normal mode */ 580 con = readl(base + pll->con_offset); 581 m = (con & RK3588_PLLCON0_M_MASK) >> 582 RK3588_PLLCON0_M_SHIFT; 583 con = readl(base + pll->con_offset + RK3588_PLLCON(1)); 584 p = (con & RK3588_PLLCON1_P_MASK) >> 585 RK3036_PLLCON0_FBDIV_SHIFT; 586 s = (con & RK3588_PLLCON1_S_MASK) >> 587 RK3588_PLLCON1_S_SHIFT; 588 con = readl(base + pll->con_offset + RK3588_PLLCON(2)); 589 k = (con & RK3588_PLLCON2_K_MASK) >> 590 RK3588_PLLCON2_K_SHIFT; 591 592 rate = OSC_HZ / p; 593 rate *= m; 594 if (k & BIT(15)) { 595 /* fractional mode */ 596 u64 frac_rate64; 597 598 k = (~(k - 1)) & RK3588_PLLCON2_K_MASK; 599 frac_rate64 = OSC_HZ * k; 600 postdiv = p; 601 postdiv *= 65536; 602 do_div(frac_rate64, postdiv); 603 rate -= frac_rate64; 604 } else { 605 /* fractional mode */ 606 u64 frac_rate64 = OSC_HZ * k; 607 608 postdiv = p; 609 postdiv *= 65536; 610 do_div(frac_rate64, postdiv); 611 rate += frac_rate64; 612 } 613 rate = rate >> s; 614 return rate; 615 case RKCLK_PLL_MODE_DEEP: 616 default: 617 return 32768; 618 } 619 } 620 621 ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll, 622 void __iomem *base, 623 ulong pll_id) 624 { 625 ulong rate = 0; 626 627 switch (pll->type) { 628 case pll_rk3036: 629 pll->mode_mask = PLL_MODE_MASK; 630 rate = rk3036_pll_get_rate(pll, base, pll_id); 631 break; 632 case pll_rk3328: 633 pll->mode_mask = PLL_RK3328_MODE_MASK; 634 rate = rk3036_pll_get_rate(pll, base, pll_id); 635 break; 636 case pll_rk3588: 637 pll->mode_mask = PLL_MODE_MASK; 638 rate = rk3588_pll_get_rate(pll, base, pll_id); 639 break; 640 default: 641 printf("%s: Unknown pll type for pll clk %ld\n", 642 __func__, pll_id); 643 } 644 return rate; 645 } 646 647 int rockchip_pll_set_rate(struct rockchip_pll_clock *pll, 648 void __iomem *base, ulong pll_id, 649 ulong drate) 650 { 651 int ret = 0; 652 653 if (rockchip_pll_get_rate(pll, base, pll_id) == drate) 654 return 0; 655 656 switch (pll->type) { 657 case pll_rk3036: 658 pll->mode_mask = PLL_MODE_MASK; 659 ret = rk3036_pll_set_rate(pll, base, pll_id, drate); 660 break; 661 case pll_rk3328: 662 pll->mode_mask = PLL_RK3328_MODE_MASK; 663 ret = rk3036_pll_set_rate(pll, base, pll_id, drate); 664 break; 665 case pll_rk3588: 666 pll->mode_mask = PLL_MODE_MASK; 667 ret = rk3588_pll_set_rate(pll, base, pll_id, drate); 668 break; 669 default: 670 printf("%s: Unknown pll type for pll clk %ld\n", 671 __func__, pll_id); 672 } 673 return ret; 674 } 675 676 const struct rockchip_cpu_rate_table * 677 rockchip_get_cpu_settings(struct rockchip_cpu_rate_table *cpu_table, 678 ulong rate) 679 { 680 struct rockchip_cpu_rate_table *ps = cpu_table; 681 682 while (ps->rate) { 683 if (ps->rate == rate) 684 break; 685 ps++; 686 } 687 if (ps->rate != rate) 688 return NULL; 689 else 690 return ps; 691 } 692 693