1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 #include <common.h> 7 #include <bitfield.h> 8 #include <clk-uclass.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <asm/io.h> 12 #include <asm/arch/clock.h> 13 #include <asm/arch/hardware.h> 14 #include <div64.h> 15 16 static struct rockchip_pll_rate_table rockchip_auto_table; 17 18 #define PLL_MODE_MASK 0x3 19 #define PLL_RK3328_MODE_MASK 0x1 20 21 #define RK3036_PLLCON0_FBDIV_MASK 0xfff 22 #define RK3036_PLLCON0_FBDIV_SHIFT 0 23 #define RK3036_PLLCON0_POSTDIV1_MASK 0x7 << 12 24 #define RK3036_PLLCON0_POSTDIV1_SHIFT 12 25 #define RK3036_PLLCON1_REFDIV_MASK 0x3f 26 #define RK3036_PLLCON1_REFDIV_SHIFT 0 27 #define RK3036_PLLCON1_POSTDIV2_MASK 0x7 << 6 28 #define RK3036_PLLCON1_POSTDIV2_SHIFT 6 29 #define RK3036_PLLCON1_DSMPD_MASK 0x1 << 12 30 #define RK3036_PLLCON1_DSMPD_SHIFT 12 31 #define RK3036_PLLCON2_FRAC_MASK 0xffffff 32 #define RK3036_PLLCON2_FRAC_SHIFT 0 33 #define RK3036_PLLCON1_PWRDOWN_SHIT 13 34 35 #define MHZ 1000000 36 #define KHZ 1000 37 38 #define OSC_HZ (24UL * MHZ) 39 #define VCO_MAX_HZ (3200UL * MHZ) 40 #define VCO_MIN_HZ (800UL * MHZ) 41 #define OUTPUT_MAX_HZ (3200UL * MHZ) 42 #define OUTPUT_MIN_HZ (24UL * MHZ) 43 #define MIN_FOUTVCO_FREQ (800UL * MHZ) 44 #define MAX_FOUTVCO_FREQ (2000UL * MHZ) 45 46 #define RK3588_VCO_MIN_HZ (2250UL * MHZ) 47 #define RK3588_VCO_MAX_HZ (4500UL * MHZ) 48 #define RK3588_FOUT_MIN_HZ (37UL * MHZ) 49 #define RK3588_FOUT_MAX_HZ (4500UL * MHZ) 50 51 int gcd(int m, int n) 52 { 53 int t; 54 55 while (m > 0) { 56 if (n > m) { 57 t = m; 58 m = n; 59 n = t; 60 } /* swap */ 61 m -= n; 62 } 63 return n; 64 } 65 66 /* 67 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63): 68 * Formulas also embedded within the Fractional PLL Verilog model: 69 * If DSMPD = 1 (DSM is disabled, "integer mode") 70 * FOUTVCO = FREF / REFDIV * FBDIV 71 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 72 * Where: 73 * FOUTVCO = Fractional PLL non-divided output frequency 74 * FOUTPOSTDIV = Fractional PLL divided output frequency 75 * (output of second post divider) 76 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input) 77 * REFDIV = Fractional PLL input reference clock divider 78 * FBDIV = Integer value programmed into feedback divide 79 * 80 */ 81 82 static int rockchip_pll_clk_set_postdiv(ulong fout_hz, 83 u32 *postdiv1, 84 u32 *postdiv2, 85 u32 *foutvco) 86 { 87 ulong freq; 88 89 if (fout_hz < MIN_FOUTVCO_FREQ) { 90 for (*postdiv1 = 1; *postdiv1 <= 7; (*postdiv1)++) { 91 for (*postdiv2 = 1; *postdiv2 <= 7; (*postdiv2)++) { 92 freq = fout_hz * (*postdiv1) * (*postdiv2); 93 if (freq >= MIN_FOUTVCO_FREQ && 94 freq <= MAX_FOUTVCO_FREQ) { 95 *foutvco = freq; 96 return 0; 97 } 98 } 99 } 100 printf("Can't FIND postdiv1/2 to make fout=%lu in 800~2000M.\n", 101 fout_hz); 102 } else { 103 *postdiv1 = 1; 104 *postdiv2 = 1; 105 } 106 return 0; 107 } 108 109 static struct rockchip_pll_rate_table * 110 rockchip_pll_clk_set_by_auto(ulong fin_hz, 111 ulong fout_hz) 112 { 113 struct rockchip_pll_rate_table *rate_table = &rockchip_auto_table; 114 /* FIXME set postdiv1/2 always 1*/ 115 u32 foutvco = fout_hz; 116 ulong fin_64, frac_64; 117 u32 f_frac, postdiv1, postdiv2; 118 ulong clk_gcd = 0; 119 120 if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz) 121 return NULL; 122 123 rockchip_pll_clk_set_postdiv(fout_hz, &postdiv1, &postdiv2, &foutvco); 124 rate_table->postdiv1 = postdiv1; 125 rate_table->postdiv2 = postdiv2; 126 rate_table->dsmpd = 1; 127 128 if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MHZ == fout_hz) { 129 fin_hz /= MHZ; 130 foutvco /= MHZ; 131 clk_gcd = gcd(fin_hz, foutvco); 132 rate_table->refdiv = fin_hz / clk_gcd; 133 rate_table->fbdiv = foutvco / clk_gcd; 134 135 rate_table->frac = 0; 136 137 debug("fin = %ld, fout = %ld, clk_gcd = %ld,\n", 138 fin_hz, fout_hz, clk_gcd); 139 debug("refdiv= %d,fbdiv= %d,postdiv1= %d,postdiv2= %d\n", 140 rate_table->refdiv, 141 rate_table->fbdiv, rate_table->postdiv1, 142 rate_table->postdiv2); 143 } else { 144 debug("frac div,fin_hz = %ld,fout_hz = %ld\n", 145 fin_hz, fout_hz); 146 debug("frac get postdiv1 = %d, postdiv2 = %d, foutvco = %d\n", 147 rate_table->postdiv1, rate_table->postdiv2, foutvco); 148 clk_gcd = gcd(fin_hz / MHZ, foutvco / MHZ); 149 rate_table->refdiv = fin_hz / MHZ / clk_gcd; 150 rate_table->fbdiv = foutvco / MHZ / clk_gcd; 151 debug("frac get refdiv = %d, fbdiv = %d\n", 152 rate_table->refdiv, rate_table->fbdiv); 153 154 rate_table->frac = 0; 155 156 f_frac = (foutvco % MHZ); 157 fin_64 = fin_hz; 158 fin_64 = fin_64 / rate_table->refdiv; 159 frac_64 = f_frac << 24; 160 frac_64 = frac_64 / fin_64; 161 rate_table->frac = frac_64; 162 if (rate_table->frac > 0) 163 rate_table->dsmpd = 0; 164 debug("frac = %x\n", rate_table->frac); 165 } 166 return rate_table; 167 } 168 169 static struct rockchip_pll_rate_table * 170 rk3588_pll_clk_set_by_auto(unsigned long fin_hz, 171 unsigned long fout_hz) 172 { 173 struct rockchip_pll_rate_table *rate_table = &rockchip_auto_table; 174 u32 p, m, s; 175 ulong fvco, fref, fout, ffrac; 176 177 if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz) 178 return NULL; 179 180 if (fout_hz > RK3588_FOUT_MAX_HZ || fout_hz < RK3588_FOUT_MIN_HZ) 181 return NULL; 182 183 if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MHZ == fout_hz) { 184 for (s = 0; s <= 6; s++) { 185 fvco = fout_hz << s; 186 if (fvco < RK3588_VCO_MIN_HZ || 187 fvco > RK3588_VCO_MAX_HZ) 188 continue; 189 for (p = 2; p <= 4; p++) { 190 for (m = 64; m <= 1023; m++) { 191 if (fvco == m * fin_hz / p) { 192 rate_table->p = p; 193 rate_table->m = m; 194 rate_table->s = s; 195 rate_table->k = 0; 196 return rate_table; 197 } 198 } 199 } 200 } 201 pr_err("CANNOT FIND Fout by auto,fout = %lu\n", fout_hz); 202 } else { 203 fout = (fout_hz / MHZ) * MHZ; 204 ffrac = (fout_hz % MHZ); 205 for (s = 0; s <= 6; s++) { 206 fvco = fout << s; 207 if (fvco < RK3588_VCO_MIN_HZ || 208 fvco > RK3588_VCO_MAX_HZ) 209 continue; 210 for (p = 1; p <= 4; p++) { 211 for (m = 64; m <= 1023; m++) { 212 if (fvco == m * fin_hz / p) { 213 rate_table->p = p; 214 rate_table->m = m; 215 rate_table->s = s; 216 fref = fin_hz / p; 217 fout = (ffrac << s) * 65535; 218 rate_table->k = fout / fref; 219 return rate_table; 220 } 221 } 222 } 223 } 224 pr_err("CANNOT FIND Fout by auto,fout = %lu\n", fout_hz); 225 } 226 return NULL; 227 } 228 229 static const struct rockchip_pll_rate_table * 230 rockchip_get_pll_settings(struct rockchip_pll_clock *pll, ulong rate) 231 { 232 struct rockchip_pll_rate_table *rate_table = pll->rate_table; 233 234 while (rate_table->rate) { 235 if (rate_table->rate == rate) 236 break; 237 rate_table++; 238 } 239 if (rate_table->rate != rate) { 240 if (pll->type == pll_rk3588) 241 return rk3588_pll_clk_set_by_auto(24 * MHZ, rate); 242 else 243 return rockchip_pll_clk_set_by_auto(24 * MHZ, rate); 244 } else { 245 return rate_table; 246 } 247 } 248 249 static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll, 250 void __iomem *base, ulong pll_id, 251 ulong drate) 252 { 253 const struct rockchip_pll_rate_table *rate; 254 int timeout = 100; 255 256 rate = rockchip_get_pll_settings(pll, drate); 257 if (!rate) { 258 printf("%s unsupport rate\n", __func__); 259 return -EINVAL; 260 } 261 262 debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d\n", 263 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv); 264 debug("%s: rate settings for %lu postdiv2: %d, dsmpd: %d, frac: %d\n", 265 __func__, rate->rate, rate->postdiv2, rate->dsmpd, rate->frac); 266 267 /* 268 * When power on or changing PLL setting, 269 * we must force PLL into slow mode to ensure output stable clock. 270 */ 271 rk_clrsetreg(base + pll->mode_offset, 272 pll->mode_mask << pll->mode_shift, 273 RKCLK_PLL_MODE_SLOW << pll->mode_shift); 274 275 /* Power down */ 276 rk_setreg(base + pll->con_offset + 0x4, 277 1 << RK3036_PLLCON1_PWRDOWN_SHIT); 278 279 rk_clrsetreg(base + pll->con_offset, 280 (RK3036_PLLCON0_POSTDIV1_MASK | 281 RK3036_PLLCON0_FBDIV_MASK), 282 (rate->postdiv1 << RK3036_PLLCON0_POSTDIV1_SHIFT) | 283 rate->fbdiv); 284 rk_clrsetreg(base + pll->con_offset + 0x4, 285 (RK3036_PLLCON1_POSTDIV2_MASK | 286 RK3036_PLLCON1_REFDIV_MASK), 287 (rate->postdiv2 << RK3036_PLLCON1_POSTDIV2_SHIFT | 288 rate->refdiv << RK3036_PLLCON1_REFDIV_SHIFT)); 289 if (!rate->dsmpd) { 290 rk_clrsetreg(base + pll->con_offset + 0x4, 291 RK3036_PLLCON1_DSMPD_MASK, 292 rate->dsmpd << RK3036_PLLCON1_DSMPD_SHIFT); 293 writel((readl(base + pll->con_offset + 0x8) & 294 (~RK3036_PLLCON2_FRAC_MASK)) | 295 (rate->frac << RK3036_PLLCON2_FRAC_SHIFT), 296 base + pll->con_offset + 0x8); 297 } 298 299 /* Power Up */ 300 rk_clrreg(base + pll->con_offset + 0x4, 301 1 << RK3036_PLLCON1_PWRDOWN_SHIT); 302 303 /* waiting for pll lock */ 304 while ((timeout > 0) && !(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift))) { 305 udelay(1); 306 timeout--; 307 } 308 309 if (!(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift))) 310 printf("%s: wait pll lock timeout! pll_id=%ld\n", __func__, pll_id); 311 312 rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift, 313 RKCLK_PLL_MODE_NORMAL << pll->mode_shift); 314 debug("PLL at %p: con0=%x con1= %x con2= %x mode= %x\n", 315 pll, readl(base + pll->con_offset), 316 readl(base + pll->con_offset + 0x4), 317 readl(base + pll->con_offset + 0x8), 318 readl(base + pll->mode_offset)); 319 320 return 0; 321 } 322 323 static ulong rk3036_pll_get_rate(struct rockchip_pll_clock *pll, 324 void __iomem *base, ulong pll_id) 325 { 326 u32 refdiv, fbdiv, postdiv1, postdiv2, dsmpd, frac; 327 u32 con = 0, shift, mask; 328 ulong rate; 329 330 con = readl(base + pll->mode_offset); 331 shift = pll->mode_shift; 332 mask = pll->mode_mask << shift; 333 334 switch ((con & mask) >> shift) { 335 case RKCLK_PLL_MODE_SLOW: 336 return OSC_HZ; 337 case RKCLK_PLL_MODE_NORMAL: 338 /* normal mode */ 339 con = readl(base + pll->con_offset); 340 postdiv1 = (con & RK3036_PLLCON0_POSTDIV1_MASK) >> 341 RK3036_PLLCON0_POSTDIV1_SHIFT; 342 fbdiv = (con & RK3036_PLLCON0_FBDIV_MASK) >> 343 RK3036_PLLCON0_FBDIV_SHIFT; 344 con = readl(base + pll->con_offset + 0x4); 345 postdiv2 = (con & RK3036_PLLCON1_POSTDIV2_MASK) >> 346 RK3036_PLLCON1_POSTDIV2_SHIFT; 347 refdiv = (con & RK3036_PLLCON1_REFDIV_MASK) >> 348 RK3036_PLLCON1_REFDIV_SHIFT; 349 dsmpd = (con & RK3036_PLLCON1_DSMPD_MASK) >> 350 RK3036_PLLCON1_DSMPD_SHIFT; 351 con = readl(base + pll->con_offset + 0x8); 352 frac = (con & RK3036_PLLCON2_FRAC_MASK) >> 353 RK3036_PLLCON2_FRAC_SHIFT; 354 rate = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; 355 if (dsmpd == 0) { 356 u64 frac_rate = OSC_HZ * (u64)frac; 357 358 do_div(frac_rate, refdiv); 359 frac_rate >>= 24; 360 do_div(frac_rate, postdiv1); 361 do_div(frac_rate, postdiv1); 362 rate += frac_rate; 363 } 364 return rate; 365 case RKCLK_PLL_MODE_DEEP: 366 default: 367 return 32768; 368 } 369 } 370 371 #define RK3588_PLLCON(i) ((i) * 0x4) 372 #define RK3588_PLLCON0_M_MASK 0x3ff << 0 373 #define RK3588_PLLCON0_M_SHIFT 0 374 #define RK3588_PLLCON1_P_MASK 0x3f << 0 375 #define RK3588_PLLCON1_P_SHIFT 0 376 #define RK3588_PLLCON1_S_MASK 0x7 << 6 377 #define RK3588_PLLCON1_S_SHIFT 6 378 #define RK3588_PLLCON2_K_MASK 0xffff 379 #define RK3588_PLLCON2_K_SHIFT 0 380 #define RK3588_PLLCON1_PWRDOWN BIT(13) 381 #define RK3588_PLLCON6_LOCK_STATUS BIT(15) 382 #define RK3588_B0PLL_CLKSEL_CON(i) ((i) * 0x4 + 0x50000 + 0x300) 383 #define RK3588_B1PLL_CLKSEL_CON(i) ((i) * 0x4 + 0x52000 + 0x300) 384 #define RK3588_LPLL_CLKSEL_CON(i) ((i) * 0x4 + 0x58000 + 0x300) 385 #define RK3588_CORE_DIV_MASK 0x1f 386 #define RK3588_CORE_L02_DIV_SHIFT 0 387 #define RK3588_CORE_L13_DIV_SHIFT 7 388 #define RK3588_CORE_B02_DIV_SHIFT 8 389 #define RK3588_CORE_B13_DIV_SHIFT 0 390 391 static int rk3588_pll_set_rate(struct rockchip_pll_clock *pll, 392 void __iomem *base, ulong pll_id, 393 ulong drate) 394 { 395 const struct rockchip_pll_rate_table *rate; 396 397 rate = rockchip_get_pll_settings(pll, drate); 398 if (!rate) { 399 printf("%s unsupported rate\n", __func__); 400 return -EINVAL; 401 } 402 403 debug("%s: rate settings for %lu p: %d, m: %d, s: %d, k: %d\n", 404 __func__, rate->rate, rate->p, rate->m, rate->s, rate->k); 405 406 /* 407 * When power on or changing PLL setting, 408 * we must force PLL into slow mode to ensure output stable clock. 409 */ 410 if (pll_id == 3) 411 rk_clrsetreg(base + 0x84c, 0x1 << 1, 0x1 << 1); 412 413 rk_clrsetreg(base + pll->mode_offset, 414 pll->mode_mask << pll->mode_shift, 415 RKCLK_PLL_MODE_SLOW << pll->mode_shift); 416 if (pll_id == 0) 417 rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(0), 418 pll->mode_mask << 6, 419 RKCLK_PLL_MODE_SLOW << 6); 420 else if (pll_id == 1) 421 rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(0), 422 pll->mode_mask << 6, 423 RKCLK_PLL_MODE_SLOW << 6); 424 else if (pll_id == 2) 425 rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(5), 426 pll->mode_mask << 14, 427 RKCLK_PLL_MODE_SLOW << 14); 428 429 /* Power down */ 430 rk_setreg(base + pll->con_offset + RK3588_PLLCON(1), 431 RK3588_PLLCON1_PWRDOWN); 432 433 rk_clrsetreg(base + pll->con_offset, 434 RK3588_PLLCON0_M_MASK, 435 (rate->m << RK3588_PLLCON0_M_SHIFT)); 436 rk_clrsetreg(base + pll->con_offset + RK3588_PLLCON(1), 437 (RK3588_PLLCON1_P_MASK | 438 RK3588_PLLCON1_S_MASK), 439 (rate->p << RK3588_PLLCON1_P_SHIFT | 440 rate->s << RK3588_PLLCON1_S_SHIFT)); 441 if (!rate->k) { 442 rk_clrsetreg(base + pll->con_offset + RK3588_PLLCON(2), 443 RK3588_PLLCON2_K_MASK, 444 rate->k << RK3588_PLLCON2_K_SHIFT); 445 } 446 /* Power up */ 447 rk_clrreg(base + pll->con_offset + RK3588_PLLCON(1), 448 RK3588_PLLCON1_PWRDOWN); 449 450 /* waiting for pll lock */ 451 while (!(readl(base + pll->con_offset + RK3588_PLLCON(6)) & 452 RK3588_PLLCON6_LOCK_STATUS)) { 453 udelay(1); 454 debug("%s: wait pll lock, pll_id=%ld\n", __func__, pll_id); 455 } 456 457 rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift, 458 RKCLK_PLL_MODE_NORMAL << pll->mode_shift); 459 if (pll_id == 0) { 460 rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(0), 461 pll->mode_mask << 6, 462 2 << 6); 463 rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(0), 464 RK3588_CORE_DIV_MASK << RK3588_CORE_B02_DIV_SHIFT, 465 0 << RK3588_CORE_B02_DIV_SHIFT); 466 rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(1), 467 RK3588_CORE_DIV_MASK << RK3588_CORE_B13_DIV_SHIFT, 468 0 << RK3588_CORE_B13_DIV_SHIFT); 469 } else if (pll_id == 1) { 470 rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(0), 471 pll->mode_mask << 6, 472 2 << 6); 473 rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(0), 474 RK3588_CORE_DIV_MASK << RK3588_CORE_B02_DIV_SHIFT, 475 0 << RK3588_CORE_B02_DIV_SHIFT); 476 rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(1), 477 RK3588_CORE_DIV_MASK << RK3588_CORE_B13_DIV_SHIFT, 478 0 << RK3588_CORE_B13_DIV_SHIFT); 479 } else if (pll_id == 2) { 480 rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(5), 481 pll->mode_mask << 14, 482 2 << 14); 483 rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(6), 484 RK3588_CORE_DIV_MASK << RK3588_CORE_L13_DIV_SHIFT, 485 0 << RK3588_CORE_L13_DIV_SHIFT); 486 rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(6), 487 RK3588_CORE_DIV_MASK << RK3588_CORE_L02_DIV_SHIFT, 488 0 << RK3588_CORE_L02_DIV_SHIFT); 489 rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(7), 490 RK3588_CORE_DIV_MASK << RK3588_CORE_L13_DIV_SHIFT, 491 0 << RK3588_CORE_L13_DIV_SHIFT); 492 rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(7), 493 RK3588_CORE_DIV_MASK << RK3588_CORE_L02_DIV_SHIFT, 494 0 << RK3588_CORE_L02_DIV_SHIFT); 495 } 496 497 if (pll_id == 3) 498 rk_clrsetreg(base + 0x84c, 0x1 << 1, 0); 499 500 debug("PLL at %p: con0=%x con1= %x con2= %x mode= %x\n", 501 pll, readl(base + pll->con_offset), 502 readl(base + pll->con_offset + 0x4), 503 readl(base + pll->con_offset + 0x8), 504 readl(base + pll->mode_offset)); 505 506 return 0; 507 } 508 509 static ulong rk3588_pll_get_rate(struct rockchip_pll_clock *pll, 510 void __iomem *base, ulong pll_id) 511 { 512 u32 m, p, s, k; 513 u32 con = 0, shift, mode; 514 u64 rate, postdiv; 515 516 con = readl(base + pll->mode_offset); 517 shift = pll->mode_shift; 518 if (pll_id == 8) 519 mode = RKCLK_PLL_MODE_NORMAL; 520 else 521 mode = (con & (pll->mode_mask << shift)) >> shift; 522 switch (mode) { 523 case RKCLK_PLL_MODE_SLOW: 524 return OSC_HZ; 525 case RKCLK_PLL_MODE_NORMAL: 526 /* normal mode */ 527 con = readl(base + pll->con_offset); 528 m = (con & RK3588_PLLCON0_M_MASK) >> 529 RK3588_PLLCON0_M_SHIFT; 530 con = readl(base + pll->con_offset + RK3588_PLLCON(1)); 531 p = (con & RK3588_PLLCON1_P_MASK) >> 532 RK3036_PLLCON0_FBDIV_SHIFT; 533 s = (con & RK3588_PLLCON1_S_MASK) >> 534 RK3588_PLLCON1_S_SHIFT; 535 con = readl(base + pll->con_offset + RK3588_PLLCON(2)); 536 k = (con & RK3588_PLLCON2_K_MASK) >> 537 RK3588_PLLCON2_K_SHIFT; 538 539 rate = OSC_HZ / p; 540 rate *= m; 541 if (k) { 542 /* fractional mode */ 543 u64 frac_rate64 = OSC_HZ * k; 544 545 postdiv = p * 65535; 546 do_div(frac_rate64, postdiv); 547 rate += frac_rate64; 548 } 549 rate = rate >> s; 550 return rate; 551 case RKCLK_PLL_MODE_DEEP: 552 default: 553 return 32768; 554 } 555 } 556 557 ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll, 558 void __iomem *base, 559 ulong pll_id) 560 { 561 ulong rate = 0; 562 563 switch (pll->type) { 564 case pll_rk3036: 565 pll->mode_mask = PLL_MODE_MASK; 566 rate = rk3036_pll_get_rate(pll, base, pll_id); 567 break; 568 case pll_rk3328: 569 pll->mode_mask = PLL_RK3328_MODE_MASK; 570 rate = rk3036_pll_get_rate(pll, base, pll_id); 571 break; 572 case pll_rk3588: 573 pll->mode_mask = PLL_MODE_MASK; 574 rate = rk3588_pll_get_rate(pll, base, pll_id); 575 break; 576 default: 577 printf("%s: Unknown pll type for pll clk %ld\n", 578 __func__, pll_id); 579 } 580 return rate; 581 } 582 583 int rockchip_pll_set_rate(struct rockchip_pll_clock *pll, 584 void __iomem *base, ulong pll_id, 585 ulong drate) 586 { 587 int ret = 0; 588 589 if (rockchip_pll_get_rate(pll, base, pll_id) == drate) 590 return 0; 591 592 switch (pll->type) { 593 case pll_rk3036: 594 pll->mode_mask = PLL_MODE_MASK; 595 ret = rk3036_pll_set_rate(pll, base, pll_id, drate); 596 break; 597 case pll_rk3328: 598 pll->mode_mask = PLL_RK3328_MODE_MASK; 599 ret = rk3036_pll_set_rate(pll, base, pll_id, drate); 600 break; 601 case pll_rk3588: 602 pll->mode_mask = PLL_MODE_MASK; 603 ret = rk3588_pll_set_rate(pll, base, pll_id, drate); 604 break; 605 default: 606 printf("%s: Unknown pll type for pll clk %ld\n", 607 __func__, pll_id); 608 } 609 return ret; 610 } 611 612 const struct rockchip_cpu_rate_table * 613 rockchip_get_cpu_settings(struct rockchip_cpu_rate_table *cpu_table, 614 ulong rate) 615 { 616 struct rockchip_cpu_rate_table *ps = cpu_table; 617 618 while (ps->rate) { 619 if (ps->rate == rate) 620 break; 621 ps++; 622 } 623 if (ps->rate != rate) 624 return NULL; 625 else 626 return ps; 627 } 628 629