1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 #include <common.h> 7 #include <bitfield.h> 8 #include <clk-uclass.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <asm/io.h> 12 #include <asm/arch/clock.h> 13 #include <asm/arch/hardware.h> 14 #include <div64.h> 15 16 static struct rockchip_pll_rate_table rockchip_auto_table; 17 18 #define PLL_MODE_MASK 0x3 19 #define PLL_RK3328_MODE_MASK 0x1 20 21 #define RK3036_PLLCON0_FBDIV_MASK 0xfff 22 #define RK3036_PLLCON0_FBDIV_SHIFT 0 23 #define RK3036_PLLCON0_POSTDIV1_MASK 0x7 << 12 24 #define RK3036_PLLCON0_POSTDIV1_SHIFT 12 25 #define RK3036_PLLCON1_REFDIV_MASK 0x3f 26 #define RK3036_PLLCON1_REFDIV_SHIFT 0 27 #define RK3036_PLLCON1_POSTDIV2_MASK 0x7 << 6 28 #define RK3036_PLLCON1_POSTDIV2_SHIFT 6 29 #define RK3036_PLLCON1_DSMPD_MASK 0x1 << 12 30 #define RK3036_PLLCON1_DSMPD_SHIFT 12 31 #define RK3036_PLLCON2_FRAC_MASK 0xffffff 32 #define RK3036_PLLCON2_FRAC_SHIFT 0 33 #define RK3036_PLLCON1_PWRDOWN_SHIT 13 34 35 #define MHZ 1000000 36 #define KHZ 1000 37 enum { 38 OSC_HZ = 24 * 1000000, 39 VCO_MAX_HZ = 3200U * 1000000, 40 VCO_MIN_HZ = 800 * 1000000, 41 OUTPUT_MAX_HZ = 3200U * 1000000, 42 OUTPUT_MIN_HZ = 24 * 1000000, 43 RK3588_VCO_MIN_HZ = 2250U * 1000000, 44 RK3588_VCO_MAX_HZ = 4500U * 1000000, 45 RK3588_FOUT_MIN_HZ = 37U * 1000000, 46 RK3588_FOUT_MAX_HZ = 4500U * 1000000, 47 }; 48 49 #define MIN_FOUTVCO_FREQ (800 * MHZ) 50 #define MAX_FOUTVCO_FREQ (2000 * MHZ) 51 52 int gcd(int m, int n) 53 { 54 int t; 55 56 while (m > 0) { 57 if (n > m) { 58 t = m; 59 m = n; 60 n = t; 61 } /* swap */ 62 m -= n; 63 } 64 return n; 65 } 66 67 /* 68 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63): 69 * Formulas also embedded within the Fractional PLL Verilog model: 70 * If DSMPD = 1 (DSM is disabled, "integer mode") 71 * FOUTVCO = FREF / REFDIV * FBDIV 72 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 73 * Where: 74 * FOUTVCO = Fractional PLL non-divided output frequency 75 * FOUTPOSTDIV = Fractional PLL divided output frequency 76 * (output of second post divider) 77 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input) 78 * REFDIV = Fractional PLL input reference clock divider 79 * FBDIV = Integer value programmed into feedback divide 80 * 81 */ 82 83 static int rockchip_pll_clk_set_postdiv(ulong fout_hz, 84 u32 *postdiv1, 85 u32 *postdiv2, 86 u32 *foutvco) 87 { 88 ulong freq; 89 90 if (fout_hz < MIN_FOUTVCO_FREQ) { 91 for (*postdiv1 = 1; *postdiv1 <= 7; (*postdiv1)++) { 92 for (*postdiv2 = 1; *postdiv2 <= 7; (*postdiv2)++) { 93 freq = fout_hz * (*postdiv1) * (*postdiv2); 94 if (freq >= MIN_FOUTVCO_FREQ && 95 freq <= MAX_FOUTVCO_FREQ) { 96 *foutvco = freq; 97 return 0; 98 } 99 } 100 } 101 printf("Can't FIND postdiv1/2 to make fout=%lu in 800~2000M.\n", 102 fout_hz); 103 } else { 104 *postdiv1 = 1; 105 *postdiv2 = 1; 106 } 107 return 0; 108 } 109 110 static struct rockchip_pll_rate_table * 111 rockchip_pll_clk_set_by_auto(ulong fin_hz, 112 ulong fout_hz) 113 { 114 struct rockchip_pll_rate_table *rate_table = &rockchip_auto_table; 115 /* FIXME set postdiv1/2 always 1*/ 116 u32 foutvco = fout_hz; 117 ulong fin_64, frac_64; 118 u32 f_frac, postdiv1, postdiv2; 119 ulong clk_gcd = 0; 120 121 if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz) 122 return NULL; 123 124 rockchip_pll_clk_set_postdiv(fout_hz, &postdiv1, &postdiv2, &foutvco); 125 rate_table->postdiv1 = postdiv1; 126 rate_table->postdiv2 = postdiv2; 127 rate_table->dsmpd = 1; 128 129 if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MHZ == fout_hz) { 130 fin_hz /= MHZ; 131 foutvco /= MHZ; 132 clk_gcd = gcd(fin_hz, foutvco); 133 rate_table->refdiv = fin_hz / clk_gcd; 134 rate_table->fbdiv = foutvco / clk_gcd; 135 136 rate_table->frac = 0; 137 138 debug("fin = %ld, fout = %ld, clk_gcd = %ld,\n", 139 fin_hz, fout_hz, clk_gcd); 140 debug("refdiv= %d,fbdiv= %d,postdiv1= %d,postdiv2= %d\n", 141 rate_table->refdiv, 142 rate_table->fbdiv, rate_table->postdiv1, 143 rate_table->postdiv2); 144 } else { 145 debug("frac div,fin_hz = %ld,fout_hz = %ld\n", 146 fin_hz, fout_hz); 147 debug("frac get postdiv1 = %d, postdiv2 = %d, foutvco = %d\n", 148 rate_table->postdiv1, rate_table->postdiv2, foutvco); 149 clk_gcd = gcd(fin_hz / MHZ, foutvco / MHZ); 150 rate_table->refdiv = fin_hz / MHZ / clk_gcd; 151 rate_table->fbdiv = foutvco / MHZ / clk_gcd; 152 debug("frac get refdiv = %d, fbdiv = %d\n", 153 rate_table->refdiv, rate_table->fbdiv); 154 155 rate_table->frac = 0; 156 157 f_frac = (foutvco % MHZ); 158 fin_64 = fin_hz; 159 fin_64 = fin_64 / rate_table->refdiv; 160 frac_64 = f_frac << 24; 161 frac_64 = frac_64 / fin_64; 162 rate_table->frac = frac_64; 163 if (rate_table->frac > 0) 164 rate_table->dsmpd = 0; 165 debug("frac = %x\n", rate_table->frac); 166 } 167 return rate_table; 168 } 169 170 static struct rockchip_pll_rate_table * 171 rk3588_pll_clk_set_by_auto(unsigned long fin_hz, 172 unsigned long fout_hz) 173 { 174 struct rockchip_pll_rate_table *rate_table = &rockchip_auto_table; 175 u32 p, m, s; 176 ulong fvco, fref, fout, ffrac; 177 178 if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz) 179 return NULL; 180 181 if (fout_hz > RK3588_FOUT_MAX_HZ || fout_hz < RK3588_FOUT_MIN_HZ) 182 return NULL; 183 184 if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MHZ == fout_hz) { 185 for (s = 0; s <= 6; s++) { 186 fvco = fout_hz << s; 187 if (fvco < RK3588_VCO_MIN_HZ || 188 fvco > RK3588_VCO_MAX_HZ) 189 continue; 190 for (p = 2; p <= 4; p++) { 191 for (m = 64; m <= 1023; m++) { 192 if (fvco == m * fin_hz / p) { 193 rate_table->p = p; 194 rate_table->m = m; 195 rate_table->s = s; 196 rate_table->k = 0; 197 return rate_table; 198 } 199 } 200 } 201 } 202 pr_err("CANNOT FIND Fout by auto,fout = %lu\n", fout_hz); 203 } else { 204 fout = (fout_hz / MHZ) * MHZ; 205 ffrac = (fout_hz % MHZ); 206 for (s = 0; s <= 6; s++) { 207 fvco = fout << s; 208 if (fvco < RK3588_VCO_MIN_HZ || 209 fvco > RK3588_VCO_MAX_HZ) 210 continue; 211 for (p = 1; p <= 4; p++) { 212 for (m = 64; m <= 1023; m++) { 213 if (fvco == m * fin_hz / p) { 214 rate_table->p = p; 215 rate_table->m = m; 216 rate_table->s = s; 217 fref = fin_hz / p; 218 fout = (ffrac << s) * 65535; 219 rate_table->k = fout / fref; 220 return rate_table; 221 } 222 } 223 } 224 } 225 pr_err("CANNOT FIND Fout by auto,fout = %lu\n", fout_hz); 226 } 227 return NULL; 228 } 229 230 static const struct rockchip_pll_rate_table * 231 rockchip_get_pll_settings(struct rockchip_pll_clock *pll, ulong rate) 232 { 233 struct rockchip_pll_rate_table *rate_table = pll->rate_table; 234 235 while (rate_table->rate) { 236 if (rate_table->rate == rate) 237 break; 238 rate_table++; 239 } 240 if (rate_table->rate != rate) { 241 if (pll->type == pll_rk3588) 242 return rk3588_pll_clk_set_by_auto(24 * MHZ, rate); 243 else 244 return rockchip_pll_clk_set_by_auto(24 * MHZ, rate); 245 } else { 246 return rate_table; 247 } 248 } 249 250 static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll, 251 void __iomem *base, ulong pll_id, 252 ulong drate) 253 { 254 const struct rockchip_pll_rate_table *rate; 255 int timeout = 100; 256 257 rate = rockchip_get_pll_settings(pll, drate); 258 if (!rate) { 259 printf("%s unsupport rate\n", __func__); 260 return -EINVAL; 261 } 262 263 debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d\n", 264 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv); 265 debug("%s: rate settings for %lu postdiv2: %d, dsmpd: %d, frac: %d\n", 266 __func__, rate->rate, rate->postdiv2, rate->dsmpd, rate->frac); 267 268 /* 269 * When power on or changing PLL setting, 270 * we must force PLL into slow mode to ensure output stable clock. 271 */ 272 rk_clrsetreg(base + pll->mode_offset, 273 pll->mode_mask << pll->mode_shift, 274 RKCLK_PLL_MODE_SLOW << pll->mode_shift); 275 276 /* Power down */ 277 rk_setreg(base + pll->con_offset + 0x4, 278 1 << RK3036_PLLCON1_PWRDOWN_SHIT); 279 280 rk_clrsetreg(base + pll->con_offset, 281 (RK3036_PLLCON0_POSTDIV1_MASK | 282 RK3036_PLLCON0_FBDIV_MASK), 283 (rate->postdiv1 << RK3036_PLLCON0_POSTDIV1_SHIFT) | 284 rate->fbdiv); 285 rk_clrsetreg(base + pll->con_offset + 0x4, 286 (RK3036_PLLCON1_POSTDIV2_MASK | 287 RK3036_PLLCON1_REFDIV_MASK), 288 (rate->postdiv2 << RK3036_PLLCON1_POSTDIV2_SHIFT | 289 rate->refdiv << RK3036_PLLCON1_REFDIV_SHIFT)); 290 if (!rate->dsmpd) { 291 rk_clrsetreg(base + pll->con_offset + 0x4, 292 RK3036_PLLCON1_DSMPD_MASK, 293 rate->dsmpd << RK3036_PLLCON1_DSMPD_SHIFT); 294 writel((readl(base + pll->con_offset + 0x8) & 295 (~RK3036_PLLCON2_FRAC_MASK)) | 296 (rate->frac << RK3036_PLLCON2_FRAC_SHIFT), 297 base + pll->con_offset + 0x8); 298 } 299 300 /* Power Up */ 301 rk_clrreg(base + pll->con_offset + 0x4, 302 1 << RK3036_PLLCON1_PWRDOWN_SHIT); 303 304 /* waiting for pll lock */ 305 while ((timeout > 0) && !(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift))) { 306 udelay(1); 307 timeout--; 308 } 309 310 if (!(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift))) 311 printf("%s: wait pll lock timeout! pll_id=%ld\n", __func__, pll_id); 312 313 rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift, 314 RKCLK_PLL_MODE_NORMAL << pll->mode_shift); 315 debug("PLL at %p: con0=%x con1= %x con2= %x mode= %x\n", 316 pll, readl(base + pll->con_offset), 317 readl(base + pll->con_offset + 0x4), 318 readl(base + pll->con_offset + 0x8), 319 readl(base + pll->mode_offset)); 320 321 return 0; 322 } 323 324 static ulong rk3036_pll_get_rate(struct rockchip_pll_clock *pll, 325 void __iomem *base, ulong pll_id) 326 { 327 u32 refdiv, fbdiv, postdiv1, postdiv2, dsmpd, frac; 328 u32 con = 0, shift, mask; 329 ulong rate; 330 331 con = readl(base + pll->mode_offset); 332 shift = pll->mode_shift; 333 mask = pll->mode_mask << shift; 334 335 switch ((con & mask) >> shift) { 336 case RKCLK_PLL_MODE_SLOW: 337 return OSC_HZ; 338 case RKCLK_PLL_MODE_NORMAL: 339 /* normal mode */ 340 con = readl(base + pll->con_offset); 341 postdiv1 = (con & RK3036_PLLCON0_POSTDIV1_MASK) >> 342 RK3036_PLLCON0_POSTDIV1_SHIFT; 343 fbdiv = (con & RK3036_PLLCON0_FBDIV_MASK) >> 344 RK3036_PLLCON0_FBDIV_SHIFT; 345 con = readl(base + pll->con_offset + 0x4); 346 postdiv2 = (con & RK3036_PLLCON1_POSTDIV2_MASK) >> 347 RK3036_PLLCON1_POSTDIV2_SHIFT; 348 refdiv = (con & RK3036_PLLCON1_REFDIV_MASK) >> 349 RK3036_PLLCON1_REFDIV_SHIFT; 350 dsmpd = (con & RK3036_PLLCON1_DSMPD_MASK) >> 351 RK3036_PLLCON1_DSMPD_SHIFT; 352 con = readl(base + pll->con_offset + 0x8); 353 frac = (con & RK3036_PLLCON2_FRAC_MASK) >> 354 RK3036_PLLCON2_FRAC_SHIFT; 355 rate = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; 356 if (dsmpd == 0) { 357 u64 frac_rate = OSC_HZ * (u64)frac; 358 359 do_div(frac_rate, refdiv); 360 frac_rate >>= 24; 361 do_div(frac_rate, postdiv1); 362 do_div(frac_rate, postdiv1); 363 rate += frac_rate; 364 } 365 return rate; 366 case RKCLK_PLL_MODE_DEEP: 367 default: 368 return 32768; 369 } 370 } 371 372 #define RK3588_PLLCON(i) ((i) * 0x4) 373 #define RK3588_PLLCON0_M_MASK 0x3ff << 0 374 #define RK3588_PLLCON0_M_SHIFT 0 375 #define RK3588_PLLCON1_P_MASK 0x3f << 0 376 #define RK3588_PLLCON1_P_SHIFT 0 377 #define RK3588_PLLCON1_S_MASK 0x7 << 6 378 #define RK3588_PLLCON1_S_SHIFT 6 379 #define RK3588_PLLCON2_K_MASK 0xffff 380 #define RK3588_PLLCON2_K_SHIFT 0 381 #define RK3588_PLLCON1_PWRDOWN BIT(13) 382 #define RK3588_PLLCON6_LOCK_STATUS BIT(15) 383 #define RK3588_B0PLL_CLKSEL_CON(i) ((i) * 0x4 + 0x50000 + 0x300) 384 #define RK3588_B1PLL_CLKSEL_CON(i) ((i) * 0x4 + 0x52000 + 0x300) 385 #define RK3588_LPLL_CLKSEL_CON(i) ((i) * 0x4 + 0x58000 + 0x300) 386 387 static int rk3588_pll_set_rate(struct rockchip_pll_clock *pll, 388 void __iomem *base, ulong pll_id, 389 ulong drate) 390 { 391 const struct rockchip_pll_rate_table *rate; 392 393 rate = rockchip_get_pll_settings(pll, drate); 394 if (!rate) { 395 printf("%s unsupported rate\n", __func__); 396 return -EINVAL; 397 } 398 399 debug("%s: rate settings for %lu p: %d, m: %d, s: %d, k: %d\n", 400 __func__, rate->rate, rate->p, rate->m, rate->s, rate->k); 401 402 /* 403 * When power on or changing PLL setting, 404 * we must force PLL into slow mode to ensure output stable clock. 405 */ 406 if (pll_id == 3) 407 rk_clrsetreg(base + 0x84c, 0x1 << 1, 0x1 << 1); 408 409 rk_clrsetreg(base + pll->mode_offset, 410 pll->mode_mask << pll->mode_shift, 411 RKCLK_PLL_MODE_SLOW << pll->mode_shift); 412 if (pll_id == 0) 413 rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(0), 414 pll->mode_mask << 6, 415 RKCLK_PLL_MODE_SLOW << 6); 416 else if (pll_id == 1) 417 rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(0), 418 pll->mode_mask << 6, 419 RKCLK_PLL_MODE_SLOW << 6); 420 else if (pll_id == 2) 421 rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(5), 422 pll->mode_mask << 14, 423 RKCLK_PLL_MODE_SLOW << 14); 424 425 /* Power down */ 426 rk_setreg(base + pll->con_offset + RK3588_PLLCON(1), 427 RK3588_PLLCON1_PWRDOWN); 428 429 rk_clrsetreg(base + pll->con_offset, 430 RK3588_PLLCON0_M_MASK, 431 (rate->m << RK3588_PLLCON0_M_SHIFT)); 432 rk_clrsetreg(base + pll->con_offset + RK3588_PLLCON(1), 433 (RK3588_PLLCON1_P_MASK | 434 RK3588_PLLCON1_S_MASK), 435 (rate->p << RK3588_PLLCON1_P_SHIFT | 436 rate->s << RK3588_PLLCON1_S_SHIFT)); 437 if (!rate->k) { 438 rk_clrsetreg(base + pll->con_offset + RK3588_PLLCON(2), 439 RK3588_PLLCON2_K_MASK, 440 rate->k << RK3588_PLLCON2_K_SHIFT); 441 } 442 /* Power up */ 443 rk_clrreg(base + pll->con_offset + RK3588_PLLCON(1), 444 RK3588_PLLCON1_PWRDOWN); 445 446 /* waiting for pll lock */ 447 while (!(readl(base + pll->con_offset + RK3588_PLLCON(6)) & 448 RK3588_PLLCON6_LOCK_STATUS)) { 449 udelay(1); 450 debug("%s: wait pll lock, pll_id=%ld\n", __func__, pll_id); 451 } 452 453 rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift, 454 RKCLK_PLL_MODE_NORMAL << pll->mode_shift); 455 if (pll_id == 0) 456 rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(0), 457 pll->mode_mask << 6, 458 2 << 6); 459 else if (pll_id == 1) 460 rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(0), 461 pll->mode_mask << 6, 462 2 << 6); 463 else if (pll_id == 2) 464 rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(5), 465 pll->mode_mask << 14, 466 2 << 14); 467 468 if (pll_id == 3) 469 rk_clrsetreg(base + 0x84c, 0x1 << 1, 0); 470 471 debug("PLL at %p: con0=%x con1= %x con2= %x mode= %x\n", 472 pll, readl(base + pll->con_offset), 473 readl(base + pll->con_offset + 0x4), 474 readl(base + pll->con_offset + 0x8), 475 readl(base + pll->mode_offset)); 476 477 return 0; 478 } 479 480 static ulong rk3588_pll_get_rate(struct rockchip_pll_clock *pll, 481 void __iomem *base, ulong pll_id) 482 { 483 u32 m, p, s, k; 484 u32 con = 0, shift, mode; 485 u64 rate, postdiv; 486 487 con = readl(base + pll->mode_offset); 488 shift = pll->mode_shift; 489 if (pll_id == 8) 490 mode = RKCLK_PLL_MODE_NORMAL; 491 else 492 mode = (con & (pll->mode_mask << shift)) >> shift; 493 switch (mode) { 494 case RKCLK_PLL_MODE_SLOW: 495 return OSC_HZ; 496 case RKCLK_PLL_MODE_NORMAL: 497 /* normal mode */ 498 con = readl(base + pll->con_offset); 499 m = (con & RK3588_PLLCON0_M_MASK) >> 500 RK3588_PLLCON0_M_SHIFT; 501 con = readl(base + pll->con_offset + RK3588_PLLCON(1)); 502 p = (con & RK3588_PLLCON1_P_MASK) >> 503 RK3036_PLLCON0_FBDIV_SHIFT; 504 s = (con & RK3588_PLLCON1_S_MASK) >> 505 RK3588_PLLCON1_S_SHIFT; 506 con = readl(base + pll->con_offset + RK3588_PLLCON(2)); 507 k = (con & RK3588_PLLCON2_K_MASK) >> 508 RK3588_PLLCON2_K_SHIFT; 509 510 rate = OSC_HZ / p; 511 rate *= m; 512 if (k) { 513 /* fractional mode */ 514 u64 frac_rate64 = OSC_HZ * k; 515 516 postdiv = p * 65535; 517 do_div(frac_rate64, postdiv); 518 rate += frac_rate64; 519 } 520 rate = rate >> s; 521 return rate; 522 case RKCLK_PLL_MODE_DEEP: 523 default: 524 return 32768; 525 } 526 } 527 528 ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll, 529 void __iomem *base, 530 ulong pll_id) 531 { 532 ulong rate = 0; 533 534 switch (pll->type) { 535 case pll_rk3036: 536 pll->mode_mask = PLL_MODE_MASK; 537 rate = rk3036_pll_get_rate(pll, base, pll_id); 538 break; 539 case pll_rk3328: 540 pll->mode_mask = PLL_RK3328_MODE_MASK; 541 rate = rk3036_pll_get_rate(pll, base, pll_id); 542 break; 543 case pll_rk3588: 544 pll->mode_mask = PLL_MODE_MASK; 545 rate = rk3588_pll_get_rate(pll, base, pll_id); 546 break; 547 default: 548 printf("%s: Unknown pll type for pll clk %ld\n", 549 __func__, pll_id); 550 } 551 return rate; 552 } 553 554 int rockchip_pll_set_rate(struct rockchip_pll_clock *pll, 555 void __iomem *base, ulong pll_id, 556 ulong drate) 557 { 558 int ret = 0; 559 560 if (rockchip_pll_get_rate(pll, base, pll_id) == drate) 561 return 0; 562 563 switch (pll->type) { 564 case pll_rk3036: 565 pll->mode_mask = PLL_MODE_MASK; 566 ret = rk3036_pll_set_rate(pll, base, pll_id, drate); 567 break; 568 case pll_rk3328: 569 pll->mode_mask = PLL_RK3328_MODE_MASK; 570 ret = rk3036_pll_set_rate(pll, base, pll_id, drate); 571 break; 572 case pll_rk3588: 573 pll->mode_mask = PLL_MODE_MASK; 574 ret = rk3588_pll_set_rate(pll, base, pll_id, drate); 575 break; 576 default: 577 printf("%s: Unknown pll type for pll clk %ld\n", 578 __func__, pll_id); 579 } 580 return ret; 581 } 582 583 const struct rockchip_cpu_rate_table * 584 rockchip_get_cpu_settings(struct rockchip_cpu_rate_table *cpu_table, 585 ulong rate) 586 { 587 struct rockchip_cpu_rate_table *ps = cpu_table; 588 589 while (ps->rate) { 590 if (ps->rate == rate) 591 break; 592 ps++; 593 } 594 if (ps->rate != rate) 595 return NULL; 596 else 597 return ps; 598 } 599 600