1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 #include <common.h> 7 #include <bitfield.h> 8 #include <clk-uclass.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <asm/io.h> 12 #include <asm/arch/clock.h> 13 #include <asm/arch/hardware.h> 14 #include <div64.h> 15 16 static struct rockchip_pll_rate_table rockchip_auto_table; 17 18 #define PLL_MODE_MASK 0x3 19 #define PLL_RK3328_MODE_MASK 0x1 20 21 #define RK3036_PLLCON0_FBDIV_MASK 0xfff 22 #define RK3036_PLLCON0_FBDIV_SHIFT 0 23 #define RK3036_PLLCON0_POSTDIV1_MASK 0x7 << 12 24 #define RK3036_PLLCON0_POSTDIV1_SHIFT 12 25 #define RK3036_PLLCON1_REFDIV_MASK 0x3f 26 #define RK3036_PLLCON1_REFDIV_SHIFT 0 27 #define RK3036_PLLCON1_POSTDIV2_MASK 0x7 << 6 28 #define RK3036_PLLCON1_POSTDIV2_SHIFT 6 29 #define RK3036_PLLCON1_DSMPD_MASK 0x1 << 12 30 #define RK3036_PLLCON1_DSMPD_SHIFT 12 31 #define RK3036_PLLCON2_FRAC_MASK 0xffffff 32 #define RK3036_PLLCON2_FRAC_SHIFT 0 33 #define RK3036_PLLCON1_PWRDOWN_SHIT 13 34 35 #define MHZ 1000000 36 #define KHZ 1000 37 38 #define OSC_HZ (24UL * MHZ) 39 #define VCO_MAX_HZ (3200UL * MHZ) 40 #define VCO_MIN_HZ (800UL * MHZ) 41 #define OUTPUT_MAX_HZ (3200UL * MHZ) 42 #define OUTPUT_MIN_HZ (24UL * MHZ) 43 #define MIN_FOUTVCO_FREQ (800UL * MHZ) 44 #define MAX_FOUTVCO_FREQ (2000UL * MHZ) 45 46 #define RK3588_VCO_MIN_HZ (2250UL * MHZ) 47 #define RK3588_VCO_MAX_HZ (4500UL * MHZ) 48 #define RK3588_FOUT_MIN_HZ (37UL * MHZ) 49 #define RK3588_FOUT_MAX_HZ (4500UL * MHZ) 50 51 int gcd(int m, int n) 52 { 53 int t; 54 55 while (m > 0) { 56 if (n > m) { 57 t = m; 58 m = n; 59 n = t; 60 } /* swap */ 61 m -= n; 62 } 63 return n; 64 } 65 66 /* 67 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63): 68 * Formulas also embedded within the Fractional PLL Verilog model: 69 * If DSMPD = 1 (DSM is disabled, "integer mode") 70 * FOUTVCO = FREF / REFDIV * FBDIV 71 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 72 * Where: 73 * FOUTVCO = Fractional PLL non-divided output frequency 74 * FOUTPOSTDIV = Fractional PLL divided output frequency 75 * (output of second post divider) 76 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input) 77 * REFDIV = Fractional PLL input reference clock divider 78 * FBDIV = Integer value programmed into feedback divide 79 * 80 */ 81 82 static int rockchip_pll_clk_set_postdiv(ulong fout_hz, 83 u32 *postdiv1, 84 u32 *postdiv2, 85 u32 *foutvco) 86 { 87 ulong freq; 88 89 if (fout_hz < MIN_FOUTVCO_FREQ) { 90 for (*postdiv1 = 1; *postdiv1 <= 7; (*postdiv1)++) { 91 for (*postdiv2 = 1; *postdiv2 <= 7; (*postdiv2)++) { 92 freq = fout_hz * (*postdiv1) * (*postdiv2); 93 if (freq >= MIN_FOUTVCO_FREQ && 94 freq <= MAX_FOUTVCO_FREQ) { 95 *foutvco = freq; 96 return 0; 97 } 98 } 99 } 100 printf("Can't FIND postdiv1/2 to make fout=%lu in 800~2000M.\n", 101 fout_hz); 102 } else { 103 *postdiv1 = 1; 104 *postdiv2 = 1; 105 } 106 return 0; 107 } 108 109 static struct rockchip_pll_rate_table * 110 rockchip_pll_clk_set_by_auto(ulong fin_hz, 111 ulong fout_hz) 112 { 113 struct rockchip_pll_rate_table *rate_table = &rockchip_auto_table; 114 /* FIXME set postdiv1/2 always 1*/ 115 u32 foutvco = fout_hz; 116 ulong fin_64, frac_64; 117 u32 f_frac, postdiv1, postdiv2; 118 ulong clk_gcd = 0; 119 120 if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz) 121 return NULL; 122 123 rockchip_pll_clk_set_postdiv(fout_hz, &postdiv1, &postdiv2, &foutvco); 124 rate_table->postdiv1 = postdiv1; 125 rate_table->postdiv2 = postdiv2; 126 rate_table->dsmpd = 1; 127 128 if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MHZ == fout_hz) { 129 fin_hz /= MHZ; 130 foutvco /= MHZ; 131 clk_gcd = gcd(fin_hz, foutvco); 132 rate_table->refdiv = fin_hz / clk_gcd; 133 rate_table->fbdiv = foutvco / clk_gcd; 134 135 rate_table->frac = 0; 136 137 debug("fin = %ld, fout = %ld, clk_gcd = %ld,\n", 138 fin_hz, fout_hz, clk_gcd); 139 debug("refdiv= %d,fbdiv= %d,postdiv1= %d,postdiv2= %d\n", 140 rate_table->refdiv, 141 rate_table->fbdiv, rate_table->postdiv1, 142 rate_table->postdiv2); 143 } else { 144 debug("frac div,fin_hz = %ld,fout_hz = %ld\n", 145 fin_hz, fout_hz); 146 debug("frac get postdiv1 = %d, postdiv2 = %d, foutvco = %d\n", 147 rate_table->postdiv1, rate_table->postdiv2, foutvco); 148 clk_gcd = gcd(fin_hz / MHZ, foutvco / MHZ); 149 rate_table->refdiv = fin_hz / MHZ / clk_gcd; 150 rate_table->fbdiv = foutvco / MHZ / clk_gcd; 151 debug("frac get refdiv = %d, fbdiv = %d\n", 152 rate_table->refdiv, rate_table->fbdiv); 153 154 rate_table->frac = 0; 155 156 f_frac = (foutvco % MHZ); 157 fin_64 = fin_hz; 158 fin_64 = fin_64 / rate_table->refdiv; 159 frac_64 = f_frac << 24; 160 frac_64 = frac_64 / fin_64; 161 rate_table->frac = frac_64; 162 if (rate_table->frac > 0) 163 rate_table->dsmpd = 0; 164 debug("frac = %x\n", rate_table->frac); 165 } 166 return rate_table; 167 } 168 169 static struct rockchip_pll_rate_table * 170 rk3588_pll_clk_set_by_auto(unsigned long fin_hz, 171 unsigned long fout_hz) 172 { 173 struct rockchip_pll_rate_table *rate_table = &rockchip_auto_table; 174 u32 p, m, s; 175 ulong fvco, fref, fout, ffrac; 176 177 if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz) 178 return NULL; 179 180 if (fout_hz > RK3588_FOUT_MAX_HZ || fout_hz < RK3588_FOUT_MIN_HZ) 181 return NULL; 182 183 if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MHZ == fout_hz) { 184 for (s = 0; s <= 6; s++) { 185 fvco = fout_hz << s; 186 if (fvco < RK3588_VCO_MIN_HZ || 187 fvco > RK3588_VCO_MAX_HZ) 188 continue; 189 for (p = 2; p <= 4; p++) { 190 for (m = 64; m <= 1023; m++) { 191 if (fvco == m * fin_hz / p) { 192 rate_table->p = p; 193 rate_table->m = m; 194 rate_table->s = s; 195 rate_table->k = 0; 196 return rate_table; 197 } 198 } 199 } 200 } 201 pr_err("CANNOT FIND Fout by auto,fout = %lu\n", fout_hz); 202 } else { 203 for (s = 0; s <= 6; s++) { 204 fvco = fout_hz << s; 205 if (fvco < RK3588_VCO_MIN_HZ || 206 fvco > RK3588_VCO_MAX_HZ) 207 continue; 208 for (p = 1; p <= 4; p++) { 209 for (m = 64; m <= 1023; m++) { 210 if ((fvco >= m * fin_hz / p) && (fvco < (m + 1) * fin_hz / p)) { 211 rate_table->p = p; 212 rate_table->m = m; 213 rate_table->s = s; 214 fref = fin_hz / p; 215 ffrac = fvco - (m * fref); 216 fout = ffrac * 65536; 217 rate_table->k = fout / fref; 218 return rate_table; 219 } 220 } 221 } 222 } 223 pr_err("CANNOT FIND Fout by auto,fout = %lu\n", fout_hz); 224 } 225 return NULL; 226 } 227 228 static const struct rockchip_pll_rate_table * 229 rockchip_get_pll_settings(struct rockchip_pll_clock *pll, ulong rate) 230 { 231 struct rockchip_pll_rate_table *rate_table = pll->rate_table; 232 233 while (rate_table->rate) { 234 if (rate_table->rate == rate) 235 break; 236 rate_table++; 237 } 238 if (rate_table->rate != rate) { 239 if (pll->type == pll_rk3588) 240 return rk3588_pll_clk_set_by_auto(24 * MHZ, rate); 241 else 242 return rockchip_pll_clk_set_by_auto(24 * MHZ, rate); 243 } else { 244 return rate_table; 245 } 246 } 247 248 static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll, 249 void __iomem *base, ulong pll_id, 250 ulong drate) 251 { 252 const struct rockchip_pll_rate_table *rate; 253 int timeout = 100; 254 255 rate = rockchip_get_pll_settings(pll, drate); 256 if (!rate) { 257 printf("%s unsupport rate\n", __func__); 258 return -EINVAL; 259 } 260 261 debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d\n", 262 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv); 263 debug("%s: rate settings for %lu postdiv2: %d, dsmpd: %d, frac: %d\n", 264 __func__, rate->rate, rate->postdiv2, rate->dsmpd, rate->frac); 265 266 /* 267 * When power on or changing PLL setting, 268 * we must force PLL into slow mode to ensure output stable clock. 269 */ 270 rk_clrsetreg(base + pll->mode_offset, 271 pll->mode_mask << pll->mode_shift, 272 RKCLK_PLL_MODE_SLOW << pll->mode_shift); 273 274 /* Power down */ 275 rk_setreg(base + pll->con_offset + 0x4, 276 1 << RK3036_PLLCON1_PWRDOWN_SHIT); 277 278 rk_clrsetreg(base + pll->con_offset, 279 (RK3036_PLLCON0_POSTDIV1_MASK | 280 RK3036_PLLCON0_FBDIV_MASK), 281 (rate->postdiv1 << RK3036_PLLCON0_POSTDIV1_SHIFT) | 282 rate->fbdiv); 283 rk_clrsetreg(base + pll->con_offset + 0x4, 284 (RK3036_PLLCON1_POSTDIV2_MASK | 285 RK3036_PLLCON1_REFDIV_MASK), 286 (rate->postdiv2 << RK3036_PLLCON1_POSTDIV2_SHIFT | 287 rate->refdiv << RK3036_PLLCON1_REFDIV_SHIFT)); 288 if (!rate->dsmpd) { 289 rk_clrsetreg(base + pll->con_offset + 0x4, 290 RK3036_PLLCON1_DSMPD_MASK, 291 rate->dsmpd << RK3036_PLLCON1_DSMPD_SHIFT); 292 writel((readl(base + pll->con_offset + 0x8) & 293 (~RK3036_PLLCON2_FRAC_MASK)) | 294 (rate->frac << RK3036_PLLCON2_FRAC_SHIFT), 295 base + pll->con_offset + 0x8); 296 } 297 298 /* Power Up */ 299 rk_clrreg(base + pll->con_offset + 0x4, 300 1 << RK3036_PLLCON1_PWRDOWN_SHIT); 301 302 /* waiting for pll lock */ 303 while ((timeout > 0) && !(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift))) { 304 udelay(1); 305 timeout--; 306 } 307 308 if (!(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift))) 309 printf("%s: wait pll lock timeout! pll_id=%ld\n", __func__, pll_id); 310 311 rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift, 312 RKCLK_PLL_MODE_NORMAL << pll->mode_shift); 313 debug("PLL at %p: con0=%x con1= %x con2= %x mode= %x\n", 314 pll, readl(base + pll->con_offset), 315 readl(base + pll->con_offset + 0x4), 316 readl(base + pll->con_offset + 0x8), 317 readl(base + pll->mode_offset)); 318 319 return 0; 320 } 321 322 static ulong rk3036_pll_get_rate(struct rockchip_pll_clock *pll, 323 void __iomem *base, ulong pll_id) 324 { 325 u32 refdiv, fbdiv, postdiv1, postdiv2, dsmpd, frac; 326 u32 con = 0, shift, mask; 327 ulong rate; 328 329 con = readl(base + pll->mode_offset); 330 shift = pll->mode_shift; 331 mask = pll->mode_mask << shift; 332 333 switch ((con & mask) >> shift) { 334 case RKCLK_PLL_MODE_SLOW: 335 return OSC_HZ; 336 case RKCLK_PLL_MODE_NORMAL: 337 /* normal mode */ 338 con = readl(base + pll->con_offset); 339 postdiv1 = (con & RK3036_PLLCON0_POSTDIV1_MASK) >> 340 RK3036_PLLCON0_POSTDIV1_SHIFT; 341 fbdiv = (con & RK3036_PLLCON0_FBDIV_MASK) >> 342 RK3036_PLLCON0_FBDIV_SHIFT; 343 con = readl(base + pll->con_offset + 0x4); 344 postdiv2 = (con & RK3036_PLLCON1_POSTDIV2_MASK) >> 345 RK3036_PLLCON1_POSTDIV2_SHIFT; 346 refdiv = (con & RK3036_PLLCON1_REFDIV_MASK) >> 347 RK3036_PLLCON1_REFDIV_SHIFT; 348 dsmpd = (con & RK3036_PLLCON1_DSMPD_MASK) >> 349 RK3036_PLLCON1_DSMPD_SHIFT; 350 con = readl(base + pll->con_offset + 0x8); 351 frac = (con & RK3036_PLLCON2_FRAC_MASK) >> 352 RK3036_PLLCON2_FRAC_SHIFT; 353 rate = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; 354 if (dsmpd == 0) { 355 u64 frac_rate = OSC_HZ * (u64)frac; 356 357 do_div(frac_rate, refdiv); 358 frac_rate >>= 24; 359 do_div(frac_rate, postdiv1); 360 do_div(frac_rate, postdiv1); 361 rate += frac_rate; 362 } 363 return rate; 364 case RKCLK_PLL_MODE_DEEP: 365 default: 366 return 32768; 367 } 368 } 369 370 #define RK3588_PLLCON(i) ((i) * 0x4) 371 #define RK3588_PLLCON0_M_MASK 0x3ff << 0 372 #define RK3588_PLLCON0_M_SHIFT 0 373 #define RK3588_PLLCON1_P_MASK 0x3f << 0 374 #define RK3588_PLLCON1_P_SHIFT 0 375 #define RK3588_PLLCON1_S_MASK 0x7 << 6 376 #define RK3588_PLLCON1_S_SHIFT 6 377 #define RK3588_PLLCON2_K_MASK 0xffff 378 #define RK3588_PLLCON2_K_SHIFT 0 379 #define RK3588_PLLCON1_PWRDOWN BIT(13) 380 #define RK3588_PLLCON6_LOCK_STATUS BIT(15) 381 #define RK3588_B0PLL_CLKSEL_CON(i) ((i) * 0x4 + 0x50000 + 0x300) 382 #define RK3588_B1PLL_CLKSEL_CON(i) ((i) * 0x4 + 0x52000 + 0x300) 383 #define RK3588_LPLL_CLKSEL_CON(i) ((i) * 0x4 + 0x58000 + 0x300) 384 #define RK3588_CORE_DIV_MASK 0x1f 385 #define RK3588_CORE_L02_DIV_SHIFT 0 386 #define RK3588_CORE_L13_DIV_SHIFT 7 387 #define RK3588_CORE_B02_DIV_SHIFT 8 388 #define RK3588_CORE_B13_DIV_SHIFT 0 389 390 static int rk3588_pll_set_rate(struct rockchip_pll_clock *pll, 391 void __iomem *base, ulong pll_id, 392 ulong drate) 393 { 394 const struct rockchip_pll_rate_table *rate; 395 396 rate = rockchip_get_pll_settings(pll, drate); 397 if (!rate) { 398 printf("%s unsupported rate\n", __func__); 399 return -EINVAL; 400 } 401 402 debug("%s: rate settings for %lu p: %d, m: %d, s: %d, k: %d\n", 403 __func__, rate->rate, rate->p, rate->m, rate->s, rate->k); 404 405 /* 406 * When power on or changing PLL setting, 407 * we must force PLL into slow mode to ensure output stable clock. 408 */ 409 if (pll_id == 3) 410 rk_clrsetreg(base + 0x84c, 0x1 << 1, 0x1 << 1); 411 412 rk_clrsetreg(base + pll->mode_offset, 413 pll->mode_mask << pll->mode_shift, 414 RKCLK_PLL_MODE_SLOW << pll->mode_shift); 415 if (pll_id == 0) 416 rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(0), 417 pll->mode_mask << 6, 418 RKCLK_PLL_MODE_SLOW << 6); 419 else if (pll_id == 1) 420 rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(0), 421 pll->mode_mask << 6, 422 RKCLK_PLL_MODE_SLOW << 6); 423 else if (pll_id == 2) 424 rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(5), 425 pll->mode_mask << 14, 426 RKCLK_PLL_MODE_SLOW << 14); 427 428 /* Power down */ 429 rk_setreg(base + pll->con_offset + RK3588_PLLCON(1), 430 RK3588_PLLCON1_PWRDOWN); 431 432 rk_clrsetreg(base + pll->con_offset, 433 RK3588_PLLCON0_M_MASK, 434 (rate->m << RK3588_PLLCON0_M_SHIFT)); 435 rk_clrsetreg(base + pll->con_offset + RK3588_PLLCON(1), 436 (RK3588_PLLCON1_P_MASK | 437 RK3588_PLLCON1_S_MASK), 438 (rate->p << RK3588_PLLCON1_P_SHIFT | 439 rate->s << RK3588_PLLCON1_S_SHIFT)); 440 if (rate->k) { 441 rk_clrsetreg(base + pll->con_offset + RK3588_PLLCON(2), 442 RK3588_PLLCON2_K_MASK, 443 rate->k << RK3588_PLLCON2_K_SHIFT); 444 } 445 /* Power up */ 446 rk_clrreg(base + pll->con_offset + RK3588_PLLCON(1), 447 RK3588_PLLCON1_PWRDOWN); 448 449 /* waiting for pll lock */ 450 while (!(readl(base + pll->con_offset + RK3588_PLLCON(6)) & 451 RK3588_PLLCON6_LOCK_STATUS)) { 452 udelay(1); 453 debug("%s: wait pll lock, pll_id=%ld\n", __func__, pll_id); 454 } 455 456 rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift, 457 RKCLK_PLL_MODE_NORMAL << pll->mode_shift); 458 if (pll_id == 0) { 459 rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(0), 460 pll->mode_mask << 6, 461 2 << 6); 462 rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(0), 463 RK3588_CORE_DIV_MASK << RK3588_CORE_B02_DIV_SHIFT, 464 0 << RK3588_CORE_B02_DIV_SHIFT); 465 rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(1), 466 RK3588_CORE_DIV_MASK << RK3588_CORE_B13_DIV_SHIFT, 467 0 << RK3588_CORE_B13_DIV_SHIFT); 468 } else if (pll_id == 1) { 469 rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(0), 470 pll->mode_mask << 6, 471 2 << 6); 472 rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(0), 473 RK3588_CORE_DIV_MASK << RK3588_CORE_B02_DIV_SHIFT, 474 0 << RK3588_CORE_B02_DIV_SHIFT); 475 rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(1), 476 RK3588_CORE_DIV_MASK << RK3588_CORE_B13_DIV_SHIFT, 477 0 << RK3588_CORE_B13_DIV_SHIFT); 478 } else if (pll_id == 2) { 479 rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(5), 480 pll->mode_mask << 14, 481 2 << 14); 482 rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(6), 483 RK3588_CORE_DIV_MASK << RK3588_CORE_L13_DIV_SHIFT, 484 0 << RK3588_CORE_L13_DIV_SHIFT); 485 rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(6), 486 RK3588_CORE_DIV_MASK << RK3588_CORE_L02_DIV_SHIFT, 487 0 << RK3588_CORE_L02_DIV_SHIFT); 488 rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(7), 489 RK3588_CORE_DIV_MASK << RK3588_CORE_L13_DIV_SHIFT, 490 0 << RK3588_CORE_L13_DIV_SHIFT); 491 rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(7), 492 RK3588_CORE_DIV_MASK << RK3588_CORE_L02_DIV_SHIFT, 493 0 << RK3588_CORE_L02_DIV_SHIFT); 494 } 495 496 if (pll_id == 3) 497 rk_clrsetreg(base + 0x84c, 0x1 << 1, 0); 498 499 debug("PLL at %p: con0=%x con1= %x con2= %x mode= %x\n", 500 pll, readl(base + pll->con_offset), 501 readl(base + pll->con_offset + 0x4), 502 readl(base + pll->con_offset + 0x8), 503 readl(base + pll->mode_offset)); 504 505 return 0; 506 } 507 508 static ulong rk3588_pll_get_rate(struct rockchip_pll_clock *pll, 509 void __iomem *base, ulong pll_id) 510 { 511 u32 m, p, s, k; 512 u32 con = 0, shift, mode; 513 u64 rate, postdiv; 514 515 con = readl(base + pll->mode_offset); 516 shift = pll->mode_shift; 517 if (pll_id == 8) 518 mode = RKCLK_PLL_MODE_NORMAL; 519 else 520 mode = (con & (pll->mode_mask << shift)) >> shift; 521 switch (mode) { 522 case RKCLK_PLL_MODE_SLOW: 523 return OSC_HZ; 524 case RKCLK_PLL_MODE_NORMAL: 525 /* normal mode */ 526 con = readl(base + pll->con_offset); 527 m = (con & RK3588_PLLCON0_M_MASK) >> 528 RK3588_PLLCON0_M_SHIFT; 529 con = readl(base + pll->con_offset + RK3588_PLLCON(1)); 530 p = (con & RK3588_PLLCON1_P_MASK) >> 531 RK3036_PLLCON0_FBDIV_SHIFT; 532 s = (con & RK3588_PLLCON1_S_MASK) >> 533 RK3588_PLLCON1_S_SHIFT; 534 con = readl(base + pll->con_offset + RK3588_PLLCON(2)); 535 k = (con & RK3588_PLLCON2_K_MASK) >> 536 RK3588_PLLCON2_K_SHIFT; 537 538 rate = OSC_HZ / p; 539 rate *= m; 540 if (k) { 541 /* fractional mode */ 542 u64 frac_rate64 = OSC_HZ * k; 543 544 postdiv = p * 65536; 545 do_div(frac_rate64, postdiv); 546 rate += frac_rate64; 547 } 548 rate = rate >> s; 549 return rate; 550 case RKCLK_PLL_MODE_DEEP: 551 default: 552 return 32768; 553 } 554 } 555 556 ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll, 557 void __iomem *base, 558 ulong pll_id) 559 { 560 ulong rate = 0; 561 562 switch (pll->type) { 563 case pll_rk3036: 564 pll->mode_mask = PLL_MODE_MASK; 565 rate = rk3036_pll_get_rate(pll, base, pll_id); 566 break; 567 case pll_rk3328: 568 pll->mode_mask = PLL_RK3328_MODE_MASK; 569 rate = rk3036_pll_get_rate(pll, base, pll_id); 570 break; 571 case pll_rk3588: 572 pll->mode_mask = PLL_MODE_MASK; 573 rate = rk3588_pll_get_rate(pll, base, pll_id); 574 break; 575 default: 576 printf("%s: Unknown pll type for pll clk %ld\n", 577 __func__, pll_id); 578 } 579 return rate; 580 } 581 582 int rockchip_pll_set_rate(struct rockchip_pll_clock *pll, 583 void __iomem *base, ulong pll_id, 584 ulong drate) 585 { 586 int ret = 0; 587 588 if (rockchip_pll_get_rate(pll, base, pll_id) == drate) 589 return 0; 590 591 switch (pll->type) { 592 case pll_rk3036: 593 pll->mode_mask = PLL_MODE_MASK; 594 ret = rk3036_pll_set_rate(pll, base, pll_id, drate); 595 break; 596 case pll_rk3328: 597 pll->mode_mask = PLL_RK3328_MODE_MASK; 598 ret = rk3036_pll_set_rate(pll, base, pll_id, drate); 599 break; 600 case pll_rk3588: 601 pll->mode_mask = PLL_MODE_MASK; 602 ret = rk3588_pll_set_rate(pll, base, pll_id, drate); 603 break; 604 default: 605 printf("%s: Unknown pll type for pll clk %ld\n", 606 __func__, pll_id); 607 } 608 return ret; 609 } 610 611 const struct rockchip_cpu_rate_table * 612 rockchip_get_cpu_settings(struct rockchip_cpu_rate_table *cpu_table, 613 ulong rate) 614 { 615 struct rockchip_cpu_rate_table *ps = cpu_table; 616 617 while (ps->rate) { 618 if (ps->rate == rate) 619 break; 620 ps++; 621 } 622 if (ps->rate != rate) 623 return NULL; 624 else 625 return ps; 626 } 627 628