1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 #include <common.h> 7 #include <bitfield.h> 8 #include <clk-uclass.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <asm/io.h> 12 #include <asm/arch/clock.h> 13 #include <asm/arch/hardware.h> 14 #include <div64.h> 15 16 static struct rockchip_pll_rate_table rockchip_auto_table; 17 18 #define PLL_MODE_MASK 0x3 19 #define PLL_RK3328_MODE_MASK 0x1 20 21 #define RK3036_PLLCON0_FBDIV_MASK 0xfff 22 #define RK3036_PLLCON0_FBDIV_SHIFT 0 23 #define RK3036_PLLCON0_POSTDIV1_MASK 0x7 << 12 24 #define RK3036_PLLCON0_POSTDIV1_SHIFT 12 25 #define RK3036_PLLCON1_REFDIV_MASK 0x3f 26 #define RK3036_PLLCON1_REFDIV_SHIFT 0 27 #define RK3036_PLLCON1_POSTDIV2_MASK 0x7 << 6 28 #define RK3036_PLLCON1_POSTDIV2_SHIFT 6 29 #define RK3036_PLLCON1_DSMPD_MASK 0x1 << 12 30 #define RK3036_PLLCON1_DSMPD_SHIFT 12 31 #define RK3036_PLLCON2_FRAC_MASK 0xffffff 32 #define RK3036_PLLCON2_FRAC_SHIFT 0 33 #define RK3036_PLLCON1_PWRDOWN_SHIT 13 34 35 #define MHZ 1000000 36 #define KHZ 1000 37 enum { 38 OSC_HZ = 24 * 1000000, 39 VCO_MAX_HZ = 3200U * 1000000, 40 VCO_MIN_HZ = 800 * 1000000, 41 OUTPUT_MAX_HZ = 3200U * 1000000, 42 OUTPUT_MIN_HZ = 24 * 1000000, 43 RK3588_VCO_MIN_HZ = 2250U * 1000000, 44 RK3588_VCO_MAX_HZ = 4500U * 1000000, 45 RK3588_FOUT_MIN_HZ = 37U * 1000000, 46 RK3588_FOUT_MAX_HZ = 4500U * 1000000, 47 }; 48 49 #define MIN_FOUTVCO_FREQ (800 * MHZ) 50 #define MAX_FOUTVCO_FREQ (2000 * MHZ) 51 52 int gcd(int m, int n) 53 { 54 int t; 55 56 while (m > 0) { 57 if (n > m) { 58 t = m; 59 m = n; 60 n = t; 61 } /* swap */ 62 m -= n; 63 } 64 return n; 65 } 66 67 /* 68 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63): 69 * Formulas also embedded within the Fractional PLL Verilog model: 70 * If DSMPD = 1 (DSM is disabled, "integer mode") 71 * FOUTVCO = FREF / REFDIV * FBDIV 72 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 73 * Where: 74 * FOUTVCO = Fractional PLL non-divided output frequency 75 * FOUTPOSTDIV = Fractional PLL divided output frequency 76 * (output of second post divider) 77 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input) 78 * REFDIV = Fractional PLL input reference clock divider 79 * FBDIV = Integer value programmed into feedback divide 80 * 81 */ 82 83 static int rockchip_pll_clk_set_postdiv(ulong fout_hz, 84 u32 *postdiv1, 85 u32 *postdiv2, 86 u32 *foutvco) 87 { 88 ulong freq; 89 90 if (fout_hz < MIN_FOUTVCO_FREQ) { 91 for (*postdiv1 = 1; *postdiv1 <= 7; (*postdiv1)++) { 92 for (*postdiv2 = 1; *postdiv2 <= 7; (*postdiv2)++) { 93 freq = fout_hz * (*postdiv1) * (*postdiv2); 94 if (freq >= MIN_FOUTVCO_FREQ && 95 freq <= MAX_FOUTVCO_FREQ) { 96 *foutvco = freq; 97 return 0; 98 } 99 } 100 } 101 printf("Can't FIND postdiv1/2 to make fout=%lu in 800~2000M.\n", 102 fout_hz); 103 } else { 104 *postdiv1 = 1; 105 *postdiv2 = 1; 106 } 107 return 0; 108 } 109 110 static struct rockchip_pll_rate_table * 111 rockchip_pll_clk_set_by_auto(ulong fin_hz, 112 ulong fout_hz) 113 { 114 struct rockchip_pll_rate_table *rate_table = &rockchip_auto_table; 115 /* FIXME set postdiv1/2 always 1*/ 116 u32 foutvco = fout_hz; 117 ulong fin_64, frac_64; 118 u32 f_frac, postdiv1, postdiv2; 119 ulong clk_gcd = 0; 120 121 if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz) 122 return NULL; 123 124 rockchip_pll_clk_set_postdiv(fout_hz, &postdiv1, &postdiv2, &foutvco); 125 rate_table->postdiv1 = postdiv1; 126 rate_table->postdiv2 = postdiv2; 127 rate_table->dsmpd = 1; 128 129 if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MHZ == fout_hz) { 130 fin_hz /= MHZ; 131 foutvco /= MHZ; 132 clk_gcd = gcd(fin_hz, foutvco); 133 rate_table->refdiv = fin_hz / clk_gcd; 134 rate_table->fbdiv = foutvco / clk_gcd; 135 136 rate_table->frac = 0; 137 138 debug("fin = %ld, fout = %ld, clk_gcd = %ld,\n", 139 fin_hz, fout_hz, clk_gcd); 140 debug("refdiv= %d,fbdiv= %d,postdiv1= %d,postdiv2= %d\n", 141 rate_table->refdiv, 142 rate_table->fbdiv, rate_table->postdiv1, 143 rate_table->postdiv2); 144 } else { 145 debug("frac div,fin_hz = %ld,fout_hz = %ld\n", 146 fin_hz, fout_hz); 147 debug("frac get postdiv1 = %d, postdiv2 = %d, foutvco = %d\n", 148 rate_table->postdiv1, rate_table->postdiv2, foutvco); 149 clk_gcd = gcd(fin_hz / MHZ, foutvco / MHZ); 150 rate_table->refdiv = fin_hz / MHZ / clk_gcd; 151 rate_table->fbdiv = foutvco / MHZ / clk_gcd; 152 debug("frac get refdiv = %d, fbdiv = %d\n", 153 rate_table->refdiv, rate_table->fbdiv); 154 155 rate_table->frac = 0; 156 157 f_frac = (foutvco % MHZ); 158 fin_64 = fin_hz; 159 fin_64 = fin_64 / rate_table->refdiv; 160 frac_64 = f_frac << 24; 161 frac_64 = frac_64 / fin_64; 162 rate_table->frac = frac_64; 163 if (rate_table->frac > 0) 164 rate_table->dsmpd = 0; 165 debug("frac = %x\n", rate_table->frac); 166 } 167 return rate_table; 168 } 169 170 static struct rockchip_pll_rate_table * 171 rk3588_pll_clk_set_by_auto(unsigned long fin_hz, 172 unsigned long fout_hz) 173 { 174 struct rockchip_pll_rate_table *rate_table = &rockchip_auto_table; 175 u32 p, m, s; 176 ulong fvco, fref, fout, ffrac; 177 178 if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz) 179 return NULL; 180 181 if (fout_hz > RK3588_FOUT_MAX_HZ || fout_hz < RK3588_FOUT_MIN_HZ) 182 return NULL; 183 184 if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MHZ == fout_hz) { 185 for (s = 0; s <= 6; s++) { 186 fvco = fout_hz << s; 187 if (fvco < RK3588_VCO_MIN_HZ || 188 fvco > RK3588_VCO_MAX_HZ) 189 continue; 190 for (p = 2; p <= 4; p++) { 191 for (m = 64; m <= 1023; m++) { 192 if (fvco == m * fin_hz / p) { 193 rate_table->p = p; 194 rate_table->m = m; 195 rate_table->s = s; 196 rate_table->k = 0; 197 return rate_table; 198 } 199 } 200 } 201 } 202 pr_err("CANNOT FIND Fout by auto,fout = %lu\n", fout_hz); 203 } else { 204 fout = (fout_hz / MHZ) * MHZ; 205 ffrac = (fout_hz % MHZ); 206 for (s = 0; s <= 6; s++) { 207 fvco = fout << s; 208 if (fvco < RK3588_VCO_MIN_HZ || 209 fvco > RK3588_VCO_MAX_HZ) 210 continue; 211 for (p = 1; p <= 4; p++) { 212 for (m = 64; m <= 1023; m++) { 213 if (fvco == m * fin_hz / p) { 214 rate_table->p = p; 215 rate_table->m = m; 216 rate_table->s = s; 217 fref = fin_hz / p; 218 fout = (ffrac << s) * 65535; 219 rate_table->k = fout / fref; 220 return rate_table; 221 } 222 } 223 } 224 } 225 pr_err("CANNOT FIND Fout by auto,fout = %lu\n", fout_hz); 226 } 227 return NULL; 228 } 229 230 static const struct rockchip_pll_rate_table * 231 rockchip_get_pll_settings(struct rockchip_pll_clock *pll, ulong rate) 232 { 233 struct rockchip_pll_rate_table *rate_table = pll->rate_table; 234 235 while (rate_table->rate) { 236 if (rate_table->rate == rate) 237 break; 238 rate_table++; 239 } 240 if (rate_table->rate != rate) { 241 if (pll->type == pll_rk3588) 242 return rk3588_pll_clk_set_by_auto(24 * MHZ, rate); 243 else 244 return rockchip_pll_clk_set_by_auto(24 * MHZ, rate); 245 } else { 246 return rate_table; 247 } 248 } 249 250 static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll, 251 void __iomem *base, ulong pll_id, 252 ulong drate) 253 { 254 const struct rockchip_pll_rate_table *rate; 255 int timeout = 100; 256 257 rate = rockchip_get_pll_settings(pll, drate); 258 if (!rate) { 259 printf("%s unsupport rate\n", __func__); 260 return -EINVAL; 261 } 262 263 debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d\n", 264 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv); 265 debug("%s: rate settings for %lu postdiv2: %d, dsmpd: %d, frac: %d\n", 266 __func__, rate->rate, rate->postdiv2, rate->dsmpd, rate->frac); 267 268 /* 269 * When power on or changing PLL setting, 270 * we must force PLL into slow mode to ensure output stable clock. 271 */ 272 rk_clrsetreg(base + pll->mode_offset, 273 pll->mode_mask << pll->mode_shift, 274 RKCLK_PLL_MODE_SLOW << pll->mode_shift); 275 276 /* Power down */ 277 rk_setreg(base + pll->con_offset + 0x4, 278 1 << RK3036_PLLCON1_PWRDOWN_SHIT); 279 280 rk_clrsetreg(base + pll->con_offset, 281 (RK3036_PLLCON0_POSTDIV1_MASK | 282 RK3036_PLLCON0_FBDIV_MASK), 283 (rate->postdiv1 << RK3036_PLLCON0_POSTDIV1_SHIFT) | 284 rate->fbdiv); 285 rk_clrsetreg(base + pll->con_offset + 0x4, 286 (RK3036_PLLCON1_POSTDIV2_MASK | 287 RK3036_PLLCON1_REFDIV_MASK), 288 (rate->postdiv2 << RK3036_PLLCON1_POSTDIV2_SHIFT | 289 rate->refdiv << RK3036_PLLCON1_REFDIV_SHIFT)); 290 if (!rate->dsmpd) { 291 rk_clrsetreg(base + pll->con_offset + 0x4, 292 RK3036_PLLCON1_DSMPD_MASK, 293 rate->dsmpd << RK3036_PLLCON1_DSMPD_SHIFT); 294 writel((readl(base + pll->con_offset + 0x8) & 295 (~RK3036_PLLCON2_FRAC_MASK)) | 296 (rate->frac << RK3036_PLLCON2_FRAC_SHIFT), 297 base + pll->con_offset + 0x8); 298 } 299 300 /* Power Up */ 301 rk_clrreg(base + pll->con_offset + 0x4, 302 1 << RK3036_PLLCON1_PWRDOWN_SHIT); 303 304 /* waiting for pll lock */ 305 while ((timeout > 0) && !(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift))) { 306 udelay(1); 307 timeout--; 308 } 309 310 if (!(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift))) 311 printf("%s: wait pll lock timeout! pll_id=%ld\n", __func__, pll_id); 312 313 rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift, 314 RKCLK_PLL_MODE_NORMAL << pll->mode_shift); 315 debug("PLL at %p: con0=%x con1= %x con2= %x mode= %x\n", 316 pll, readl(base + pll->con_offset), 317 readl(base + pll->con_offset + 0x4), 318 readl(base + pll->con_offset + 0x8), 319 readl(base + pll->mode_offset)); 320 321 return 0; 322 } 323 324 static ulong rk3036_pll_get_rate(struct rockchip_pll_clock *pll, 325 void __iomem *base, ulong pll_id) 326 { 327 u32 refdiv, fbdiv, postdiv1, postdiv2, dsmpd, frac; 328 u32 con = 0, shift, mask; 329 ulong rate; 330 331 con = readl(base + pll->mode_offset); 332 shift = pll->mode_shift; 333 mask = pll->mode_mask << shift; 334 335 switch ((con & mask) >> shift) { 336 case RKCLK_PLL_MODE_SLOW: 337 return OSC_HZ; 338 case RKCLK_PLL_MODE_NORMAL: 339 /* normal mode */ 340 con = readl(base + pll->con_offset); 341 postdiv1 = (con & RK3036_PLLCON0_POSTDIV1_MASK) >> 342 RK3036_PLLCON0_POSTDIV1_SHIFT; 343 fbdiv = (con & RK3036_PLLCON0_FBDIV_MASK) >> 344 RK3036_PLLCON0_FBDIV_SHIFT; 345 con = readl(base + pll->con_offset + 0x4); 346 postdiv2 = (con & RK3036_PLLCON1_POSTDIV2_MASK) >> 347 RK3036_PLLCON1_POSTDIV2_SHIFT; 348 refdiv = (con & RK3036_PLLCON1_REFDIV_MASK) >> 349 RK3036_PLLCON1_REFDIV_SHIFT; 350 dsmpd = (con & RK3036_PLLCON1_DSMPD_MASK) >> 351 RK3036_PLLCON1_DSMPD_SHIFT; 352 con = readl(base + pll->con_offset + 0x8); 353 frac = (con & RK3036_PLLCON2_FRAC_MASK) >> 354 RK3036_PLLCON2_FRAC_SHIFT; 355 rate = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; 356 if (dsmpd == 0) { 357 u64 frac_rate = OSC_HZ * (u64)frac; 358 359 do_div(frac_rate, refdiv); 360 frac_rate >>= 24; 361 do_div(frac_rate, postdiv1); 362 do_div(frac_rate, postdiv1); 363 rate += frac_rate; 364 } 365 return rate; 366 case RKCLK_PLL_MODE_DEEP: 367 default: 368 return 32768; 369 } 370 } 371 372 #define RK3588_PLLCON(i) ((i) * 0x4) 373 #define RK3588_PLLCON0_M_MASK 0x3ff << 0 374 #define RK3588_PLLCON0_M_SHIFT 0 375 #define RK3588_PLLCON1_P_MASK 0x3f << 0 376 #define RK3588_PLLCON1_P_SHIFT 0 377 #define RK3588_PLLCON1_S_MASK 0x7 << 6 378 #define RK3588_PLLCON1_S_SHIFT 6 379 #define RK3588_PLLCON2_K_MASK 0xffff 380 #define RK3588_PLLCON2_K_SHIFT 0 381 #define RK3588_PLLCON1_PWRDOWN BIT(13) 382 #define RK3588_PLLCON6_LOCK_STATUS BIT(15) 383 #define RK3588_B0PLL_CLKSEL_CON(i) ((i) * 0x4 + 0x50000 + 0x300) 384 #define RK3588_B1PLL_CLKSEL_CON(i) ((i) * 0x4 + 0x52000 + 0x300) 385 #define RK3588_LPLL_CLKSEL_CON(i) ((i) * 0x4 + 0x58000 + 0x300) 386 #define RK3588_CORE_DIV_MASK 0x1f 387 #define RK3588_CORE_L02_DIV_SHIFT 0 388 #define RK3588_CORE_L13_DIV_SHIFT 7 389 #define RK3588_CORE_B02_DIV_SHIFT 8 390 #define RK3588_CORE_B13_DIV_SHIFT 0 391 392 static int rk3588_pll_set_rate(struct rockchip_pll_clock *pll, 393 void __iomem *base, ulong pll_id, 394 ulong drate) 395 { 396 const struct rockchip_pll_rate_table *rate; 397 398 rate = rockchip_get_pll_settings(pll, drate); 399 if (!rate) { 400 printf("%s unsupported rate\n", __func__); 401 return -EINVAL; 402 } 403 404 debug("%s: rate settings for %lu p: %d, m: %d, s: %d, k: %d\n", 405 __func__, rate->rate, rate->p, rate->m, rate->s, rate->k); 406 407 /* 408 * When power on or changing PLL setting, 409 * we must force PLL into slow mode to ensure output stable clock. 410 */ 411 if (pll_id == 3) 412 rk_clrsetreg(base + 0x84c, 0x1 << 1, 0x1 << 1); 413 414 rk_clrsetreg(base + pll->mode_offset, 415 pll->mode_mask << pll->mode_shift, 416 RKCLK_PLL_MODE_SLOW << pll->mode_shift); 417 if (pll_id == 0) 418 rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(0), 419 pll->mode_mask << 6, 420 RKCLK_PLL_MODE_SLOW << 6); 421 else if (pll_id == 1) 422 rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(0), 423 pll->mode_mask << 6, 424 RKCLK_PLL_MODE_SLOW << 6); 425 else if (pll_id == 2) 426 rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(5), 427 pll->mode_mask << 14, 428 RKCLK_PLL_MODE_SLOW << 14); 429 430 /* Power down */ 431 rk_setreg(base + pll->con_offset + RK3588_PLLCON(1), 432 RK3588_PLLCON1_PWRDOWN); 433 434 rk_clrsetreg(base + pll->con_offset, 435 RK3588_PLLCON0_M_MASK, 436 (rate->m << RK3588_PLLCON0_M_SHIFT)); 437 rk_clrsetreg(base + pll->con_offset + RK3588_PLLCON(1), 438 (RK3588_PLLCON1_P_MASK | 439 RK3588_PLLCON1_S_MASK), 440 (rate->p << RK3588_PLLCON1_P_SHIFT | 441 rate->s << RK3588_PLLCON1_S_SHIFT)); 442 if (!rate->k) { 443 rk_clrsetreg(base + pll->con_offset + RK3588_PLLCON(2), 444 RK3588_PLLCON2_K_MASK, 445 rate->k << RK3588_PLLCON2_K_SHIFT); 446 } 447 /* Power up */ 448 rk_clrreg(base + pll->con_offset + RK3588_PLLCON(1), 449 RK3588_PLLCON1_PWRDOWN); 450 451 /* waiting for pll lock */ 452 while (!(readl(base + pll->con_offset + RK3588_PLLCON(6)) & 453 RK3588_PLLCON6_LOCK_STATUS)) { 454 udelay(1); 455 debug("%s: wait pll lock, pll_id=%ld\n", __func__, pll_id); 456 } 457 458 rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift, 459 RKCLK_PLL_MODE_NORMAL << pll->mode_shift); 460 if (pll_id == 0) { 461 rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(0), 462 pll->mode_mask << 6, 463 2 << 6); 464 rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(0), 465 RK3588_CORE_DIV_MASK << RK3588_CORE_B02_DIV_SHIFT, 466 0 << RK3588_CORE_B02_DIV_SHIFT); 467 rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(1), 468 RK3588_CORE_DIV_MASK << RK3588_CORE_B13_DIV_SHIFT, 469 0 << RK3588_CORE_B13_DIV_SHIFT); 470 } else if (pll_id == 1) { 471 rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(0), 472 pll->mode_mask << 6, 473 2 << 6); 474 rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(0), 475 RK3588_CORE_DIV_MASK << RK3588_CORE_B02_DIV_SHIFT, 476 0 << RK3588_CORE_B02_DIV_SHIFT); 477 rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(1), 478 RK3588_CORE_DIV_MASK << RK3588_CORE_B13_DIV_SHIFT, 479 0 << RK3588_CORE_B13_DIV_SHIFT); 480 } else if (pll_id == 2) { 481 rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(5), 482 pll->mode_mask << 14, 483 2 << 14); 484 rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(6), 485 RK3588_CORE_DIV_MASK << RK3588_CORE_L13_DIV_SHIFT, 486 0 << RK3588_CORE_L13_DIV_SHIFT); 487 rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(6), 488 RK3588_CORE_DIV_MASK << RK3588_CORE_L02_DIV_SHIFT, 489 0 << RK3588_CORE_L02_DIV_SHIFT); 490 rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(7), 491 RK3588_CORE_DIV_MASK << RK3588_CORE_L13_DIV_SHIFT, 492 0 << RK3588_CORE_L13_DIV_SHIFT); 493 rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(7), 494 RK3588_CORE_DIV_MASK << RK3588_CORE_L02_DIV_SHIFT, 495 0 << RK3588_CORE_L02_DIV_SHIFT); 496 } 497 498 if (pll_id == 3) 499 rk_clrsetreg(base + 0x84c, 0x1 << 1, 0); 500 501 debug("PLL at %p: con0=%x con1= %x con2= %x mode= %x\n", 502 pll, readl(base + pll->con_offset), 503 readl(base + pll->con_offset + 0x4), 504 readl(base + pll->con_offset + 0x8), 505 readl(base + pll->mode_offset)); 506 507 return 0; 508 } 509 510 static ulong rk3588_pll_get_rate(struct rockchip_pll_clock *pll, 511 void __iomem *base, ulong pll_id) 512 { 513 u32 m, p, s, k; 514 u32 con = 0, shift, mode; 515 u64 rate, postdiv; 516 517 con = readl(base + pll->mode_offset); 518 shift = pll->mode_shift; 519 if (pll_id == 8) 520 mode = RKCLK_PLL_MODE_NORMAL; 521 else 522 mode = (con & (pll->mode_mask << shift)) >> shift; 523 switch (mode) { 524 case RKCLK_PLL_MODE_SLOW: 525 return OSC_HZ; 526 case RKCLK_PLL_MODE_NORMAL: 527 /* normal mode */ 528 con = readl(base + pll->con_offset); 529 m = (con & RK3588_PLLCON0_M_MASK) >> 530 RK3588_PLLCON0_M_SHIFT; 531 con = readl(base + pll->con_offset + RK3588_PLLCON(1)); 532 p = (con & RK3588_PLLCON1_P_MASK) >> 533 RK3036_PLLCON0_FBDIV_SHIFT; 534 s = (con & RK3588_PLLCON1_S_MASK) >> 535 RK3588_PLLCON1_S_SHIFT; 536 con = readl(base + pll->con_offset + RK3588_PLLCON(2)); 537 k = (con & RK3588_PLLCON2_K_MASK) >> 538 RK3588_PLLCON2_K_SHIFT; 539 540 rate = OSC_HZ / p; 541 rate *= m; 542 if (k) { 543 /* fractional mode */ 544 u64 frac_rate64 = OSC_HZ * k; 545 546 postdiv = p * 65535; 547 do_div(frac_rate64, postdiv); 548 rate += frac_rate64; 549 } 550 rate = rate >> s; 551 return rate; 552 case RKCLK_PLL_MODE_DEEP: 553 default: 554 return 32768; 555 } 556 } 557 558 ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll, 559 void __iomem *base, 560 ulong pll_id) 561 { 562 ulong rate = 0; 563 564 switch (pll->type) { 565 case pll_rk3036: 566 pll->mode_mask = PLL_MODE_MASK; 567 rate = rk3036_pll_get_rate(pll, base, pll_id); 568 break; 569 case pll_rk3328: 570 pll->mode_mask = PLL_RK3328_MODE_MASK; 571 rate = rk3036_pll_get_rate(pll, base, pll_id); 572 break; 573 case pll_rk3588: 574 pll->mode_mask = PLL_MODE_MASK; 575 rate = rk3588_pll_get_rate(pll, base, pll_id); 576 break; 577 default: 578 printf("%s: Unknown pll type for pll clk %ld\n", 579 __func__, pll_id); 580 } 581 return rate; 582 } 583 584 int rockchip_pll_set_rate(struct rockchip_pll_clock *pll, 585 void __iomem *base, ulong pll_id, 586 ulong drate) 587 { 588 int ret = 0; 589 590 if (rockchip_pll_get_rate(pll, base, pll_id) == drate) 591 return 0; 592 593 switch (pll->type) { 594 case pll_rk3036: 595 pll->mode_mask = PLL_MODE_MASK; 596 ret = rk3036_pll_set_rate(pll, base, pll_id, drate); 597 break; 598 case pll_rk3328: 599 pll->mode_mask = PLL_RK3328_MODE_MASK; 600 ret = rk3036_pll_set_rate(pll, base, pll_id, drate); 601 break; 602 case pll_rk3588: 603 pll->mode_mask = PLL_MODE_MASK; 604 ret = rk3588_pll_set_rate(pll, base, pll_id, drate); 605 break; 606 default: 607 printf("%s: Unknown pll type for pll clk %ld\n", 608 __func__, pll_id); 609 } 610 return ret; 611 } 612 613 const struct rockchip_cpu_rate_table * 614 rockchip_get_cpu_settings(struct rockchip_cpu_rate_table *cpu_table, 615 ulong rate) 616 { 617 struct rockchip_cpu_rate_table *ps = cpu_table; 618 619 while (ps->rate) { 620 if (ps->rate == rate) 621 break; 622 ps++; 623 } 624 if (ps->rate != rate) 625 return NULL; 626 else 627 return ps; 628 } 629 630