1 /* 2 * Reference to the ARM TF Project, 3 * plat/arm/common/arm_bl2_setup.c 4 * Portions copyright (c) 2013-2016, ARM Limited and Contributors. All rights 5 * reserved. 6 * Copyright (C) 2016 Rockchip Electronic Co.,Ltd 7 * Written by Kever Yang <kever.yang@rock-chips.com> 8 * 9 * SPDX-License-Identifier: BSD-3-Clause 10 */ 11 12 #include <common.h> 13 #include <atf_common.h> 14 #include <errno.h> 15 #include <spl.h> 16 17 static struct bl2_to_bl31_params_mem bl31_params_mem; 18 static struct bl31_params *bl2_to_bl31_params; 19 20 /** 21 * bl2_plat_get_bl31_params() - prepare params for bl31. 22 * 23 * This function assigns a pointer to the memory that the platform has kept 24 * aside to pass platform specific and trusted firmware related information 25 * to BL31. This memory is allocated by allocating memory to 26 * bl2_to_bl31_params_mem structure which is a superset of all the 27 * structure whose information is passed to BL31 28 * NOTE: This function should be called only once and should be done 29 * before generating params to BL31 30 * 31 * @return bl31 params structure pointer 32 */ 33 struct bl31_params *bl2_plat_get_bl31_params(void) 34 { 35 struct entry_point_info *bl33_ep_info; 36 37 /* 38 * Initialise the memory for all the arguments that needs to 39 * be passed to BL31 40 */ 41 memset(&bl31_params_mem, 0, sizeof(struct bl2_to_bl31_params_mem)); 42 43 /* Assign memory for TF related information */ 44 bl2_to_bl31_params = &bl31_params_mem.bl31_params; 45 SET_PARAM_HEAD(bl2_to_bl31_params, ATF_PARAM_BL31, ATF_VERSION_1, 0); 46 47 /* Fill BL31 related information */ 48 SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, 49 ATF_PARAM_IMAGE_BINARY, ATF_VERSION_1, 0); 50 51 /* Fill BL32 related information if it exists */ 52 bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info; 53 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, ATF_PARAM_EP, 54 ATF_VERSION_1, 0); 55 bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info; 56 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, 57 ATF_PARAM_IMAGE_BINARY, ATF_VERSION_1, 0); 58 #ifndef BL32_BASE 59 bl2_to_bl31_params->bl32_ep_info->pc = 0; 60 #endif /* BL32_BASE */ 61 62 /* Fill BL33 related information */ 63 bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info; 64 bl33_ep_info = &bl31_params_mem.bl33_ep_info; 65 SET_PARAM_HEAD(bl33_ep_info, ATF_PARAM_EP, ATF_VERSION_1, 66 ATF_EP_NON_SECURE); 67 68 /* BL33 expects to receive the primary CPU MPID (through x0) */ 69 bl33_ep_info->args.arg0 = 0xffff & read_mpidr(); 70 bl33_ep_info->pc = CONFIG_SYS_TEXT_BASE; 71 bl33_ep_info->spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, 72 DISABLE_ALL_EXECPTIONS); 73 74 bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info; 75 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, 76 ATF_PARAM_IMAGE_BINARY, ATF_VERSION_1, 0); 77 78 return bl2_to_bl31_params; 79 } 80 81 void raw_write_daif(unsigned int daif) 82 { 83 __asm__ __volatile__("msr DAIF, %0\n\t" : : "r" (daif) : "memory"); 84 } 85 86 void spl_bl31_entry(void *entry_addr) 87 { 88 struct bl31_params *bl31_params; 89 void (*entry)(struct bl31_params *params, void *plat_params) = NULL; 90 91 bl31_params = bl2_plat_get_bl31_params(); 92 entry = entry_addr; 93 94 raw_write_daif(SPSR_EXCEPTION_MASK); 95 dcache_disable(); 96 97 entry(bl31_params, NULL); 98 } 99