1 /* 2 * (C) Copyright 2016 3 * Vikas Manocha, <vikas.manocha@st.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <ram.h> 11 #include <spl.h> 12 #include <asm/io.h> 13 #include <asm/armv7m.h> 14 #include <asm/arch/stm32.h> 15 #include <asm/arch/gpio.h> 16 #include <asm/arch/fmc.h> 17 #include <dm/platform_data/serial_stm32x7.h> 18 #include <asm/arch/stm32_periph.h> 19 #include <asm/arch/stm32_defs.h> 20 #include <asm/arch/syscfg.h> 21 #include <asm/gpio.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 int get_memory_base_size(fdt_addr_t *mr_base, fdt_addr_t *mr_size) 26 { 27 int mr_node; 28 29 mr_node = fdt_path_offset(gd->fdt_blob, "/memory"); 30 if (mr_node < 0) 31 return mr_node; 32 *mr_base = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, mr_node, 33 "reg", 0, mr_size, false); 34 debug("mr_base = %lx, mr_size= %lx\n", *mr_base, *mr_size); 35 36 return 0; 37 } 38 int dram_init(void) 39 { 40 int rv; 41 fdt_addr_t mr_base, mr_size; 42 43 #ifndef CONFIG_SUPPORT_SPL 44 struct udevice *dev; 45 rv = uclass_get_device(UCLASS_RAM, 0, &dev); 46 if (rv) { 47 debug("DRAM init failed: %d\n", rv); 48 return rv; 49 } 50 51 #endif 52 rv = get_memory_base_size(&mr_base, &mr_size); 53 if (rv) 54 return rv; 55 gd->ram_size = mr_size; 56 gd->ram_top = mr_base; 57 58 return rv; 59 } 60 61 int dram_init_banksize(void) 62 { 63 fdt_addr_t mr_base, mr_size; 64 get_memory_base_size(&mr_base, &mr_size); 65 /* 66 * Fill in global info with description of SRAM configuration 67 */ 68 gd->bd->bi_dram[0].start = mr_base; 69 gd->bd->bi_dram[0].size = mr_size; 70 71 return 0; 72 } 73 74 #ifdef CONFIG_ETH_DESIGNWARE 75 static int stmmac_setup(void) 76 { 77 clock_setup(SYSCFG_CLOCK_CFG); 78 /* Set >RMII mode */ 79 STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL; 80 clock_setup(STMMAC_CLOCK_CFG); 81 82 return 0; 83 } 84 85 int board_early_init_f(void) 86 { 87 stmmac_setup(); 88 89 return 0; 90 } 91 #endif 92 93 #ifdef CONFIG_SPL_BUILD 94 int spl_dram_init(void) 95 { 96 struct udevice *dev; 97 int rv; 98 rv = uclass_get_device(UCLASS_RAM, 0, &dev); 99 if (rv) 100 debug("DRAM init failed: %d\n", rv); 101 return rv; 102 } 103 void spl_board_init(void) 104 { 105 spl_dram_init(); 106 preloader_console_init(); 107 arch_cpu_init(); /* to configure mpu for sdram rw permissions */ 108 } 109 u32 spl_boot_device(void) 110 { 111 return BOOT_DEVICE_NOR; 112 } 113 114 #endif 115 u32 get_board_rev(void) 116 { 117 return 0; 118 } 119 120 int board_late_init(void) 121 { 122 struct gpio_desc gpio = {}; 123 int node; 124 125 node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,led1"); 126 if (node < 0) 127 return -1; 128 129 gpio_request_by_name_nodev(offset_to_ofnode(node), "led-gpio", 0, &gpio, 130 GPIOD_IS_OUT); 131 132 if (dm_gpio_is_valid(&gpio)) { 133 dm_gpio_set_value(&gpio, 0); 134 mdelay(10); 135 dm_gpio_set_value(&gpio, 1); 136 } 137 138 /* read button 1*/ 139 node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,button1"); 140 if (node < 0) 141 return -1; 142 143 gpio_request_by_name_nodev(offset_to_ofnode(node), "button-gpio", 0, 144 &gpio, GPIOD_IS_IN); 145 146 if (dm_gpio_is_valid(&gpio)) { 147 if (dm_gpio_get_value(&gpio)) 148 puts("usr button is at HIGH LEVEL\n"); 149 else 150 puts("usr button is at LOW LEVEL\n"); 151 } 152 153 return 0; 154 } 155 156 int board_init(void) 157 { 158 gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; 159 return 0; 160 } 161