1 /* 2 * (C) Copyright 2016 3 * Vikas Manocha, <vikas.manocha@st.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <ram.h> 11 #include <asm/io.h> 12 #include <asm/armv7m.h> 13 #include <asm/arch/stm32.h> 14 #include <asm/arch/gpio.h> 15 #include <dm/platdata.h> 16 #include <dm/platform_data/serial_stm32x7.h> 17 #include <asm/arch/stm32_periph.h> 18 #include <asm/arch/stm32_defs.h> 19 #include <asm/arch/syscfg.h> 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 const struct stm32_gpio_ctl gpio_ctl_gpout = { 24 .mode = STM32_GPIO_MODE_OUT, 25 .otype = STM32_GPIO_OTYPE_PP, 26 .speed = STM32_GPIO_SPEED_50M, 27 .pupd = STM32_GPIO_PUPD_NO, 28 .af = STM32_GPIO_AF0 29 }; 30 31 static int fmc_setup_gpio(void) 32 { 33 clock_setup(GPIO_B_CLOCK_CFG); 34 clock_setup(GPIO_C_CLOCK_CFG); 35 clock_setup(GPIO_D_CLOCK_CFG); 36 clock_setup(GPIO_E_CLOCK_CFG); 37 clock_setup(GPIO_F_CLOCK_CFG); 38 clock_setup(GPIO_G_CLOCK_CFG); 39 clock_setup(GPIO_H_CLOCK_CFG); 40 41 return 0; 42 } 43 44 int dram_init(void) 45 { 46 struct udevice *dev; 47 struct ram_info ram; 48 int rv; 49 50 rv = fmc_setup_gpio(); 51 if (rv) 52 return rv; 53 54 clock_setup(FMC_CLOCK_CFG); 55 56 rv = uclass_get_device(UCLASS_RAM, 0, &dev); 57 if (rv) { 58 debug("DRAM init failed: %d\n", rv); 59 return rv; 60 } 61 rv = ram_get_info(dev, &ram); 62 if (rv) { 63 debug("Cannot get DRAM size: %d\n", rv); 64 return rv; 65 } 66 debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size); 67 gd->ram_size = ram.size; 68 69 /* 70 * Fill in global info with description of SRAM configuration 71 */ 72 gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE; 73 gd->bd->bi_dram[0].size = ram.size; 74 75 return rv; 76 } 77 78 int uart_setup_gpio(void) 79 { 80 clock_setup(GPIO_A_CLOCK_CFG); 81 clock_setup(GPIO_B_CLOCK_CFG); 82 return 0; 83 } 84 85 #ifdef CONFIG_ETH_DESIGNWARE 86 87 static int stmmac_setup(void) 88 { 89 clock_setup(SYSCFG_CLOCK_CFG); 90 /* Set >RMII mode */ 91 STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL; 92 93 clock_setup(GPIO_A_CLOCK_CFG); 94 clock_setup(GPIO_C_CLOCK_CFG); 95 clock_setup(GPIO_G_CLOCK_CFG); 96 clock_setup(STMMAC_CLOCK_CFG); 97 98 return 0; 99 } 100 #endif 101 102 #ifdef CONFIG_STM32_QSPI 103 104 static int qspi_setup(void) 105 { 106 clock_setup(GPIO_B_CLOCK_CFG); 107 clock_setup(GPIO_D_CLOCK_CFG); 108 clock_setup(GPIO_E_CLOCK_CFG); 109 return 0; 110 } 111 #endif 112 113 u32 get_board_rev(void) 114 { 115 return 0; 116 } 117 118 int board_early_init_f(void) 119 { 120 int res; 121 122 res = uart_setup_gpio(); 123 if (res) 124 return res; 125 126 #ifdef CONFIG_ETH_DESIGNWARE 127 res = stmmac_setup(); 128 if (res) 129 return res; 130 #endif 131 132 #ifdef CONFIG_STM32_QSPI 133 res = qspi_setup(); 134 if (res) 135 return res; 136 #endif 137 138 return 0; 139 } 140 141 int board_init(void) 142 { 143 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 144 145 return 0; 146 } 147