1 /* 2 * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com> 3 * 4 * Copyright 2007 Embedded Specialties, Inc. 5 * 6 * Copyright 2004, 2007 Freescale Semiconductor. 7 * 8 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 29 #include <common.h> 30 #include <pci.h> 31 #include <asm/processor.h> 32 #include <asm/immap_85xx.h> 33 #include <asm/fsl_pci.h> 34 #include <asm/fsl_ddr_sdram.h> 35 #include <spd_sdram.h> 36 #include <netdev.h> 37 #include <tsec.h> 38 #include <miiphy.h> 39 #include <libfdt.h> 40 #include <fdt_support.h> 41 42 DECLARE_GLOBAL_DATA_PTR; 43 44 void local_bus_init(void); 45 void sdram_init(void); 46 long int fixed_sdram (void); 47 48 int board_early_init_f (void) 49 { 50 return 0; 51 } 52 53 int checkboard (void) 54 { 55 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 56 volatile u_char *rev= (void *)CONFIG_SYS_BD_REV; 57 58 printf ("Board: Wind River SBC8548 Rev. 0x%01x\n", 59 (*rev) >> 4); 60 61 /* 62 * Initialize local bus. 63 */ 64 local_bus_init (); 65 66 ecm->eedr = 0xffffffff; /* clear ecm errors */ 67 ecm->eeer = 0xffffffff; /* enable ecm errors */ 68 return 0; 69 } 70 71 phys_size_t 72 initdram(int board_type) 73 { 74 long dram_size = 0; 75 76 puts("Initializing\n"); 77 78 #if defined(CONFIG_DDR_DLL) 79 { 80 /* 81 * Work around to stabilize DDR DLL MSYNC_IN. 82 * Errata DDR9 seems to have been fixed. 83 * This is now the workaround for Errata DDR11: 84 * Override DLL = 1, Course Adj = 1, Tap Select = 0 85 */ 86 87 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 88 89 gur->ddrdllcr = 0x81000000; 90 asm("sync;isync;msync"); 91 udelay(200); 92 } 93 #endif 94 95 #if defined(CONFIG_SPD_EEPROM) 96 dram_size = fsl_ddr_sdram(); 97 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 98 dram_size *= 0x100000; 99 #else 100 dram_size = fixed_sdram (); 101 #endif 102 103 /* 104 * SDRAM Initialization 105 */ 106 sdram_init(); 107 108 puts(" DDR: "); 109 return dram_size; 110 } 111 112 /* 113 * Initialize Local Bus 114 */ 115 void 116 local_bus_init(void) 117 { 118 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 119 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); 120 121 uint clkdiv; 122 uint lbc_hz; 123 sys_info_t sysinfo; 124 125 get_sys_info(&sysinfo); 126 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; 127 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; 128 129 gur->lbiuiplldcr1 = 0x00078080; 130 if (clkdiv == 16) { 131 gur->lbiuiplldcr0 = 0x7c0f1bf0; 132 } else if (clkdiv == 8) { 133 gur->lbiuiplldcr0 = 0x6c0f1bf0; 134 } else if (clkdiv == 4) { 135 gur->lbiuiplldcr0 = 0x5c0f1bf0; 136 } 137 138 lbc->lcrr |= 0x00030000; 139 140 asm("sync;isync;msync"); 141 142 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ 143 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ 144 } 145 146 /* 147 * Initialize SDRAM memory on the Local Bus. 148 */ 149 void 150 sdram_init(void) 151 { 152 #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM) 153 154 uint idx; 155 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); 156 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; 157 uint lsdmr_common; 158 159 puts(" SDRAM: "); 160 161 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); 162 163 /* 164 * Setup SDRAM Base and Option Registers 165 */ 166 lbc->or3 = CONFIG_SYS_OR3_PRELIM; 167 asm("msync"); 168 169 lbc->br3 = CONFIG_SYS_BR3_PRELIM; 170 asm("msync"); 171 172 lbc->lbcr = CONFIG_SYS_LBC_LBCR; 173 asm("msync"); 174 175 176 lbc->lsrt = CONFIG_SYS_LBC_LSRT; 177 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; 178 asm("msync"); 179 180 /* 181 * MPC8548 uses "new" 15-16 style addressing. 182 */ 183 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; 184 lsdmr_common |= LSDMR_BSMA1516; 185 186 /* 187 * Issue PRECHARGE ALL command. 188 */ 189 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; 190 asm("sync;msync"); 191 *sdram_addr = 0xff; 192 ppcDcbf((unsigned long) sdram_addr); 193 udelay(100); 194 195 /* 196 * Issue 8 AUTO REFRESH commands. 197 */ 198 for (idx = 0; idx < 8; idx++) { 199 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; 200 asm("sync;msync"); 201 *sdram_addr = 0xff; 202 ppcDcbf((unsigned long) sdram_addr); 203 udelay(100); 204 } 205 206 /* 207 * Issue 8 MODE-set command. 208 */ 209 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; 210 asm("sync;msync"); 211 *sdram_addr = 0xff; 212 ppcDcbf((unsigned long) sdram_addr); 213 udelay(100); 214 215 /* 216 * Issue NORMAL OP command. 217 */ 218 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; 219 asm("sync;msync"); 220 *sdram_addr = 0xff; 221 ppcDcbf((unsigned long) sdram_addr); 222 udelay(200); /* Overkill. Must wait > 200 bus cycles */ 223 224 #endif /* enable SDRAM init */ 225 } 226 227 #if defined(CONFIG_SYS_DRAM_TEST) 228 int 229 testdram(void) 230 { 231 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; 232 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; 233 uint *p; 234 235 printf("Testing DRAM from 0x%08x to 0x%08x\n", 236 CONFIG_SYS_MEMTEST_START, 237 CONFIG_SYS_MEMTEST_END); 238 239 printf("DRAM test phase 1:\n"); 240 for (p = pstart; p < pend; p++) 241 *p = 0xaaaaaaaa; 242 243 for (p = pstart; p < pend; p++) { 244 if (*p != 0xaaaaaaaa) { 245 printf ("DRAM test fails at: %08x\n", (uint) p); 246 return 1; 247 } 248 } 249 250 printf("DRAM test phase 2:\n"); 251 for (p = pstart; p < pend; p++) 252 *p = 0x55555555; 253 254 for (p = pstart; p < pend; p++) { 255 if (*p != 0x55555555) { 256 printf ("DRAM test fails at: %08x\n", (uint) p); 257 return 1; 258 } 259 } 260 261 printf("DRAM test passed.\n"); 262 return 0; 263 } 264 #endif 265 266 #if !defined(CONFIG_SPD_EEPROM) 267 /************************************************************************* 268 * fixed_sdram init -- doesn't use serial presence detect. 269 * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed. 270 ************************************************************************/ 271 long int fixed_sdram (void) 272 { 273 #define CONFIG_SYS_DDR_CONTROL 0xc300c000 274 275 volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); 276 277 ddr->cs0_bnds = 0x0000007f; 278 ddr->cs1_bnds = 0x008000ff; 279 ddr->cs2_bnds = 0x00000000; 280 ddr->cs3_bnds = 0x00000000; 281 ddr->cs0_config = 0x80010101; 282 ddr->cs1_config = 0x80010101; 283 ddr->cs2_config = 0x00000000; 284 ddr->cs3_config = 0x00000000; 285 ddr->timing_cfg_3 = 0x00000000; 286 ddr->timing_cfg_0 = 0x00220802; 287 ddr->timing_cfg_1 = 0x38377322; 288 ddr->timing_cfg_2 = 0x0fa044C7; 289 ddr->sdram_cfg = 0x4300C000; 290 ddr->sdram_cfg_2 = 0x24401000; 291 ddr->sdram_mode = 0x23C00542; 292 ddr->sdram_mode_2 = 0x00000000; 293 ddr->sdram_interval = 0x05080100; 294 ddr->sdram_md_cntl = 0x00000000; 295 ddr->sdram_data_init = 0x00000000; 296 ddr->sdram_clk_cntl = 0x03800000; 297 asm("sync;isync;msync"); 298 udelay(500); 299 300 #if defined (CONFIG_DDR_ECC) 301 /* Enable ECC checking */ 302 ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); 303 #else 304 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 305 #endif 306 307 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 308 } 309 #endif 310 311 #ifdef CONFIG_PCI1 312 static struct pci_controller pci1_hose; 313 #endif /* CONFIG_PCI1 */ 314 315 #ifdef CONFIG_PCIE1 316 static struct pci_controller pcie1_hose; 317 #endif /* CONFIG_PCIE1 */ 318 319 int first_free_busno=0; 320 321 void 322 pci_init_board(void) 323 { 324 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 325 326 #ifdef CONFIG_PCI1 327 { 328 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; 329 struct pci_controller *hose = &pci1_hose; 330 struct pci_region *r = hose->regions; 331 332 uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ 333 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ 334 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ 335 336 uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */ 337 338 if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { 339 printf (" PCI host: %d bit, %s MHz, %s, %s\n", 340 (pci_32) ? 32 : 64, 341 (pci_speed == 33000000) ? "33" : 342 (pci_speed == 66000000) ? "66" : "unknown", 343 pci_clk_sel ? "sync" : "async", 344 pci_arb ? "arbiter" : "external-arbiter" 345 ); 346 347 /* outbound memory */ 348 pci_set_region(r++, 349 CONFIG_SYS_PCI1_MEM_BASE, 350 CONFIG_SYS_PCI1_MEM_PHYS, 351 CONFIG_SYS_PCI1_MEM_SIZE, 352 PCI_REGION_MEM); 353 354 /* outbound io */ 355 pci_set_region(r++, 356 CONFIG_SYS_PCI1_IO_BASE, 357 CONFIG_SYS_PCI1_IO_PHYS, 358 CONFIG_SYS_PCI1_IO_SIZE, 359 PCI_REGION_IO); 360 hose->region_count = r - hose->regions; 361 362 hose->first_busno=first_free_busno; 363 364 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 365 first_free_busno=hose->last_busno+1; 366 printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); 367 #ifdef CONFIG_PCIX_CHECK 368 if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) { 369 /* PCI-X init */ 370 if (CONFIG_SYS_CLK_FREQ < 66000000) 371 printf("PCI-X will only work at 66 MHz\n"); 372 373 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ 374 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; 375 pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16); 376 } 377 #endif 378 } else { 379 printf (" PCI: disabled\n"); 380 } 381 } 382 #else 383 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ 384 #endif 385 386 gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable PCI2 */ 387 388 #ifdef CONFIG_PCIE1 389 { 390 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; 391 struct pci_controller *hose = &pcie1_hose; 392 struct pci_region *r = hose->regions; 393 394 int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); 395 396 if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ 397 printf ("\n PCIE at base address %x", 398 (uint)pci); 399 400 if (pci->pme_msg_det) { 401 pci->pme_msg_det = 0xffffffff; 402 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 403 } 404 printf ("\n"); 405 406 /* outbound memory */ 407 pci_set_region(r++, 408 CONFIG_SYS_PCIE1_MEM_BASE, 409 CONFIG_SYS_PCIE1_MEM_PHYS, 410 CONFIG_SYS_PCIE1_MEM_SIZE, 411 PCI_REGION_MEM); 412 413 /* outbound io */ 414 pci_set_region(r++, 415 CONFIG_SYS_PCIE1_IO_BASE, 416 CONFIG_SYS_PCIE1_IO_PHYS, 417 CONFIG_SYS_PCIE1_IO_SIZE, 418 PCI_REGION_IO); 419 420 hose->region_count = r - hose->regions; 421 422 hose->first_busno=first_free_busno; 423 424 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 425 printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno); 426 427 first_free_busno=hose->last_busno+1; 428 429 } else { 430 printf (" PCIE: disabled\n"); 431 } 432 } 433 #else 434 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 435 #endif 436 437 } 438 439 int board_eth_init(bd_t *bis) 440 { 441 tsec_standard_init(bis); 442 pci_eth_init(bis); 443 return 0; /* otherwise cpu_eth_init gets run */ 444 } 445 446 int last_stage_init(void) 447 { 448 return 0; 449 } 450 451 #if defined(CONFIG_OF_BOARD_SETUP) 452 void ft_board_setup(void *blob, bd_t *bd) 453 { 454 ft_cpu_setup(blob, bd); 455 #ifdef CONFIG_PCI1 456 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); 457 #endif 458 #ifdef CONFIG_PCIE1 459 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); 460 #endif 461 } 462 #endif 463