1 /* 2 * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com> 3 * 4 * Copyright 2007 Embedded Specialties, Inc. 5 * 6 * Copyright 2004, 2007 Freescale Semiconductor. 7 * 8 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 29 #include <common.h> 30 #include <pci.h> 31 #include <asm/processor.h> 32 #include <asm/immap_85xx.h> 33 #include <asm/fsl_pci.h> 34 #include <asm/fsl_ddr_sdram.h> 35 #include <spd_sdram.h> 36 #include <netdev.h> 37 #include <tsec.h> 38 #include <miiphy.h> 39 #include <libfdt.h> 40 #include <fdt_support.h> 41 42 DECLARE_GLOBAL_DATA_PTR; 43 44 void local_bus_init(void); 45 void sdram_init(void); 46 long int fixed_sdram (void); 47 48 int board_early_init_f (void) 49 { 50 return 0; 51 } 52 53 int checkboard (void) 54 { 55 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 56 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 57 volatile u_char *rev= (void *)CONFIG_SYS_BD_REV; 58 59 printf ("Board: Wind River SBC8548 Rev. 0x%01x\n", 60 (*rev) >> 4); 61 62 /* 63 * Initialize local bus. 64 */ 65 local_bus_init (); 66 67 /* 68 * Hack TSEC 3 and 4 IO voltages. 69 */ 70 gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ 71 72 ecm->eedr = 0xffffffff; /* clear ecm errors */ 73 ecm->eeer = 0xffffffff; /* enable ecm errors */ 74 return 0; 75 } 76 77 phys_size_t 78 initdram(int board_type) 79 { 80 long dram_size = 0; 81 82 puts("Initializing\n"); 83 84 #if defined(CONFIG_DDR_DLL) 85 { 86 /* 87 * Work around to stabilize DDR DLL MSYNC_IN. 88 * Errata DDR9 seems to have been fixed. 89 * This is now the workaround for Errata DDR11: 90 * Override DLL = 1, Course Adj = 1, Tap Select = 0 91 */ 92 93 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 94 95 gur->ddrdllcr = 0x81000000; 96 asm("sync;isync;msync"); 97 udelay(200); 98 } 99 #endif 100 101 #if defined(CONFIG_SPD_EEPROM) 102 dram_size = fsl_ddr_sdram(); 103 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 104 dram_size *= 0x100000; 105 #else 106 dram_size = fixed_sdram (); 107 #endif 108 109 /* 110 * SDRAM Initialization 111 */ 112 sdram_init(); 113 114 puts(" DDR: "); 115 return dram_size; 116 } 117 118 /* 119 * Initialize Local Bus 120 */ 121 void 122 local_bus_init(void) 123 { 124 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 125 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); 126 127 uint clkdiv; 128 uint lbc_hz; 129 sys_info_t sysinfo; 130 131 get_sys_info(&sysinfo); 132 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; 133 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; 134 135 gur->lbiuiplldcr1 = 0x00078080; 136 if (clkdiv == 16) { 137 gur->lbiuiplldcr0 = 0x7c0f1bf0; 138 } else if (clkdiv == 8) { 139 gur->lbiuiplldcr0 = 0x6c0f1bf0; 140 } else if (clkdiv == 4) { 141 gur->lbiuiplldcr0 = 0x5c0f1bf0; 142 } 143 144 lbc->lcrr |= 0x00030000; 145 146 asm("sync;isync;msync"); 147 148 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ 149 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ 150 } 151 152 /* 153 * Initialize SDRAM memory on the Local Bus. 154 */ 155 void 156 sdram_init(void) 157 { 158 #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM) 159 160 uint idx; 161 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); 162 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; 163 uint lsdmr_common; 164 165 puts(" SDRAM: "); 166 167 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); 168 169 /* 170 * Setup SDRAM Base and Option Registers 171 */ 172 lbc->or3 = CONFIG_SYS_OR3_PRELIM; 173 asm("msync"); 174 175 lbc->br3 = CONFIG_SYS_BR3_PRELIM; 176 asm("msync"); 177 178 lbc->lbcr = CONFIG_SYS_LBC_LBCR; 179 asm("msync"); 180 181 182 lbc->lsrt = CONFIG_SYS_LBC_LSRT; 183 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; 184 asm("msync"); 185 186 /* 187 * MPC8548 uses "new" 15-16 style addressing. 188 */ 189 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; 190 lsdmr_common |= LSDMR_BSMA1516; 191 192 /* 193 * Issue PRECHARGE ALL command. 194 */ 195 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; 196 asm("sync;msync"); 197 *sdram_addr = 0xff; 198 ppcDcbf((unsigned long) sdram_addr); 199 udelay(100); 200 201 /* 202 * Issue 8 AUTO REFRESH commands. 203 */ 204 for (idx = 0; idx < 8; idx++) { 205 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; 206 asm("sync;msync"); 207 *sdram_addr = 0xff; 208 ppcDcbf((unsigned long) sdram_addr); 209 udelay(100); 210 } 211 212 /* 213 * Issue 8 MODE-set command. 214 */ 215 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; 216 asm("sync;msync"); 217 *sdram_addr = 0xff; 218 ppcDcbf((unsigned long) sdram_addr); 219 udelay(100); 220 221 /* 222 * Issue NORMAL OP command. 223 */ 224 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; 225 asm("sync;msync"); 226 *sdram_addr = 0xff; 227 ppcDcbf((unsigned long) sdram_addr); 228 udelay(200); /* Overkill. Must wait > 200 bus cycles */ 229 230 #endif /* enable SDRAM init */ 231 } 232 233 #if defined(CONFIG_SYS_DRAM_TEST) 234 int 235 testdram(void) 236 { 237 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; 238 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; 239 uint *p; 240 241 printf("Testing DRAM from 0x%08x to 0x%08x\n", 242 CONFIG_SYS_MEMTEST_START, 243 CONFIG_SYS_MEMTEST_END); 244 245 printf("DRAM test phase 1:\n"); 246 for (p = pstart; p < pend; p++) 247 *p = 0xaaaaaaaa; 248 249 for (p = pstart; p < pend; p++) { 250 if (*p != 0xaaaaaaaa) { 251 printf ("DRAM test fails at: %08x\n", (uint) p); 252 return 1; 253 } 254 } 255 256 printf("DRAM test phase 2:\n"); 257 for (p = pstart; p < pend; p++) 258 *p = 0x55555555; 259 260 for (p = pstart; p < pend; p++) { 261 if (*p != 0x55555555) { 262 printf ("DRAM test fails at: %08x\n", (uint) p); 263 return 1; 264 } 265 } 266 267 printf("DRAM test passed.\n"); 268 return 0; 269 } 270 #endif 271 272 #if !defined(CONFIG_SPD_EEPROM) 273 /************************************************************************* 274 * fixed_sdram init -- doesn't use serial presence detect. 275 * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed. 276 ************************************************************************/ 277 long int fixed_sdram (void) 278 { 279 #define CONFIG_SYS_DDR_CONTROL 0xc300c000 280 281 volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); 282 283 ddr->cs0_bnds = 0x0000007f; 284 ddr->cs1_bnds = 0x008000ff; 285 ddr->cs2_bnds = 0x00000000; 286 ddr->cs3_bnds = 0x00000000; 287 ddr->cs0_config = 0x80010101; 288 ddr->cs1_config = 0x80010101; 289 ddr->cs2_config = 0x00000000; 290 ddr->cs3_config = 0x00000000; 291 ddr->timing_cfg_3 = 0x00000000; 292 ddr->timing_cfg_0 = 0x00220802; 293 ddr->timing_cfg_1 = 0x38377322; 294 ddr->timing_cfg_2 = 0x0fa044C7; 295 ddr->sdram_cfg = 0x4300C000; 296 ddr->sdram_cfg_2 = 0x24401000; 297 ddr->sdram_mode = 0x23C00542; 298 ddr->sdram_mode_2 = 0x00000000; 299 ddr->sdram_interval = 0x05080100; 300 ddr->sdram_md_cntl = 0x00000000; 301 ddr->sdram_data_init = 0x00000000; 302 ddr->sdram_clk_cntl = 0x03800000; 303 asm("sync;isync;msync"); 304 udelay(500); 305 306 #if defined (CONFIG_DDR_ECC) 307 /* Enable ECC checking */ 308 ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); 309 #else 310 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 311 #endif 312 313 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 314 } 315 #endif 316 317 #if defined(CONFIG_PCI) || defined(CONFIG_PCI1) 318 /* For some reason the Tundra PCI bridge shows up on itself as a 319 * different device. Work around that by refusing to configure it. 320 */ 321 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } 322 323 static struct pci_config_table pci_sbc8548_config_table[] = { 324 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, 325 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, 326 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, 327 mpc85xx_config_via_usbide, {0,0,0}}, 328 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, 329 mpc85xx_config_via_usb, {0,0,0}}, 330 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, 331 mpc85xx_config_via_usb2, {0,0,0}}, 332 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, 333 mpc85xx_config_via_power, {0,0,0}}, 334 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, 335 mpc85xx_config_via_ac97, {0,0,0}}, 336 {}, 337 }; 338 339 static struct pci_controller pci1_hose = { 340 config_table: pci_sbc8548_config_table}; 341 #endif /* CONFIG_PCI */ 342 343 #ifdef CONFIG_PCI2 344 static struct pci_controller pci2_hose; 345 #endif /* CONFIG_PCI2 */ 346 347 #ifdef CONFIG_PCIE1 348 static struct pci_controller pcie1_hose; 349 #endif /* CONFIG_PCIE1 */ 350 351 int first_free_busno=0; 352 353 void 354 pci_init_board(void) 355 { 356 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 357 358 #ifdef CONFIG_PCI1 359 { 360 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; 361 struct pci_controller *hose = &pci1_hose; 362 struct pci_config_table *table; 363 struct pci_region *r = hose->regions; 364 365 uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ 366 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ 367 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ 368 369 uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent); 370 371 uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ 372 373 if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { 374 printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", 375 (pci_32) ? 32 : 64, 376 (pci_speed == 33333000) ? "33" : 377 (pci_speed == 66666000) ? "66" : "unknown", 378 pci_clk_sel ? "sync" : "async", 379 pci_agent ? "agent" : "host", 380 pci_arb ? "arbiter" : "external-arbiter" 381 ); 382 383 /* outbound memory */ 384 pci_set_region(r++, 385 CONFIG_SYS_PCI1_MEM_BASE, 386 CONFIG_SYS_PCI1_MEM_PHYS, 387 CONFIG_SYS_PCI1_MEM_SIZE, 388 PCI_REGION_MEM); 389 390 /* outbound io */ 391 pci_set_region(r++, 392 CONFIG_SYS_PCI1_IO_BASE, 393 CONFIG_SYS_PCI1_IO_PHYS, 394 CONFIG_SYS_PCI1_IO_SIZE, 395 PCI_REGION_IO); 396 hose->region_count = r - hose->regions; 397 398 /* relocate config table pointers */ 399 hose->config_table = \ 400 (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off); 401 for (table = hose->config_table; table && table->vendor; table++) 402 table->config_device += gd->reloc_off; 403 404 hose->first_busno=first_free_busno; 405 406 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 407 first_free_busno=hose->last_busno+1; 408 printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); 409 #ifdef CONFIG_PCIX_CHECK 410 if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) { 411 /* PCI-X init */ 412 if (CONFIG_SYS_CLK_FREQ < 66000000) 413 printf("PCI-X will only work at 66 MHz\n"); 414 415 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ 416 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; 417 pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16); 418 } 419 #endif 420 } else { 421 printf (" PCI: disabled\n"); 422 } 423 } 424 #else 425 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ 426 #endif 427 428 #ifdef CONFIG_PCI2 429 { 430 uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ 431 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ 432 if (pci_dual) { 433 printf (" PCI2: 32 bit, 66 MHz, %s\n", 434 pci2_clk_sel ? "sync" : "async"); 435 } else { 436 printf (" PCI2: disabled\n"); 437 } 438 } 439 #else 440 gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */ 441 #endif /* CONFIG_PCI2 */ 442 443 #ifdef CONFIG_PCIE1 444 { 445 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; 446 struct pci_controller *hose = &pcie1_hose; 447 int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); 448 struct pci_region *r = hose->regions; 449 450 int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); 451 452 if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ 453 printf ("\n PCIE connected to slot as %s (base address %x)", 454 pcie_ep ? "End Point" : "Root Complex", 455 (uint)pci); 456 457 if (pci->pme_msg_det) { 458 pci->pme_msg_det = 0xffffffff; 459 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 460 } 461 printf ("\n"); 462 463 /* outbound memory */ 464 pci_set_region(r++, 465 CONFIG_SYS_PCIE1_MEM_BASE, 466 CONFIG_SYS_PCIE1_MEM_PHYS, 467 CONFIG_SYS_PCIE1_MEM_SIZE, 468 PCI_REGION_MEM); 469 470 /* outbound io */ 471 pci_set_region(r++, 472 CONFIG_SYS_PCIE1_IO_BASE, 473 CONFIG_SYS_PCIE1_IO_PHYS, 474 CONFIG_SYS_PCIE1_IO_SIZE, 475 PCI_REGION_IO); 476 477 hose->region_count = r - hose->regions; 478 479 hose->first_busno=first_free_busno; 480 481 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 482 printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno); 483 484 first_free_busno=hose->last_busno+1; 485 486 } else { 487 printf (" PCIE: disabled\n"); 488 } 489 } 490 #else 491 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 492 #endif 493 494 } 495 496 int board_eth_init(bd_t *bis) 497 { 498 tsec_standard_init(bis); 499 pci_eth_init(bis); 500 return 0; /* otherwise cpu_eth_init gets run */ 501 } 502 503 int last_stage_init(void) 504 { 505 return 0; 506 } 507 508 #if defined(CONFIG_OF_BOARD_SETUP) 509 void ft_board_setup(void *blob, bd_t *bd) 510 { 511 ft_cpu_setup(blob, bd); 512 #ifdef CONFIG_PCI1 513 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); 514 #endif 515 #ifdef CONFIG_PCIE1 516 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); 517 #endif 518 } 519 #endif 520