1 /* 2 * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com> 3 * Copyright 2007 Embedded Specialties, Inc. 4 * 5 * Copyright 2004, 2007 Freescale Semiconductor. 6 * 7 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <common.h> 29 #include <pci.h> 30 #include <asm/processor.h> 31 #include <asm/immap_85xx.h> 32 #include <asm/immap_fsl_pci.h> 33 #include <asm/fsl_ddr_sdram.h> 34 #include <spd_sdram.h> 35 #include <miiphy.h> 36 #include <libfdt.h> 37 #include <fdt_support.h> 38 39 DECLARE_GLOBAL_DATA_PTR; 40 41 void local_bus_init(void); 42 void sdram_init(void); 43 long int fixed_sdram (void); 44 45 int board_early_init_f (void) 46 { 47 return 0; 48 } 49 50 int checkboard (void) 51 { 52 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 53 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 54 volatile u_char *rev= (void *)CONFIG_SYS_BD_REV; 55 56 printf ("Board: Wind River SBC8548 Rev. 0x%01x\n", 57 (*rev) >> 4); 58 59 /* 60 * Initialize local bus. 61 */ 62 local_bus_init (); 63 64 /* 65 * Fix CPU2 errata: A core hang possible while executing a 66 * msync instruction and a snoopable transaction from an I/O 67 * master tagged to make quick forward progress is present. 68 */ 69 ecm->eebpcr |= (1 << 16); 70 71 /* 72 * Hack TSEC 3 and 4 IO voltages. 73 */ 74 gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ 75 76 ecm->eedr = 0xffffffff; /* clear ecm errors */ 77 ecm->eeer = 0xffffffff; /* enable ecm errors */ 78 return 0; 79 } 80 81 phys_size_t 82 initdram(int board_type) 83 { 84 long dram_size = 0; 85 86 puts("Initializing\n"); 87 88 #if defined(CONFIG_DDR_DLL) 89 { 90 /* 91 * Work around to stabilize DDR DLL MSYNC_IN. 92 * Errata DDR9 seems to have been fixed. 93 * This is now the workaround for Errata DDR11: 94 * Override DLL = 1, Course Adj = 1, Tap Select = 0 95 */ 96 97 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 98 99 gur->ddrdllcr = 0x81000000; 100 asm("sync;isync;msync"); 101 udelay(200); 102 } 103 #endif 104 105 #if defined(CONFIG_SPD_EEPROM) 106 dram_size = fsl_ddr_sdram(); 107 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 108 dram_size *= 0x100000; 109 #else 110 dram_size = fixed_sdram (); 111 #endif 112 113 /* 114 * SDRAM Initialization 115 */ 116 sdram_init(); 117 118 puts(" DDR: "); 119 return dram_size; 120 } 121 122 /* 123 * Initialize Local Bus 124 */ 125 void 126 local_bus_init(void) 127 { 128 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 129 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); 130 131 uint clkdiv; 132 uint lbc_hz; 133 sys_info_t sysinfo; 134 135 get_sys_info(&sysinfo); 136 clkdiv = (lbc->lcrr & 0x0f) * 2; 137 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; 138 139 gur->lbiuiplldcr1 = 0x00078080; 140 if (clkdiv == 16) { 141 gur->lbiuiplldcr0 = 0x7c0f1bf0; 142 } else if (clkdiv == 8) { 143 gur->lbiuiplldcr0 = 0x6c0f1bf0; 144 } else if (clkdiv == 4) { 145 gur->lbiuiplldcr0 = 0x5c0f1bf0; 146 } 147 148 lbc->lcrr |= 0x00030000; 149 150 asm("sync;isync;msync"); 151 152 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ 153 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ 154 } 155 156 /* 157 * Initialize SDRAM memory on the Local Bus. 158 */ 159 void 160 sdram_init(void) 161 { 162 #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM) 163 164 uint idx; 165 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); 166 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; 167 uint lsdmr_common; 168 169 puts(" SDRAM: "); 170 171 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); 172 173 /* 174 * Setup SDRAM Base and Option Registers 175 */ 176 lbc->or3 = CONFIG_SYS_OR3_PRELIM; 177 asm("msync"); 178 179 lbc->br3 = CONFIG_SYS_BR3_PRELIM; 180 asm("msync"); 181 182 lbc->lbcr = CONFIG_SYS_LBC_LBCR; 183 asm("msync"); 184 185 186 lbc->lsrt = CONFIG_SYS_LBC_LSRT; 187 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; 188 asm("msync"); 189 190 /* 191 * MPC8548 uses "new" 15-16 style addressing. 192 */ 193 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; 194 lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516; 195 196 /* 197 * Issue PRECHARGE ALL command. 198 */ 199 lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL; 200 asm("sync;msync"); 201 *sdram_addr = 0xff; 202 ppcDcbf((unsigned long) sdram_addr); 203 udelay(100); 204 205 /* 206 * Issue 8 AUTO REFRESH commands. 207 */ 208 for (idx = 0; idx < 8; idx++) { 209 lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH; 210 asm("sync;msync"); 211 *sdram_addr = 0xff; 212 ppcDcbf((unsigned long) sdram_addr); 213 udelay(100); 214 } 215 216 /* 217 * Issue 8 MODE-set command. 218 */ 219 lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW; 220 asm("sync;msync"); 221 *sdram_addr = 0xff; 222 ppcDcbf((unsigned long) sdram_addr); 223 udelay(100); 224 225 /* 226 * Issue NORMAL OP command. 227 */ 228 lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL; 229 asm("sync;msync"); 230 *sdram_addr = 0xff; 231 ppcDcbf((unsigned long) sdram_addr); 232 udelay(200); /* Overkill. Must wait > 200 bus cycles */ 233 234 #endif /* enable SDRAM init */ 235 } 236 237 #if defined(CONFIG_SYS_DRAM_TEST) 238 int 239 testdram(void) 240 { 241 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; 242 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; 243 uint *p; 244 245 printf("Testing DRAM from 0x%08x to 0x%08x\n", 246 CONFIG_SYS_MEMTEST_START, 247 CONFIG_SYS_MEMTEST_END); 248 249 printf("DRAM test phase 1:\n"); 250 for (p = pstart; p < pend; p++) 251 *p = 0xaaaaaaaa; 252 253 for (p = pstart; p < pend; p++) { 254 if (*p != 0xaaaaaaaa) { 255 printf ("DRAM test fails at: %08x\n", (uint) p); 256 return 1; 257 } 258 } 259 260 printf("DRAM test phase 2:\n"); 261 for (p = pstart; p < pend; p++) 262 *p = 0x55555555; 263 264 for (p = pstart; p < pend; p++) { 265 if (*p != 0x55555555) { 266 printf ("DRAM test fails at: %08x\n", (uint) p); 267 return 1; 268 } 269 } 270 271 printf("DRAM test passed.\n"); 272 return 0; 273 } 274 #endif 275 276 #if !defined(CONFIG_SPD_EEPROM) 277 /************************************************************************* 278 * fixed_sdram init -- doesn't use serial presence detect. 279 * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed. 280 ************************************************************************/ 281 long int fixed_sdram (void) 282 { 283 #define CONFIG_SYS_DDR_CONTROL 0xc300c000 284 285 volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); 286 287 ddr->cs0_bnds = 0x0000007f; 288 ddr->cs1_bnds = 0x008000ff; 289 ddr->cs2_bnds = 0x00000000; 290 ddr->cs3_bnds = 0x00000000; 291 ddr->cs0_config = 0x80010101; 292 ddr->cs1_config = 0x80010101; 293 ddr->cs2_config = 0x00000000; 294 ddr->cs3_config = 0x00000000; 295 ddr->timing_cfg_3 = 0x00000000; 296 ddr->timing_cfg_0 = 0x00220802; 297 ddr->timing_cfg_1 = 0x38377322; 298 ddr->timing_cfg_2 = 0x0fa044C7; 299 ddr->sdram_cfg = 0x4300C000; 300 ddr->sdram_cfg_2 = 0x24401000; 301 ddr->sdram_mode = 0x23C00542; 302 ddr->sdram_mode_2 = 0x00000000; 303 ddr->sdram_interval = 0x05080100; 304 ddr->sdram_md_cntl = 0x00000000; 305 ddr->sdram_data_init = 0x00000000; 306 ddr->sdram_clk_cntl = 0x03800000; 307 asm("sync;isync;msync"); 308 udelay(500); 309 310 #if defined (CONFIG_DDR_ECC) 311 /* Enable ECC checking */ 312 ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); 313 #else 314 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 315 #endif 316 317 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 318 } 319 #endif 320 321 #if defined(CONFIG_PCI) || defined(CONFIG_PCI1) 322 /* For some reason the Tundra PCI bridge shows up on itself as a 323 * different device. Work around that by refusing to configure it. 324 */ 325 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } 326 327 static struct pci_config_table pci_sbc8548_config_table[] = { 328 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, 329 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, 330 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, 331 mpc85xx_config_via_usbide, {0,0,0}}, 332 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, 333 mpc85xx_config_via_usb, {0,0,0}}, 334 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, 335 mpc85xx_config_via_usb2, {0,0,0}}, 336 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, 337 mpc85xx_config_via_power, {0,0,0}}, 338 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, 339 mpc85xx_config_via_ac97, {0,0,0}}, 340 {}, 341 }; 342 343 static struct pci_controller pci1_hose = { 344 config_table: pci_sbc8548_config_table}; 345 #endif /* CONFIG_PCI */ 346 347 #ifdef CONFIG_PCI2 348 static struct pci_controller pci2_hose; 349 #endif /* CONFIG_PCI2 */ 350 351 #ifdef CONFIG_PCIE1 352 static struct pci_controller pcie1_hose; 353 #endif /* CONFIG_PCIE1 */ 354 355 int first_free_busno=0; 356 357 extern int fsl_pci_setup_inbound_windows(struct pci_region *r); 358 extern void fsl_pci_init(struct pci_controller *hose); 359 360 void 361 pci_init_board(void) 362 { 363 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 364 365 #ifdef CONFIG_PCI1 366 { 367 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; 368 struct pci_controller *hose = &pci1_hose; 369 struct pci_config_table *table; 370 struct pci_region *r = hose->regions; 371 372 uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ 373 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ 374 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ 375 376 uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); 377 378 uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ 379 380 if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { 381 printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", 382 (pci_32) ? 32 : 64, 383 (pci_speed == 33333000) ? "33" : 384 (pci_speed == 66666000) ? "66" : "unknown", 385 pci_clk_sel ? "sync" : "async", 386 pci_agent ? "agent" : "host", 387 pci_arb ? "arbiter" : "external-arbiter" 388 ); 389 390 391 /* inbound */ 392 r += fsl_pci_setup_inbound_windows(r); 393 394 /* outbound memory */ 395 pci_set_region(r++, 396 CONFIG_SYS_PCI1_MEM_BASE, 397 CONFIG_SYS_PCI1_MEM_PHYS, 398 CONFIG_SYS_PCI1_MEM_SIZE, 399 PCI_REGION_MEM); 400 401 /* outbound io */ 402 pci_set_region(r++, 403 CONFIG_SYS_PCI1_IO_BASE, 404 CONFIG_SYS_PCI1_IO_PHYS, 405 CONFIG_SYS_PCI1_IO_SIZE, 406 PCI_REGION_IO); 407 hose->region_count = r - hose->regions; 408 409 /* relocate config table pointers */ 410 hose->config_table = \ 411 (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off); 412 for (table = hose->config_table; table && table->vendor; table++) 413 table->config_device += gd->reloc_off; 414 415 hose->first_busno=first_free_busno; 416 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 417 418 fsl_pci_init(hose); 419 first_free_busno=hose->last_busno+1; 420 printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); 421 #ifdef CONFIG_PCIX_CHECK 422 if (!(gur->pordevsr & PORDEVSR_PCI)) { 423 /* PCI-X init */ 424 if (CONFIG_SYS_CLK_FREQ < 66000000) 425 printf("PCI-X will only work at 66 MHz\n"); 426 427 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ 428 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; 429 pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16); 430 } 431 #endif 432 } else { 433 printf (" PCI: disabled\n"); 434 } 435 } 436 #else 437 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ 438 #endif 439 440 #ifdef CONFIG_PCI2 441 { 442 uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ 443 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ 444 if (pci_dual) { 445 printf (" PCI2: 32 bit, 66 MHz, %s\n", 446 pci2_clk_sel ? "sync" : "async"); 447 } else { 448 printf (" PCI2: disabled\n"); 449 } 450 } 451 #else 452 gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */ 453 #endif /* CONFIG_PCI2 */ 454 455 #ifdef CONFIG_PCIE1 456 { 457 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; 458 struct pci_controller *hose = &pcie1_hose; 459 int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); 460 struct pci_region *r = hose->regions; 461 462 int pcie_configured = io_sel >= 1; 463 464 if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ 465 printf ("\n PCIE connected to slot as %s (base address %x)", 466 pcie_ep ? "End Point" : "Root Complex", 467 (uint)pci); 468 469 if (pci->pme_msg_det) { 470 pci->pme_msg_det = 0xffffffff; 471 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 472 } 473 printf ("\n"); 474 475 /* inbound */ 476 pci_set_region(r++, 477 CONFIG_SYS_PCI_MEMORY_BUS, 478 CONFIG_SYS_PCI_MEMORY_PHYS, 479 CONFIG_SYS_PCI_MEMORY_SIZE, 480 PCI_REGION_MEM | PCI_REGION_MEMORY); 481 482 /* outbound memory */ 483 pci_set_region(r++, 484 CONFIG_SYS_PCIE1_MEM_BASE, 485 CONFIG_SYS_PCIE1_MEM_PHYS, 486 CONFIG_SYS_PCIE1_MEM_SIZE, 487 PCI_REGION_MEM); 488 489 /* outbound io */ 490 pci_set_region(r++, 491 CONFIG_SYS_PCIE1_IO_BASE, 492 CONFIG_SYS_PCIE1_IO_PHYS, 493 CONFIG_SYS_PCIE1_IO_SIZE, 494 PCI_REGION_IO); 495 496 hose->region_count = r - hose->regions; 497 498 hose->first_busno=first_free_busno; 499 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 500 501 fsl_pci_init(hose); 502 printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno); 503 504 first_free_busno=hose->last_busno+1; 505 506 } else { 507 printf (" PCIE: disabled\n"); 508 } 509 } 510 #else 511 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 512 #endif 513 514 } 515 516 int last_stage_init(void) 517 { 518 return 0; 519 } 520 521 #if defined(CONFIG_OF_BOARD_SETUP) 522 extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, 523 struct pci_controller *hose); 524 525 void ft_board_setup(void *blob, bd_t *bd) 526 { 527 ft_cpu_setup(blob, bd); 528 #ifdef CONFIG_PCI1 529 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); 530 #endif 531 #ifdef CONFIG_PCIE1 532 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); 533 #endif 534 } 535 #endif 536