1 /* 2 * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com> 3 * Copyright 2007 Embedded Specialties, Inc. 4 * 5 * Copyright 2004, 2007 Freescale Semiconductor. 6 * 7 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <common.h> 29 #include <pci.h> 30 #include <asm/processor.h> 31 #include <asm/immap_85xx.h> 32 #include <asm/immap_fsl_pci.h> 33 #include <spd.h> 34 #include <miiphy.h> 35 #include <libfdt.h> 36 #include <fdt_support.h> 37 38 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 39 extern void ddr_enable_ecc(unsigned int dram_size); 40 #endif 41 42 DECLARE_GLOBAL_DATA_PTR; 43 44 extern long int spd_sdram(void); 45 46 void local_bus_init(void); 47 void sdram_init(void); 48 long int fixed_sdram (void); 49 50 int board_early_init_f (void) 51 { 52 return 0; 53 } 54 55 int checkboard (void) 56 { 57 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 58 volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); 59 volatile u_char *rev= (void *)CFG_BD_REV; 60 61 printf ("Board: Wind River SBC8548 Rev. 0x%01x\n", 62 (*rev) >> 4); 63 64 /* 65 * Initialize local bus. 66 */ 67 local_bus_init (); 68 69 /* 70 * Fix CPU2 errata: A core hang possible while executing a 71 * msync instruction and a snoopable transaction from an I/O 72 * master tagged to make quick forward progress is present. 73 */ 74 ecm->eebpcr |= (1 << 16); 75 76 /* 77 * Hack TSEC 3 and 4 IO voltages. 78 */ 79 gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ 80 81 ecm->eedr = 0xffffffff; /* clear ecm errors */ 82 ecm->eeer = 0xffffffff; /* enable ecm errors */ 83 return 0; 84 } 85 86 long int 87 initdram(int board_type) 88 { 89 long dram_size = 0; 90 91 puts("Initializing\n"); 92 93 #if defined(CONFIG_DDR_DLL) 94 { 95 /* 96 * Work around to stabilize DDR DLL MSYNC_IN. 97 * Errata DDR9 seems to have been fixed. 98 * This is now the workaround for Errata DDR11: 99 * Override DLL = 1, Course Adj = 1, Tap Select = 0 100 */ 101 102 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 103 104 gur->ddrdllcr = 0x81000000; 105 asm("sync;isync;msync"); 106 udelay(200); 107 } 108 #endif 109 110 #if defined(CONFIG_SPD_EEPROM) 111 dram_size = spd_sdram (); 112 #else 113 dram_size = fixed_sdram (); 114 #endif 115 116 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 117 /* 118 * Initialize and enable DDR ECC. 119 */ 120 ddr_enable_ecc(dram_size); 121 #endif 122 /* 123 * SDRAM Initialization 124 */ 125 sdram_init(); 126 127 puts(" DDR: "); 128 return dram_size; 129 } 130 131 /* 132 * Initialize Local Bus 133 */ 134 void 135 local_bus_init(void) 136 { 137 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 138 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); 139 140 uint clkdiv; 141 uint lbc_hz; 142 sys_info_t sysinfo; 143 144 get_sys_info(&sysinfo); 145 clkdiv = (lbc->lcrr & 0x0f) * 2; 146 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; 147 148 gur->lbiuiplldcr1 = 0x00078080; 149 if (clkdiv == 16) { 150 gur->lbiuiplldcr0 = 0x7c0f1bf0; 151 } else if (clkdiv == 8) { 152 gur->lbiuiplldcr0 = 0x6c0f1bf0; 153 } else if (clkdiv == 4) { 154 gur->lbiuiplldcr0 = 0x5c0f1bf0; 155 } 156 157 lbc->lcrr |= 0x00030000; 158 159 asm("sync;isync;msync"); 160 161 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ 162 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ 163 } 164 165 /* 166 * Initialize SDRAM memory on the Local Bus. 167 */ 168 void 169 sdram_init(void) 170 { 171 #if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM) 172 173 uint idx; 174 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); 175 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; 176 uint lsdmr_common; 177 178 puts(" SDRAM: "); 179 180 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); 181 182 /* 183 * Setup SDRAM Base and Option Registers 184 */ 185 lbc->or3 = CFG_OR3_PRELIM; 186 asm("msync"); 187 188 lbc->br3 = CFG_BR3_PRELIM; 189 asm("msync"); 190 191 lbc->lbcr = CFG_LBC_LBCR; 192 asm("msync"); 193 194 195 lbc->lsrt = CFG_LBC_LSRT; 196 lbc->mrtpr = CFG_LBC_MRTPR; 197 asm("msync"); 198 199 /* 200 * MPC8548 uses "new" 15-16 style addressing. 201 */ 202 lsdmr_common = CFG_LBC_LSDMR_COMMON; 203 lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; 204 205 /* 206 * Issue PRECHARGE ALL command. 207 */ 208 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; 209 asm("sync;msync"); 210 *sdram_addr = 0xff; 211 ppcDcbf((unsigned long) sdram_addr); 212 udelay(100); 213 214 /* 215 * Issue 8 AUTO REFRESH commands. 216 */ 217 for (idx = 0; idx < 8; idx++) { 218 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; 219 asm("sync;msync"); 220 *sdram_addr = 0xff; 221 ppcDcbf((unsigned long) sdram_addr); 222 udelay(100); 223 } 224 225 /* 226 * Issue 8 MODE-set command. 227 */ 228 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; 229 asm("sync;msync"); 230 *sdram_addr = 0xff; 231 ppcDcbf((unsigned long) sdram_addr); 232 udelay(100); 233 234 /* 235 * Issue NORMAL OP command. 236 */ 237 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; 238 asm("sync;msync"); 239 *sdram_addr = 0xff; 240 ppcDcbf((unsigned long) sdram_addr); 241 udelay(200); /* Overkill. Must wait > 200 bus cycles */ 242 243 #endif /* enable SDRAM init */ 244 } 245 246 #if defined(CFG_DRAM_TEST) 247 int 248 testdram(void) 249 { 250 uint *pstart = (uint *) CFG_MEMTEST_START; 251 uint *pend = (uint *) CFG_MEMTEST_END; 252 uint *p; 253 254 printf("Testing DRAM from 0x%08x to 0x%08x\n", 255 CFG_MEMTEST_START, 256 CFG_MEMTEST_END); 257 258 printf("DRAM test phase 1:\n"); 259 for (p = pstart; p < pend; p++) 260 *p = 0xaaaaaaaa; 261 262 for (p = pstart; p < pend; p++) { 263 if (*p != 0xaaaaaaaa) { 264 printf ("DRAM test fails at: %08x\n", (uint) p); 265 return 1; 266 } 267 } 268 269 printf("DRAM test phase 2:\n"); 270 for (p = pstart; p < pend; p++) 271 *p = 0x55555555; 272 273 for (p = pstart; p < pend; p++) { 274 if (*p != 0x55555555) { 275 printf ("DRAM test fails at: %08x\n", (uint) p); 276 return 1; 277 } 278 } 279 280 printf("DRAM test passed.\n"); 281 return 0; 282 } 283 #endif 284 285 #if !defined(CONFIG_SPD_EEPROM) 286 /************************************************************************* 287 * fixed_sdram init -- doesn't use serial presence detect. 288 * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed. 289 ************************************************************************/ 290 long int fixed_sdram (void) 291 { 292 #define CFG_DDR_CONTROL 0xc300c000 293 294 volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR); 295 296 ddr->cs0_bnds = 0x0000007f; 297 ddr->cs1_bnds = 0x008000ff; 298 ddr->cs2_bnds = 0x00000000; 299 ddr->cs3_bnds = 0x00000000; 300 ddr->cs0_config = 0x80010101; 301 ddr->cs1_config = 0x80010101; 302 ddr->cs2_config = 0x00000000; 303 ddr->cs3_config = 0x00000000; 304 ddr->ext_refrec = 0x00000000; 305 ddr->timing_cfg_0 = 0x00220802; 306 ddr->timing_cfg_1 = 0x38377322; 307 ddr->timing_cfg_2 = 0x0fa044C7; 308 ddr->sdram_cfg = 0x4300C000; 309 ddr->sdram_cfg_2 = 0x24401000; 310 ddr->sdram_mode = 0x23C00542; 311 ddr->sdram_mode_2 = 0x00000000; 312 ddr->sdram_interval = 0x05080100; 313 ddr->sdram_md_cntl = 0x00000000; 314 ddr->sdram_data_init = 0x00000000; 315 ddr->sdram_clk_cntl = 0x03800000; 316 asm("sync;isync;msync"); 317 udelay(500); 318 319 #if defined (CONFIG_DDR_ECC) 320 /* Enable ECC checking */ 321 ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); 322 #else 323 ddr->sdram_cfg = CFG_DDR_CONTROL; 324 #endif 325 326 return CFG_SDRAM_SIZE * 1024 * 1024; 327 } 328 #endif 329 330 #if defined(CONFIG_PCI) || defined(CONFIG_PCI1) 331 /* For some reason the Tundra PCI bridge shows up on itself as a 332 * different device. Work around that by refusing to configure it. 333 */ 334 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } 335 336 static struct pci_config_table pci_sbc8548_config_table[] = { 337 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, 338 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, 339 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, 340 mpc85xx_config_via_usbide, {0,0,0}}, 341 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, 342 mpc85xx_config_via_usb, {0,0,0}}, 343 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, 344 mpc85xx_config_via_usb2, {0,0,0}}, 345 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, 346 mpc85xx_config_via_power, {0,0,0}}, 347 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, 348 mpc85xx_config_via_ac97, {0,0,0}}, 349 {}, 350 }; 351 352 static struct pci_controller pci1_hose = { 353 config_table: pci_sbc8548_config_table}; 354 #endif /* CONFIG_PCI */ 355 356 #ifdef CONFIG_PCI2 357 static struct pci_controller pci2_hose; 358 #endif /* CONFIG_PCI2 */ 359 360 #ifdef CONFIG_PCIE1 361 static struct pci_controller pcie1_hose; 362 #endif /* CONFIG_PCIE1 */ 363 364 int first_free_busno=0; 365 366 void 367 pci_init_board(void) 368 { 369 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 370 371 #ifdef CONFIG_PCI1 372 { 373 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; 374 extern void fsl_pci_init(struct pci_controller *hose); 375 struct pci_controller *hose = &pci1_hose; 376 struct pci_config_table *table; 377 378 uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ 379 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ 380 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ 381 382 uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); 383 384 uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ 385 386 if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { 387 printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", 388 (pci_32) ? 32 : 64, 389 (pci_speed == 33333000) ? "33" : 390 (pci_speed == 66666000) ? "66" : "unknown", 391 pci_clk_sel ? "sync" : "async", 392 pci_agent ? "agent" : "host", 393 pci_arb ? "arbiter" : "external-arbiter" 394 ); 395 396 397 /* inbound */ 398 pci_set_region(hose->regions + 0, 399 CFG_PCI_MEMORY_BUS, 400 CFG_PCI_MEMORY_PHYS, 401 CFG_PCI_MEMORY_SIZE, 402 PCI_REGION_MEM | PCI_REGION_MEMORY); 403 404 405 /* outbound memory */ 406 pci_set_region(hose->regions + 1, 407 CFG_PCI1_MEM_BASE, 408 CFG_PCI1_MEM_PHYS, 409 CFG_PCI1_MEM_SIZE, 410 PCI_REGION_MEM); 411 412 /* outbound io */ 413 pci_set_region(hose->regions + 2, 414 CFG_PCI1_IO_BASE, 415 CFG_PCI1_IO_PHYS, 416 CFG_PCI1_IO_SIZE, 417 PCI_REGION_IO); 418 hose->region_count = 3; 419 420 /* relocate config table pointers */ 421 hose->config_table = \ 422 (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off); 423 for (table = hose->config_table; table && table->vendor; table++) 424 table->config_device += gd->reloc_off; 425 426 hose->first_busno=first_free_busno; 427 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 428 429 fsl_pci_init(hose); 430 first_free_busno=hose->last_busno+1; 431 printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); 432 #ifdef CONFIG_PCIX_CHECK 433 if (!(gur->pordevsr & PORDEVSR_PCI)) { 434 /* PCI-X init */ 435 if (CONFIG_SYS_CLK_FREQ < 66000000) 436 printf("PCI-X will only work at 66 MHz\n"); 437 438 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ 439 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; 440 pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16); 441 } 442 #endif 443 } else { 444 printf (" PCI: disabled\n"); 445 } 446 } 447 #else 448 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ 449 #endif 450 451 #ifdef CONFIG_PCI2 452 { 453 uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ 454 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ 455 if (pci_dual) { 456 printf (" PCI2: 32 bit, 66 MHz, %s\n", 457 pci2_clk_sel ? "sync" : "async"); 458 } else { 459 printf (" PCI2: disabled\n"); 460 } 461 } 462 #else 463 gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */ 464 #endif /* CONFIG_PCI2 */ 465 466 #ifdef CONFIG_PCIE1 467 { 468 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; 469 extern void fsl_pci_init(struct pci_controller *hose); 470 struct pci_controller *hose = &pcie1_hose; 471 int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); 472 473 int pcie_configured = io_sel >= 1; 474 475 if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ 476 printf ("\n PCIE connected to slot as %s (base address %x)", 477 pcie_ep ? "End Point" : "Root Complex", 478 (uint)pci); 479 480 if (pci->pme_msg_det) { 481 pci->pme_msg_det = 0xffffffff; 482 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 483 } 484 printf ("\n"); 485 486 /* inbound */ 487 pci_set_region(hose->regions + 0, 488 CFG_PCI_MEMORY_BUS, 489 CFG_PCI_MEMORY_PHYS, 490 CFG_PCI_MEMORY_SIZE, 491 PCI_REGION_MEM | PCI_REGION_MEMORY); 492 493 /* outbound memory */ 494 pci_set_region(hose->regions + 1, 495 CFG_PCIE1_MEM_BASE, 496 CFG_PCIE1_MEM_PHYS, 497 CFG_PCIE1_MEM_SIZE, 498 PCI_REGION_MEM); 499 500 /* outbound io */ 501 pci_set_region(hose->regions + 2, 502 CFG_PCIE1_IO_BASE, 503 CFG_PCIE1_IO_PHYS, 504 CFG_PCIE1_IO_SIZE, 505 PCI_REGION_IO); 506 507 hose->region_count = 3; 508 509 hose->first_busno=first_free_busno; 510 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 511 512 fsl_pci_init(hose); 513 printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno); 514 515 first_free_busno=hose->last_busno+1; 516 517 } else { 518 printf (" PCIE: disabled\n"); 519 } 520 } 521 #else 522 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 523 #endif 524 525 } 526 527 int last_stage_init(void) 528 { 529 return 0; 530 } 531 532 #if defined(CONFIG_OF_BOARD_SETUP) 533 void 534 ft_pci_setup(void *blob, bd_t *bd) 535 { 536 int node, tmp[2]; 537 538 node = fdt_path_offset(blob, "/aliases"); 539 tmp[0] = 0; 540 if (node >= 0) { 541 #ifdef CONFIG_PCI1 542 const char *path; 543 path = fdt_getprop(blob, node, "pci0", NULL); 544 if (path) { 545 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; 546 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 547 } 548 #endif 549 #ifdef CONFIG_PCIE1 550 const char *path; 551 path = fdt_getprop(blob, node, "pci1", NULL); 552 if (path) { 553 tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; 554 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 555 } 556 #endif 557 } 558 } 559 #endif 560 561 #if defined(CONFIG_OF_BOARD_SETUP) 562 void 563 ft_board_setup(void *blob, bd_t *bd) 564 { 565 ft_cpu_setup(blob, bd); 566 #ifdef CONFIG_PCI 567 ft_pci_setup(blob, bd); 568 #endif 569 } 570 #endif 571