1 /* 2 * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com> 3 * 4 * Copyright 2007 Embedded Specialties, Inc. 5 * 6 * Copyright 2004, 2007 Freescale Semiconductor. 7 * 8 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 29 #include <common.h> 30 #include <pci.h> 31 #include <asm/processor.h> 32 #include <asm/immap_85xx.h> 33 #include <asm/fsl_pci.h> 34 #include <asm/fsl_ddr_sdram.h> 35 #include <asm/fsl_serdes.h> 36 #include <spd_sdram.h> 37 #include <netdev.h> 38 #include <tsec.h> 39 #include <miiphy.h> 40 #include <libfdt.h> 41 #include <fdt_support.h> 42 43 DECLARE_GLOBAL_DATA_PTR; 44 45 void local_bus_init(void); 46 void sdram_init(void); 47 long int fixed_sdram (void); 48 49 int board_early_init_f (void) 50 { 51 return 0; 52 } 53 54 int checkboard (void) 55 { 56 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 57 volatile u_char *rev= (void *)CONFIG_SYS_BD_REV; 58 59 printf ("Board: Wind River SBC8548 Rev. 0x%01x\n", 60 in_8(rev) >> 4); 61 62 /* 63 * Initialize local bus. 64 */ 65 local_bus_init (); 66 67 out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */ 68 out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */ 69 return 0; 70 } 71 72 phys_size_t 73 initdram(int board_type) 74 { 75 long dram_size = 0; 76 77 puts("Initializing\n"); 78 79 #if defined(CONFIG_DDR_DLL) 80 { 81 /* 82 * Work around to stabilize DDR DLL MSYNC_IN. 83 * Errata DDR9 seems to have been fixed. 84 * This is now the workaround for Errata DDR11: 85 * Override DLL = 1, Course Adj = 1, Tap Select = 0 86 */ 87 88 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 89 90 out_be32(&gur->ddrdllcr, 0x81000000); 91 asm("sync;isync;msync"); 92 udelay(200); 93 } 94 #endif 95 96 #if defined(CONFIG_SPD_EEPROM) 97 dram_size = fsl_ddr_sdram(); 98 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 99 dram_size *= 0x100000; 100 #else 101 dram_size = fixed_sdram (); 102 #endif 103 104 /* 105 * SDRAM Initialization 106 */ 107 sdram_init(); 108 109 puts(" DDR: "); 110 return dram_size; 111 } 112 113 /* 114 * Initialize Local Bus 115 */ 116 void 117 local_bus_init(void) 118 { 119 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 120 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 121 122 uint clkdiv; 123 uint lbc_hz; 124 sys_info_t sysinfo; 125 126 get_sys_info(&sysinfo); 127 clkdiv = (in_be32(&lbc->lcrr) & LCRR_CLKDIV) * 2; 128 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; 129 130 out_be32(&gur->lbiuiplldcr1, 0x00078080); 131 if (clkdiv == 16) { 132 out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0); 133 } else if (clkdiv == 8) { 134 out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0); 135 } else if (clkdiv == 4) { 136 out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0); 137 } 138 139 setbits_be32(&lbc->lcrr, 0x00030000); 140 141 asm("sync;isync;msync"); 142 143 out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */ 144 out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */ 145 } 146 147 /* 148 * Initialize SDRAM memory on the Local Bus. 149 */ 150 void 151 sdram_init(void) 152 { 153 #if defined(CONFIG_SYS_LBC_SDRAM_SIZE) 154 155 uint idx; 156 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 157 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; 158 uint lsdmr_common; 159 160 puts(" SDRAM: "); 161 162 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); 163 164 /* 165 * Setup SDRAM Base and Option Registers 166 */ 167 set_lbc_or(3, CONFIG_SYS_OR3_PRELIM); 168 set_lbc_br(3, CONFIG_SYS_BR3_PRELIM); 169 set_lbc_or(4, CONFIG_SYS_OR4_PRELIM); 170 set_lbc_br(4, CONFIG_SYS_BR4_PRELIM); 171 172 out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); 173 asm("msync"); 174 175 out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT); 176 out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR); 177 asm("msync"); 178 179 /* 180 * MPC8548 uses "new" 15-16 style addressing. 181 */ 182 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; 183 lsdmr_common |= LSDMR_BSMA1516; 184 185 /* 186 * Issue PRECHARGE ALL command. 187 */ 188 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_PCHALL); 189 asm("sync;msync"); 190 *sdram_addr = 0xff; 191 ppcDcbf((unsigned long) sdram_addr); 192 udelay(100); 193 194 /* 195 * Issue 8 AUTO REFRESH commands. 196 */ 197 for (idx = 0; idx < 8; idx++) { 198 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_ARFRSH); 199 asm("sync;msync"); 200 *sdram_addr = 0xff; 201 ppcDcbf((unsigned long) sdram_addr); 202 udelay(100); 203 } 204 205 /* 206 * Issue 8 MODE-set command. 207 */ 208 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_MRW); 209 asm("sync;msync"); 210 *sdram_addr = 0xff; 211 ppcDcbf((unsigned long) sdram_addr); 212 udelay(100); 213 214 /* 215 * Issue NORMAL OP command. 216 */ 217 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_NORMAL); 218 asm("sync;msync"); 219 *sdram_addr = 0xff; 220 ppcDcbf((unsigned long) sdram_addr); 221 udelay(200); /* Overkill. Must wait > 200 bus cycles */ 222 223 #endif /* enable SDRAM init */ 224 } 225 226 #if defined(CONFIG_SYS_DRAM_TEST) 227 int 228 testdram(void) 229 { 230 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; 231 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; 232 uint *p; 233 234 printf("Testing DRAM from 0x%08x to 0x%08x\n", 235 CONFIG_SYS_MEMTEST_START, 236 CONFIG_SYS_MEMTEST_END); 237 238 printf("DRAM test phase 1:\n"); 239 for (p = pstart; p < pend; p++) 240 *p = 0xaaaaaaaa; 241 242 for (p = pstart; p < pend; p++) { 243 if (*p != 0xaaaaaaaa) { 244 printf ("DRAM test fails at: %08x\n", (uint) p); 245 return 1; 246 } 247 } 248 249 printf("DRAM test phase 2:\n"); 250 for (p = pstart; p < pend; p++) 251 *p = 0x55555555; 252 253 for (p = pstart; p < pend; p++) { 254 if (*p != 0x55555555) { 255 printf ("DRAM test fails at: %08x\n", (uint) p); 256 return 1; 257 } 258 } 259 260 printf("DRAM test passed.\n"); 261 return 0; 262 } 263 #endif 264 265 #if !defined(CONFIG_SPD_EEPROM) 266 #define CONFIG_SYS_DDR_CONTROL 0xc300c000 267 /************************************************************************* 268 * fixed_sdram init -- doesn't use serial presence detect. 269 * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed. 270 ************************************************************************/ 271 long int fixed_sdram (void) 272 { 273 volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); 274 275 out_be32(&ddr->cs0_bnds, 0x0000007f); 276 out_be32(&ddr->cs1_bnds, 0x008000ff); 277 out_be32(&ddr->cs2_bnds, 0x00000000); 278 out_be32(&ddr->cs3_bnds, 0x00000000); 279 out_be32(&ddr->cs0_config, 0x80010101); 280 out_be32(&ddr->cs1_config, 0x80010101); 281 out_be32(&ddr->cs2_config, 0x00000000); 282 out_be32(&ddr->cs3_config, 0x00000000); 283 out_be32(&ddr->timing_cfg_3, 0x00000000); 284 out_be32(&ddr->timing_cfg_0, 0x00220802); 285 out_be32(&ddr->timing_cfg_1, 0x38377322); 286 out_be32(&ddr->timing_cfg_2, 0x0fa044C7); 287 out_be32(&ddr->sdram_cfg, 0x4300C000); 288 out_be32(&ddr->sdram_cfg_2, 0x24401000); 289 out_be32(&ddr->sdram_mode, 0x23C00542); 290 out_be32(&ddr->sdram_mode_2, 0x00000000); 291 out_be32(&ddr->sdram_interval, 0x05080100); 292 out_be32(&ddr->sdram_md_cntl, 0x00000000); 293 out_be32(&ddr->sdram_data_init, 0x00000000); 294 out_be32(&ddr->sdram_clk_cntl, 0x03800000); 295 asm("sync;isync;msync"); 296 udelay(500); 297 298 #if defined (CONFIG_DDR_ECC) 299 /* Enable ECC checking */ 300 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000); 301 #else 302 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); 303 #endif 304 305 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 306 } 307 #endif 308 309 #ifdef CONFIG_PCI1 310 static struct pci_controller pci1_hose; 311 #endif /* CONFIG_PCI1 */ 312 313 #ifdef CONFIG_PCIE1 314 static struct pci_controller pcie1_hose; 315 #endif /* CONFIG_PCIE1 */ 316 317 318 #ifdef CONFIG_PCI 319 void 320 pci_init_board(void) 321 { 322 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 323 struct fsl_pci_info pci_info[2]; 324 u32 devdisr, pordevsr, porpllsr, io_sel; 325 int first_free_busno = 0; 326 int num = 0; 327 328 #ifdef CONFIG_PCIE1 329 int pcie_configured; 330 #endif 331 332 devdisr = in_be32(&gur->devdisr); 333 pordevsr = in_be32(&gur->pordevsr); 334 porpllsr = in_be32(&gur->porpllsr); 335 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 336 337 debug(" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); 338 339 #ifdef CONFIG_PCI1 340 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 341 uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; 342 uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; 343 uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; 344 uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */ 345 346 printf("PCI: Host, %d bit, %s MHz, %s, %s\n", 347 (pci_32) ? 32 : 64, 348 (pci_speed == 33000000) ? "33" : 349 (pci_speed == 66000000) ? "66" : "unknown", 350 pci_clk_sel ? "sync" : "async", 351 pci_arb ? "arbiter" : "external-arbiter"); 352 353 SET_STD_PCI_INFO(pci_info[num], 1); 354 first_free_busno = fsl_pci_init_port(&pci_info[num++], 355 &pci1_hose, first_free_busno); 356 } else { 357 printf("PCI: disabled\n"); 358 } 359 360 puts("\n"); 361 #else 362 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ 363 #endif 364 365 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */ 366 367 #ifdef CONFIG_PCIE1 368 pcie_configured = is_serdes_configured(PCIE1); 369 370 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 371 SET_STD_PCIE_INFO(pci_info[num], 1); 372 printf("PCIE: base address %lx\n", pci_info[num].regs); 373 first_free_busno = fsl_pci_init_port(&pci_info[num++], 374 &pcie1_hose, first_free_busno); 375 } else { 376 printf("PCIE: disabled\n"); 377 } 378 379 puts("\n"); 380 #else 381 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ 382 #endif 383 } 384 #endif 385 386 int board_eth_init(bd_t *bis) 387 { 388 tsec_standard_init(bis); 389 pci_eth_init(bis); 390 return 0; /* otherwise cpu_eth_init gets run */ 391 } 392 393 int last_stage_init(void) 394 { 395 return 0; 396 } 397 398 #if defined(CONFIG_OF_BOARD_SETUP) 399 void ft_board_setup(void *blob, bd_t *bd) 400 { 401 ft_cpu_setup(blob, bd); 402 403 #ifdef CONFIG_FSL_PCI_INIT 404 FT_FSL_PCI_SETUP; 405 #endif 406 } 407 #endif 408