xref: /rk3399_rockchip-uboot/arch/x86/dts/chromebook_link.dts (revision e3b5f04143a859092d4e09f61e526790836714f2) 
1/dts-v1/;
2
3/include/ "skeleton.dtsi"
4/include/ "keyboard.dtsi"
5/include/ "serial.dtsi"
6/include/ "rtc.dtsi"
7/include/ "tsc_timer.dtsi"
8
9/ {
10	model = "Google Link";
11	compatible = "google,link", "intel,celeron-ivybridge";
12
13	aliases {
14		spi0 = "/pci/pch/spi";
15	};
16
17	config {
18	       silent_console = <0>;
19	};
20
21	cpus {
22		#address-cells = <1>;
23		#size-cells = <0>;
24
25		cpu@0 {
26			device_type = "cpu";
27			compatible = "intel,core-gen3";
28			reg = <0>;
29			intel,apic-id = <0>;
30		};
31
32		cpu@1 {
33			device_type = "cpu";
34			compatible = "intel,core-gen3";
35			reg = <1>;
36			intel,apic-id = <1>;
37		};
38
39		cpu@2 {
40			device_type = "cpu";
41			compatible = "intel,core-gen3";
42			reg = <2>;
43			intel,apic-id = <2>;
44		};
45
46		cpu@3 {
47			device_type = "cpu";
48			compatible = "intel,core-gen3";
49			reg = <3>;
50			intel,apic-id = <3>;
51		};
52
53	};
54
55	gpioa {
56		compatible = "intel,ich6-gpio";
57		u-boot,dm-pre-reloc;
58		reg = <0 0x10>;
59		bank-name = "A";
60	};
61
62	gpiob {
63		compatible = "intel,ich6-gpio";
64		u-boot,dm-pre-reloc;
65		reg = <0x30 0x10>;
66		bank-name = "B";
67	};
68
69	gpioc {
70		compatible = "intel,ich6-gpio";
71		u-boot,dm-pre-reloc;
72		reg = <0x40 0x10>;
73		bank-name = "C";
74	};
75
76	chosen {
77		stdout-path = "/serial";
78	};
79
80	keyboard {
81		intel,duplicate-por;
82	};
83
84	spd {
85		compatible = "memory-spd";
86		#address-cells = <1>;
87		#size-cells = <0>;
88		elpida_4Gb_1600_x16 {
89			reg = <0>;
90			data = [92 10 0b 03 04 19 02 02
91				03 52 01 08 0a 00 fe 00
92				69 78 69 3c 69 11 18 81
93				20 08 3c 3c 01 40 83 81
94				00 00 00 00 00 00 00 00
95				00 00 00 00 00 00 00 00
96				00 00 00 00 00 00 00 00
97				00 00 00 00 0f 11 42 00
98				00 00 00 00 00 00 00 00
99				00 00 00 00 00 00 00 00
100				00 00 00 00 00 00 00 00
101				00 00 00 00 00 00 00 00
102				00 00 00 00 00 00 00 00
103				00 00 00 00 00 00 00 00
104				00 00 00 00 00 02 fe 00
105				11 52 00 00 00 07 7f 37
106				45 42 4a 32 30 55 47 36
107				45 42 55 30 2d 47 4e 2d
108				46 20 30 20 02 fe 00 00
109				00 00 00 00 00 00 00 00
110				00 00 00 00 00 00 00 00
111				00 00 00 00 00 00 00 00
112				00 00 00 00 00 00 00 00
113				00 00 00 00 00 00 00 00
114				00 00 00 00 00 00 00 00
115				00 00 00 00 00 00 00 00
116				00 00 00 00 00 00 00 00
117				00 00 00 00 00 00 00 00
118				00 00 00 00 00 00 00 00
119				00 00 00 00 00 00 00 00
120				00 00 00 00 00 00 00 00
121				00 00 00 00 00 00 00 00];
122		};
123		samsung_4Gb_1600_1.35v_x16 {
124			reg = <1>;
125			data = [92 11 0b 03 04 19 02 02
126				03 11 01 08 0a 00 fe 00
127				69 78 69 3c 69 11 18 81
128				f0 0a 3c 3c 01 40 83 01
129				00 80 00 00 00 00 00 00
130				00 00 00 00 00 00 00 00
131				00 00 00 00 00 00 00 00
132				00 00 00 00 0f 11 02 00
133				00 00 00 00 00 00 00 00
134				00 00 00 00 00 00 00 00
135				00 00 00 00 00 00 00 00
136				00 00 00 00 00 00 00 00
137				00 00 00 00 00 00 00 00
138				00 00 00 00 00 00 00 00
139				00 00 00 00 00 80 ce 01
140				00 00 00 00 00 00 6a 04
141				4d 34 37 31 42 35 36 37
142				34 42 48 30 2d 59 4b 30
143				20 20 00 00 80 ce 00 00
144				00 00 00 00 00 00 00 00
145				00 00 00 00 00 00 00 00
146				00 00 00 00 00 00 00 00
147				00 00 00 00 00 00 00 00
148				00 00 00 00 00 00 00 00
149				00 00 00 00 00 00 00 00
150				00 00 00 00 00 00 00 00
151				00 00 00 00 00 00 00 00
152				00 00 00 00 00 00 00 00
153				00 00 00 00 00 00 00 00
154				00 00 00 00 00 00 00 00
155				00 00 00 00 00 00 00 00
156				00 00 00 00 00 00 00 00];
157			};
158		micron_4Gb_1600_1.35v_x16 {
159			reg = <2>;
160			data = [92 11 0b 03 04 19 02 02
161				03 11 01 08 0a 00 fe 00
162				69 78 69 3c 69 11 18 81
163				20 08 3c 3c 01 40 83 05
164				00 00 00 00 00 00 00 00
165				00 00 00 00 00 00 00 00
166				00 00 00 00 00 00 00 00
167				00 00 00 00 0f 01 02 00
168				00 00 00 00 00 00 00 00
169				00 00 00 00 00 00 00 00
170				00 00 00 00 00 00 00 00
171				00 00 00 00 00 00 00 00
172				00 00 00 00 00 00 00 00
173				00 00 00 00 00 00 00 00
174				00 00 00 00 00 80 2c 00
175				00 00 00 00 00 00 ad 75
176				34 4b 54 46 32 35 36 36
177				34 48 5a 2d 31 47 36 45
178				31 20 45 31 80 2c 00 00
179				00 00 00 00 00 00 00 00
180				00 00 00 00 00 00 00 00
181				00 00 00 00 00 00 00 00
182				ff ff ff ff ff ff ff ff
183				ff ff ff ff ff ff ff ff
184				ff ff ff ff ff ff ff ff
185				ff ff ff ff ff ff ff ff
186				ff ff ff ff ff ff ff ff
187				ff ff ff ff ff ff ff ff
188				ff ff ff ff ff ff ff ff
189				ff ff ff ff ff ff ff ff
190				ff ff ff ff ff ff ff ff
191				ff ff ff ff ff ff ff ff];
192		};
193	};
194
195	pci {
196		compatible = "intel,pci-ivybridge", "pci-x86";
197		#address-cells = <3>;
198		#size-cells = <2>;
199		u-boot,dm-pre-reloc;
200		ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
201			0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
202			0x01000000 0x0 0x1000 0x1000 0 0xefff>;
203
204		northbridge@0,0 {
205			reg = <0x00000000 0 0 0 0>;
206			compatible = "intel,bd82x6x-northbridge";
207			u-boot,dm-pre-reloc;
208		};
209
210		sata {
211			compatible = "intel,pantherpoint-ahci";
212			intel,sata-mode = "ahci";
213			intel,sata-port-map = <1>;
214			intel,sata-port0-gen3-tx = <0x00880a7f>;
215		};
216
217		gma {
218			compatible = "intel,gma";
219			intel,dp_hotplug = <0 0 0x06>;
220			intel,panel-port-select = <1>;
221			intel,panel-power-cycle-delay = <6>;
222			intel,panel-power-up-delay = <2000>;
223			intel,panel-power-down-delay = <500>;
224			intel,panel-power-backlight-on-delay = <2000>;
225			intel,panel-power-backlight-off-delay = <2000>;
226			intel,cpu-backlight = <0x00000200>;
227			intel,pch-backlight = <0x04000000>;
228		};
229
230		pch@1f,0 {
231			reg = <0x0000f800 0 0 0 0>;
232			compatible = "intel,bd82x6x", "intel,pch9";
233			u-boot,dm-pre-reloc;
234			#address-cells = <1>;
235			#size-cells = <1>;
236			intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
237						0x80 0x80 0x80 0x80>;
238			intel,gpi-routing = <0 0 0 0 0 0 0 2
239						1 0 0 0 0 0 0 0>;
240			/* Enable EC SMI source */
241			intel,alt-gp-smi-enable = <0x0100>;
242
243			spi {
244				#address-cells = <1>;
245				#size-cells = <0>;
246				compatible = "intel,ich-spi";
247				spi-flash@0 {
248					#size-cells = <1>;
249					#address-cells = <1>;
250					reg = <0>;
251					compatible = "winbond,w25q64",
252							"spi-flash";
253					memory-map = <0xff800000 0x00800000>;
254					rw-mrc-cache {
255						label = "rw-mrc-cache";
256						reg = <0x003e0000 0x00010000>;
257					};
258				};
259			};
260
261			lpc {
262				compatible = "intel,bd82x6x-lpc";
263				#address-cells = <1>;
264				#size-cells = <0>;
265				u-boot,dm-pre-reloc;
266				intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
267				cros-ec@200 {
268					compatible = "google,cros-ec";
269					reg = <0x204 1 0x200 1 0x880 0x80>;
270
271					/*
272					 * Describes the flash memory within
273					 * the EC
274					 */
275					#address-cells = <1>;
276					#size-cells = <1>;
277					flash@8000000 {
278						reg = <0x08000000 0x20000>;
279						erase-value = <0xff>;
280					};
281				};
282			};
283		};
284	};
285
286	tpm {
287		reg = <0xfed40000 0x5000>;
288		compatible = "infineon,slb9635lpc";
289	};
290
291	microcode {
292		update@0 {
293#include "microcode/m12306a9_0000001b.dtsi"
294		};
295	};
296
297};
298