1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * (C) Copyright 2010,2011 4 * Graeme Russ, <graeme.russ@gmail.com> 5 * 6 * Portions from Coreboot mainboard/google/link/romstage.c 7 * Copyright (C) 2007-2010 coresystems GmbH 8 * Copyright (C) 2011 Google Inc. 9 * 10 * SPDX-License-Identifier: GPL-2.0 11 */ 12 13 #include <common.h> 14 #include <errno.h> 15 #include <fdtdec.h> 16 #include <malloc.h> 17 #include <net.h> 18 #include <rtc.h> 19 #include <spi.h> 20 #include <spi_flash.h> 21 #include <asm/processor.h> 22 #include <asm/gpio.h> 23 #include <asm/global_data.h> 24 #include <asm/mrccache.h> 25 #include <asm/mtrr.h> 26 #include <asm/pci.h> 27 #include <asm/arch/me.h> 28 #include <asm/arch/pei_data.h> 29 #include <asm/arch/pch.h> 30 #include <asm/post.h> 31 #include <asm/arch/sandybridge.h> 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 #define CMOS_OFFSET_MRC_SEED 152 36 #define CMOS_OFFSET_MRC_SEED_S3 156 37 #define CMOS_OFFSET_MRC_SEED_CHK 160 38 39 /* 40 * This function looks for the highest region of memory lower than 4GB which 41 * has enough space for U-Boot where U-Boot is aligned on a page boundary. 42 * It overrides the default implementation found elsewhere which simply 43 * picks the end of ram, wherever that may be. The location of the stack, 44 * the relocation address, and how far U-Boot is moved by relocation are 45 * set in the global data structure. 46 */ 47 ulong board_get_usable_ram_top(ulong total_size) 48 { 49 struct memory_info *info = &gd->arch.meminfo; 50 uintptr_t dest_addr = 0; 51 struct memory_area *largest = NULL; 52 int i; 53 54 /* Find largest area of memory below 4GB */ 55 56 for (i = 0; i < info->num_areas; i++) { 57 struct memory_area *area = &info->area[i]; 58 59 if (area->start >= 1ULL << 32) 60 continue; 61 if (!largest || area->size > largest->size) 62 largest = area; 63 } 64 65 /* If no suitable area was found, return an error. */ 66 assert(largest); 67 if (!largest || largest->size < (2 << 20)) 68 panic("No available memory found for relocation"); 69 70 dest_addr = largest->start + largest->size; 71 72 return (ulong)dest_addr; 73 } 74 75 void dram_init_banksize(void) 76 { 77 struct memory_info *info = &gd->arch.meminfo; 78 int num_banks; 79 int i; 80 81 for (i = 0, num_banks = 0; i < info->num_areas; i++) { 82 struct memory_area *area = &info->area[i]; 83 84 if (area->start >= 1ULL << 32) 85 continue; 86 gd->bd->bi_dram[num_banks].start = area->start; 87 gd->bd->bi_dram[num_banks].size = area->size; 88 num_banks++; 89 } 90 } 91 92 static int read_seed_from_cmos(struct pei_data *pei_data) 93 { 94 u16 c1, c2, checksum, seed_checksum; 95 struct udevice *dev; 96 int ret = 0; 97 98 ret = uclass_get_device(UCLASS_RTC, 0, &dev); 99 if (ret) { 100 debug("Cannot find RTC: err=%d\n", ret); 101 return -ENODEV; 102 } 103 104 /* 105 * Read scrambler seeds from CMOS RAM. We don't want to store them in 106 * SPI flash since they change on every boot and that would wear down 107 * the flash too much. So we store these in CMOS and the large MRC 108 * data in SPI flash. 109 */ 110 ret = rtc_read32(dev, CMOS_OFFSET_MRC_SEED, &pei_data->scrambler_seed); 111 if (!ret) { 112 ret = rtc_read32(dev, CMOS_OFFSET_MRC_SEED_S3, 113 &pei_data->scrambler_seed_s3); 114 } 115 if (ret) { 116 debug("Failed to read from RTC %s\n", dev->name); 117 return ret; 118 } 119 120 debug("Read scrambler seed 0x%08x from CMOS 0x%02x\n", 121 pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); 122 debug("Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n", 123 pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); 124 125 /* Compute seed checksum and compare */ 126 c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed, 127 sizeof(u32)); 128 c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3, 129 sizeof(u32)); 130 checksum = add_ip_checksums(sizeof(u32), c1, c2); 131 132 seed_checksum = rtc_read8(dev, CMOS_OFFSET_MRC_SEED_CHK); 133 seed_checksum |= rtc_read8(dev, CMOS_OFFSET_MRC_SEED_CHK + 1) << 8; 134 135 if (checksum != seed_checksum) { 136 debug("%s: invalid seed checksum\n", __func__); 137 pei_data->scrambler_seed = 0; 138 pei_data->scrambler_seed_s3 = 0; 139 return -EINVAL; 140 } 141 142 return 0; 143 } 144 145 static int prepare_mrc_cache(struct pei_data *pei_data) 146 { 147 struct mrc_data_container *mrc_cache; 148 struct mrc_region entry; 149 int ret; 150 151 ret = read_seed_from_cmos(pei_data); 152 if (ret) 153 return ret; 154 ret = mrccache_get_region(NULL, &entry); 155 if (ret) 156 return ret; 157 mrc_cache = mrccache_find_current(&entry); 158 if (!mrc_cache) 159 return -ENOENT; 160 161 /* 162 * TODO(sjg@chromium.org): Skip this for now as it causes boot 163 * problems 164 */ 165 if (0) { 166 pei_data->mrc_input = mrc_cache->data; 167 pei_data->mrc_input_len = mrc_cache->data_size; 168 } 169 debug("%s: at %p, size %x checksum %04x\n", __func__, 170 pei_data->mrc_input, pei_data->mrc_input_len, 171 mrc_cache->checksum); 172 173 return 0; 174 } 175 176 static int write_seeds_to_cmos(struct pei_data *pei_data) 177 { 178 u16 c1, c2, checksum; 179 struct udevice *dev; 180 int ret = 0; 181 182 ret = uclass_get_device(UCLASS_RTC, 0, &dev); 183 if (ret) { 184 debug("Cannot find RTC: err=%d\n", ret); 185 return -ENODEV; 186 } 187 188 /* Save the MRC seed values to CMOS */ 189 rtc_write32(dev, CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed); 190 debug("Save scrambler seed 0x%08x to CMOS 0x%02x\n", 191 pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); 192 193 rtc_write32(dev, CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3); 194 debug("Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n", 195 pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); 196 197 /* Save a simple checksum of the seed values */ 198 c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed, 199 sizeof(u32)); 200 c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3, 201 sizeof(u32)); 202 checksum = add_ip_checksums(sizeof(u32), c1, c2); 203 204 rtc_write8(dev, CMOS_OFFSET_MRC_SEED_CHK, checksum & 0xff); 205 rtc_write8(dev, CMOS_OFFSET_MRC_SEED_CHK + 1, (checksum >> 8) & 0xff); 206 207 return 0; 208 } 209 210 /* Use this hook to save our SDRAM parameters */ 211 int misc_init_r(void) 212 { 213 int ret; 214 215 ret = mrccache_save(); 216 if (ret) 217 printf("Unable to save MRC data: %d\n", ret); 218 219 return 0; 220 } 221 222 static const char *const ecc_decoder[] = { 223 "inactive", 224 "active on IO", 225 "disabled on IO", 226 "active" 227 }; 228 229 /* 230 * Dump in the log memory controller configuration as read from the memory 231 * controller registers. 232 */ 233 static void report_memory_config(void) 234 { 235 u32 addr_decoder_common, addr_decode_ch[2]; 236 int i; 237 238 addr_decoder_common = readl(MCHBAR_REG(0x5000)); 239 addr_decode_ch[0] = readl(MCHBAR_REG(0x5004)); 240 addr_decode_ch[1] = readl(MCHBAR_REG(0x5008)); 241 242 debug("memcfg DDR3 clock %d MHz\n", 243 (readl(MCHBAR_REG(0x5e04)) * 13333 * 2 + 50) / 100); 244 debug("memcfg channel assignment: A: %d, B % d, C % d\n", 245 addr_decoder_common & 3, 246 (addr_decoder_common >> 2) & 3, 247 (addr_decoder_common >> 4) & 3); 248 249 for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { 250 u32 ch_conf = addr_decode_ch[i]; 251 debug("memcfg channel[%d] config (%8.8x):\n", i, ch_conf); 252 debug(" ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); 253 debug(" enhanced interleave mode %s\n", 254 ((ch_conf >> 22) & 1) ? "on" : "off"); 255 debug(" rank interleave %s\n", 256 ((ch_conf >> 21) & 1) ? "on" : "off"); 257 debug(" DIMMA %d MB width x%d %s rank%s\n", 258 ((ch_conf >> 0) & 0xff) * 256, 259 ((ch_conf >> 19) & 1) ? 16 : 8, 260 ((ch_conf >> 17) & 1) ? "dual" : "single", 261 ((ch_conf >> 16) & 1) ? "" : ", selected"); 262 debug(" DIMMB %d MB width x%d %s rank%s\n", 263 ((ch_conf >> 8) & 0xff) * 256, 264 ((ch_conf >> 20) & 1) ? 16 : 8, 265 ((ch_conf >> 18) & 1) ? "dual" : "single", 266 ((ch_conf >> 16) & 1) ? ", selected" : ""); 267 } 268 } 269 270 static void post_system_agent_init(struct pei_data *pei_data) 271 { 272 /* If PCIe init is skipped, set the PEG clock gating */ 273 if (!pei_data->pcie_init) 274 setbits_le32(MCHBAR_REG(0x7010), 1); 275 } 276 277 static asmlinkage void console_tx_byte(unsigned char byte) 278 { 279 #ifdef DEBUG 280 putc(byte); 281 #endif 282 } 283 284 static int recovery_mode_enabled(void) 285 { 286 return false; 287 } 288 289 /** 290 * Find the PEI executable in the ROM and execute it. 291 * 292 * @param pei_data: configuration data for UEFI PEI reference code 293 */ 294 int sdram_initialise(struct pei_data *pei_data) 295 { 296 unsigned version; 297 const char *data; 298 uint16_t done; 299 int ret; 300 301 report_platform_info(); 302 303 /* Wait for ME to be ready */ 304 ret = intel_early_me_init(); 305 if (ret) 306 return ret; 307 ret = intel_early_me_uma_size(); 308 if (ret < 0) 309 return ret; 310 311 debug("Starting UEFI PEI System Agent\n"); 312 313 /* 314 * Do not pass MRC data in for recovery mode boot, 315 * Always pass it in for S3 resume. 316 */ 317 if (!recovery_mode_enabled() || 318 pei_data->boot_mode == PEI_BOOT_RESUME) { 319 ret = prepare_mrc_cache(pei_data); 320 if (ret) 321 debug("prepare_mrc_cache failed: %d\n", ret); 322 } 323 324 /* If MRC data is not found we cannot continue S3 resume. */ 325 if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) { 326 debug("Giving up in sdram_initialize: No MRC data\n"); 327 reset_cpu(0); 328 } 329 330 /* Pass console handler in pei_data */ 331 pei_data->tx_byte = console_tx_byte; 332 333 debug("PEI data at %p, size %x:\n", pei_data, sizeof(*pei_data)); 334 335 data = (char *)CONFIG_X86_MRC_ADDR; 336 if (data) { 337 int rv; 338 int (*func)(struct pei_data *); 339 340 debug("Calling MRC at %p\n", data); 341 post_code(POST_PRE_MRC); 342 func = (int (*)(struct pei_data *))data; 343 rv = func(pei_data); 344 post_code(POST_MRC); 345 if (rv) { 346 switch (rv) { 347 case -1: 348 printf("PEI version mismatch.\n"); 349 break; 350 case -2: 351 printf("Invalid memory frequency.\n"); 352 break; 353 default: 354 printf("MRC returned %x.\n", rv); 355 } 356 printf("Nonzero MRC return value.\n"); 357 return -EFAULT; 358 } 359 } else { 360 printf("UEFI PEI System Agent not found.\n"); 361 return -ENOSYS; 362 } 363 364 #if CONFIG_USBDEBUG 365 /* mrc.bin reconfigures USB, so reinit it to have debug */ 366 early_usbdebug_init(); 367 #endif 368 369 version = readl(MCHBAR_REG(0x5034)); 370 debug("System Agent Version %d.%d.%d Build %d\n", 371 version >> 24 , (version >> 16) & 0xff, 372 (version >> 8) & 0xff, version & 0xff); 373 debug("MRC output data length %#x at %p\n", pei_data->mrc_output_len, 374 pei_data->mrc_output); 375 376 /* 377 * Send ME init done for SandyBridge here. This is done inside the 378 * SystemAgent binary on IvyBridge 379 */ 380 done = x86_pci_read_config32(PCH_DEV, PCI_DEVICE_ID); 381 done &= BASE_REV_MASK; 382 if (BASE_REV_SNB == done) 383 intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); 384 else 385 intel_early_me_status(); 386 387 post_system_agent_init(pei_data); 388 report_memory_config(); 389 390 /* S3 resume: don't save scrambler seed or MRC data */ 391 if (pei_data->boot_mode != PEI_BOOT_RESUME) { 392 /* 393 * This will be copied to SDRAM in reserve_arch(), then written 394 * to SPI flash in mrccache_save() 395 */ 396 gd->arch.mrc_output = (char *)pei_data->mrc_output; 397 gd->arch.mrc_output_len = pei_data->mrc_output_len; 398 ret = write_seeds_to_cmos(pei_data); 399 if (ret) 400 debug("Failed to write seeds to CMOS: %d\n", ret); 401 } 402 403 return 0; 404 } 405 406 int reserve_arch(void) 407 { 408 return mrccache_reserve(); 409 } 410 411 static int copy_spd(struct pei_data *peid) 412 { 413 const int gpio_vector[] = {41, 42, 43, 10, -1}; 414 int spd_index; 415 const void *blob = gd->fdt_blob; 416 int node, spd_node; 417 int ret, i; 418 419 for (i = 0; ; i++) { 420 if (gpio_vector[i] == -1) 421 break; 422 ret = gpio_requestf(gpio_vector[i], "spd_id%d", i); 423 if (ret) { 424 debug("%s: Could not request gpio %d\n", __func__, 425 gpio_vector[i]); 426 return ret; 427 } 428 } 429 spd_index = gpio_get_values_as_int(gpio_vector); 430 debug("spd index %d\n", spd_index); 431 node = fdtdec_next_compatible(blob, 0, COMPAT_MEMORY_SPD); 432 if (node < 0) { 433 printf("SPD data not found.\n"); 434 return -ENOENT; 435 } 436 437 for (spd_node = fdt_first_subnode(blob, node); 438 spd_node > 0; 439 spd_node = fdt_next_subnode(blob, spd_node)) { 440 const char *data; 441 int len; 442 443 if (fdtdec_get_int(blob, spd_node, "reg", -1) != spd_index) 444 continue; 445 data = fdt_getprop(blob, spd_node, "data", &len); 446 if (len < sizeof(peid->spd_data[0])) { 447 printf("Missing SPD data\n"); 448 return -EINVAL; 449 } 450 451 debug("Using SDRAM SPD data for '%s'\n", 452 fdt_get_name(blob, spd_node, NULL)); 453 memcpy(peid->spd_data[0], data, sizeof(peid->spd_data[0])); 454 break; 455 } 456 457 if (spd_node < 0) { 458 printf("No SPD data found for index %d\n", spd_index); 459 return -ENOENT; 460 } 461 462 return 0; 463 } 464 465 /** 466 * add_memory_area() - Add a new usable memory area to our list 467 * 468 * Note: @start and @end must not span the first 4GB boundary 469 * 470 * @info: Place to store memory info 471 * @start: Start of this memory area 472 * @end: End of this memory area + 1 473 */ 474 static int add_memory_area(struct memory_info *info, 475 uint64_t start, uint64_t end) 476 { 477 struct memory_area *ptr; 478 479 if (info->num_areas == CONFIG_NR_DRAM_BANKS) 480 return -ENOSPC; 481 482 ptr = &info->area[info->num_areas]; 483 ptr->start = start; 484 ptr->size = end - start; 485 info->total_memory += ptr->size; 486 if (ptr->start < (1ULL << 32)) 487 info->total_32bit_memory += ptr->size; 488 debug("%d: memory %llx size %llx, total now %llx / %llx\n", 489 info->num_areas, ptr->start, ptr->size, 490 info->total_32bit_memory, info->total_memory); 491 info->num_areas++; 492 493 return 0; 494 } 495 496 /** 497 * sdram_find() - Find available memory 498 * 499 * This is a bit complicated since on x86 there are system memory holes all 500 * over the place. We create a list of available memory blocks 501 */ 502 static int sdram_find(pci_dev_t dev) 503 { 504 struct memory_info *info = &gd->arch.meminfo; 505 uint32_t tseg_base, uma_size, tolud; 506 uint64_t tom, me_base, touud; 507 uint64_t uma_memory_base = 0; 508 uint64_t uma_memory_size; 509 unsigned long long tomk; 510 uint16_t ggc; 511 512 /* Total Memory 2GB example: 513 * 514 * 00000000 0000MB-1992MB 1992MB RAM (writeback) 515 * 7c800000 1992MB-2000MB 8MB TSEG (SMRR) 516 * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached) 517 * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached) 518 * 7f200000 2034MB TOLUD 519 * 7f800000 2040MB MEBASE 520 * 7f800000 2040MB-2048MB 8MB ME UMA (uncached) 521 * 80000000 2048MB TOM 522 * 100000000 4096MB-4102MB 6MB RAM (writeback) 523 * 524 * Total Memory 4GB example: 525 * 526 * 00000000 0000MB-2768MB 2768MB RAM (writeback) 527 * ad000000 2768MB-2776MB 8MB TSEG (SMRR) 528 * ad800000 2776MB-2778MB 2MB GFX GTT (uncached) 529 * ada00000 2778MB-2810MB 32MB GFX UMA (uncached) 530 * afa00000 2810MB TOLUD 531 * ff800000 4088MB MEBASE 532 * ff800000 4088MB-4096MB 8MB ME UMA (uncached) 533 * 100000000 4096MB TOM 534 * 100000000 4096MB-5374MB 1278MB RAM (writeback) 535 * 14fe00000 5368MB TOUUD 536 */ 537 538 /* Top of Upper Usable DRAM, including remap */ 539 touud = x86_pci_read_config32(dev, TOUUD+4); 540 touud <<= 32; 541 touud |= x86_pci_read_config32(dev, TOUUD); 542 543 /* Top of Lower Usable DRAM */ 544 tolud = x86_pci_read_config32(dev, TOLUD); 545 546 /* Top of Memory - does not account for any UMA */ 547 tom = x86_pci_read_config32(dev, 0xa4); 548 tom <<= 32; 549 tom |= x86_pci_read_config32(dev, 0xa0); 550 551 debug("TOUUD %llx TOLUD %08x TOM %llx\n", touud, tolud, tom); 552 553 /* ME UMA needs excluding if total memory <4GB */ 554 me_base = x86_pci_read_config32(dev, 0x74); 555 me_base <<= 32; 556 me_base |= x86_pci_read_config32(dev, 0x70); 557 558 debug("MEBASE %llx\n", me_base); 559 560 /* TODO: Get rid of all this shifting by 10 bits */ 561 tomk = tolud >> 10; 562 if (me_base == tolud) { 563 /* ME is from MEBASE-TOM */ 564 uma_size = (tom - me_base) >> 10; 565 /* Increment TOLUD to account for ME as RAM */ 566 tolud += uma_size << 10; 567 /* UMA starts at old TOLUD */ 568 uma_memory_base = tomk * 1024ULL; 569 uma_memory_size = uma_size * 1024ULL; 570 debug("ME UMA base %llx size %uM\n", me_base, uma_size >> 10); 571 } 572 573 /* Graphics memory comes next */ 574 ggc = x86_pci_read_config16(dev, GGC); 575 if (!(ggc & 2)) { 576 debug("IGD decoded, subtracting "); 577 578 /* Graphics memory */ 579 uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL; 580 debug("%uM UMA", uma_size >> 10); 581 tomk -= uma_size; 582 uma_memory_base = tomk * 1024ULL; 583 uma_memory_size += uma_size * 1024ULL; 584 585 /* GTT Graphics Stolen Memory Size (GGMS) */ 586 uma_size = ((ggc >> 8) & 0x3) * 1024ULL; 587 tomk -= uma_size; 588 uma_memory_base = tomk * 1024ULL; 589 uma_memory_size += uma_size * 1024ULL; 590 debug(" and %uM GTT\n", uma_size >> 10); 591 } 592 593 /* Calculate TSEG size from its base which must be below GTT */ 594 tseg_base = x86_pci_read_config32(dev, 0xb8); 595 uma_size = (uma_memory_base - tseg_base) >> 10; 596 tomk -= uma_size; 597 uma_memory_base = tomk * 1024ULL; 598 uma_memory_size += uma_size * 1024ULL; 599 debug("TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10); 600 601 debug("Available memory below 4GB: %lluM\n", tomk >> 10); 602 603 /* Report the memory regions */ 604 add_memory_area(info, 1 << 20, 2 << 28); 605 add_memory_area(info, (2 << 28) + (2 << 20), 4 << 28); 606 add_memory_area(info, (4 << 28) + (2 << 20), tseg_base); 607 add_memory_area(info, 1ULL << 32, touud); 608 609 /* Add MTRRs for memory */ 610 mtrr_add_request(MTRR_TYPE_WRBACK, 0, 2ULL << 30); 611 mtrr_add_request(MTRR_TYPE_WRBACK, 2ULL << 30, 512 << 20); 612 mtrr_add_request(MTRR_TYPE_WRBACK, 0xaULL << 28, 256 << 20); 613 mtrr_add_request(MTRR_TYPE_UNCACHEABLE, tseg_base, 16 << 20); 614 mtrr_add_request(MTRR_TYPE_UNCACHEABLE, tseg_base + (16 << 20), 615 32 << 20); 616 617 /* 618 * If >= 4GB installed then memory from TOLUD to 4GB 619 * is remapped above TOM, TOUUD will account for both 620 */ 621 if (touud > (1ULL << 32ULL)) { 622 debug("Available memory above 4GB: %lluM\n", 623 (touud >> 20) - 4096); 624 } 625 626 return 0; 627 } 628 629 static void rcba_config(void) 630 { 631 /* 632 * GFX INTA -> PIRQA (MSI) 633 * D28IP_P3IP WLAN INTA -> PIRQB 634 * D29IP_E1P EHCI1 INTA -> PIRQD 635 * D26IP_E2P EHCI2 INTA -> PIRQF 636 * D31IP_SIP SATA INTA -> PIRQF (MSI) 637 * D31IP_SMIP SMBUS INTB -> PIRQH 638 * D31IP_TTIP THRT INTC -> PIRQA 639 * D27IP_ZIP HDA INTA -> PIRQA (MSI) 640 * 641 * TRACKPAD -> PIRQE (Edge Triggered) 642 * TOUCHSCREEN -> PIRQG (Edge Triggered) 643 */ 644 645 /* Device interrupt pin register (board specific) */ 646 writel((INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | 647 (INTB << D31IP_SMIP) | (INTA << D31IP_SIP), RCB_REG(D31IP)); 648 writel(NOINT << D30IP_PIP, RCB_REG(D30IP)); 649 writel(INTA << D29IP_E1P, RCB_REG(D29IP)); 650 writel(INTA << D28IP_P3IP, RCB_REG(D28IP)); 651 writel(INTA << D27IP_ZIP, RCB_REG(D27IP)); 652 writel(INTA << D26IP_E2P, RCB_REG(D26IP)); 653 writel(NOINT << D25IP_LIP, RCB_REG(D25IP)); 654 writel(NOINT << D22IP_MEI1IP, RCB_REG(D22IP)); 655 656 /* Device interrupt route registers */ 657 writel(DIR_ROUTE(PIRQB, PIRQH, PIRQA, PIRQC), RCB_REG(D31IR)); 658 writel(DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG), RCB_REG(D29IR)); 659 writel(DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE), RCB_REG(D28IR)); 660 writel(DIR_ROUTE(PIRQA, PIRQH, PIRQA, PIRQB), RCB_REG(D27IR)); 661 writel(DIR_ROUTE(PIRQF, PIRQE, PIRQG, PIRQH), RCB_REG(D26IR)); 662 writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D25IR)); 663 writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D22IR)); 664 665 /* Enable IOAPIC (generic) */ 666 writew(0x0100, RCB_REG(OIC)); 667 /* PCH BWG says to read back the IOAPIC enable register */ 668 (void)readw(RCB_REG(OIC)); 669 670 /* Disable unused devices (board specific) */ 671 setbits_le32(RCB_REG(FD), PCH_DISABLE_ALWAYS); 672 } 673 674 int dram_init(void) 675 { 676 struct pei_data pei_data __aligned(8) = { 677 .pei_version = PEI_VERSION, 678 .mchbar = DEFAULT_MCHBAR, 679 .dmibar = DEFAULT_DMIBAR, 680 .epbar = DEFAULT_EPBAR, 681 .pciexbar = CONFIG_PCIE_ECAM_BASE, 682 .smbusbar = SMBUS_IO_BASE, 683 .wdbbar = 0x4000000, 684 .wdbsize = 0x1000, 685 .hpet_address = CONFIG_HPET_ADDRESS, 686 .rcba = DEFAULT_RCBABASE, 687 .pmbase = DEFAULT_PMBASE, 688 .gpiobase = DEFAULT_GPIOBASE, 689 .thermalbase = 0xfed08000, 690 .system_type = 0, /* 0 Mobile, 1 Desktop/Server */ 691 .tseg_size = CONFIG_SMM_TSEG_SIZE, 692 .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, 693 .ec_present = 1, 694 .ddr3lv_support = 1, 695 /* 696 * 0 = leave channel enabled 697 * 1 = disable dimm 0 on channel 698 * 2 = disable dimm 1 on channel 699 * 3 = disable dimm 0+1 on channel 700 */ 701 .dimm_channel0_disabled = 2, 702 .dimm_channel1_disabled = 2, 703 .max_ddr3_freq = 1600, 704 .usb_port_config = { 705 /* 706 * Empty and onboard Ports 0-7, set to un-used pin 707 * OC3 708 */ 709 { 0, 3, 0x0000 }, /* P0= Empty */ 710 { 1, 0, 0x0040 }, /* P1= Left USB 1 (OC0) */ 711 { 1, 1, 0x0040 }, /* P2= Left USB 2 (OC1) */ 712 { 1, 3, 0x0040 }, /* P3= SDCARD (no OC) */ 713 { 0, 3, 0x0000 }, /* P4= Empty */ 714 { 1, 3, 0x0040 }, /* P5= WWAN (no OC) */ 715 { 0, 3, 0x0000 }, /* P6= Empty */ 716 { 0, 3, 0x0000 }, /* P7= Empty */ 717 /* 718 * Empty and onboard Ports 8-13, set to un-used pin 719 * OC4 720 */ 721 { 1, 4, 0x0040 }, /* P8= Camera (no OC) */ 722 { 1, 4, 0x0040 }, /* P9= Bluetooth (no OC) */ 723 { 0, 4, 0x0000 }, /* P10= Empty */ 724 { 0, 4, 0x0000 }, /* P11= Empty */ 725 { 0, 4, 0x0000 }, /* P12= Empty */ 726 { 0, 4, 0x0000 }, /* P13= Empty */ 727 }, 728 }; 729 pci_dev_t dev = PCI_BDF(0, 0, 0); 730 int ret; 731 732 debug("Boot mode %d\n", gd->arch.pei_boot_mode); 733 debug("mrc_input %p\n", pei_data.mrc_input); 734 pei_data.boot_mode = gd->arch.pei_boot_mode; 735 ret = copy_spd(&pei_data); 736 if (!ret) 737 ret = sdram_initialise(&pei_data); 738 if (ret) 739 return ret; 740 741 rcba_config(); 742 quick_ram_check(); 743 744 writew(0xCAFE, MCHBAR_REG(SSKPD)); 745 746 post_code(POST_DRAM); 747 748 ret = sdram_find(dev); 749 if (ret) 750 return ret; 751 752 gd->ram_size = gd->arch.meminfo.total_32bit_memory; 753 754 return 0; 755 } 756