1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * (C) Copyright 2008 4 * Graeme Russ, graeme.russ@gmail.com. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/u-boot-x86.h> 11 #include <flash.h> 12 #include <netdev.h> 13 #include <ns16550.h> 14 #include <asm/msr.h> 15 #include <asm/cache.h> 16 #include <asm/io.h> 17 #include <asm/arch-coreboot/tables.h> 18 #include <asm/arch-coreboot/sysinfo.h> 19 #include <asm/arch/timestamp.h> 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 int arch_cpu_init(void) 24 { 25 int ret = get_coreboot_info(&lib_sysinfo); 26 if (ret != 0) { 27 printf("Failed to parse coreboot tables.\n"); 28 return ret; 29 } 30 31 timestamp_init(); 32 33 return x86_cpu_init_f(); 34 } 35 36 int board_early_init_f(void) 37 { 38 return 0; 39 } 40 41 int board_early_init_r(void) 42 { 43 /* CPU Speed to 100MHz */ 44 gd->cpu_clk = 100000000; 45 46 /* Crystal is 33.000MHz */ 47 gd->bus_clk = 33000000; 48 49 return 0; 50 } 51 52 void show_boot_progress(int val) 53 { 54 #if MIN_PORT80_KCLOCKS_DELAY 55 /* 56 * Scale the time counter reading to avoid using 64 bit arithmetics. 57 * Can't use get_timer() here becuase it could be not yet 58 * initialized or even implemented. 59 */ 60 if (!gd->arch.tsc_prev) { 61 gd->arch.tsc_base_kclocks = rdtsc() / 1000; 62 gd->arch.tsc_prev = 0; 63 } else { 64 uint32_t now; 65 66 do { 67 now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks; 68 } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY)); 69 gd->arch.tsc_prev = now; 70 } 71 #endif 72 outb(val, 0x80); 73 } 74 75 int last_stage_init(void) 76 { 77 if (gd->flags & GD_FLG_COLD_BOOT) 78 timestamp_add_to_bootstage(); 79 80 return 0; 81 } 82 83 #ifndef CONFIG_SYS_NO_FLASH 84 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) 85 { 86 return 0; 87 } 88 #endif 89 90 int board_eth_init(bd_t *bis) 91 { 92 return pci_eth_init(bis); 93 } 94 95 #define MTRR_TYPE_WP 5 96 #define MTRRcap_MSR 0xfe 97 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) 98 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) 99 100 void board_final_cleanup(void) 101 { 102 /* Un-cache the ROM so the kernel has one 103 * more MTRR available. 104 * 105 * Coreboot should have assigned this to the 106 * top available variable MTRR. 107 */ 108 u8 top_mtrr = (native_read_msr(MTRRcap_MSR) & 0xff) - 1; 109 u8 top_type = native_read_msr(MTRRphysBase_MSR(top_mtrr)) & 0xff; 110 111 /* Make sure this MTRR is the correct Write-Protected type */ 112 if (top_type == MTRR_TYPE_WP) { 113 disable_caches(); 114 wrmsrl(MTRRphysBase_MSR(top_mtrr), 0); 115 wrmsrl(MTRRphysMask_MSR(top_mtrr), 0); 116 enable_caches(); 117 } 118 119 /* Issue SMI to Coreboot to lock down ME and registers */ 120 printf("Finalizing Coreboot\n"); 121 outb(0xcb, 0xb2); 122 } 123 124 void panic_puts(const char *str) 125 { 126 NS16550_t port = (NS16550_t)0x3f8; 127 128 NS16550_init(port, 1); 129 while (*str) 130 NS16550_putc(port, *str++); 131 } 132