1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * (C) Copyright 2008 4 * Graeme Russ, graeme.russ@gmail.com. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/u-boot-x86.h> 11 #include <flash.h> 12 #include <netdev.h> 13 #include <ns16550.h> 14 #include <asm/msr.h> 15 #include <asm/cache.h> 16 #include <asm/cpu.h> 17 #include <asm/io.h> 18 #include <asm/post.h> 19 #include <asm/arch/tables.h> 20 #include <asm/arch/sysinfo.h> 21 #include <asm/arch/timestamp.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 int arch_cpu_init(void) 26 { 27 int ret = get_coreboot_info(&lib_sysinfo); 28 if (ret != 0) { 29 printf("Failed to parse coreboot tables.\n"); 30 return ret; 31 } 32 33 timestamp_init(); 34 35 return x86_cpu_init_f(); 36 } 37 38 int board_early_init_f(void) 39 { 40 return 0; 41 } 42 43 int board_early_init_r(void) 44 { 45 /* CPU Speed to 100MHz */ 46 gd->cpu_clk = 100000000; 47 48 /* Crystal is 33.000MHz */ 49 gd->bus_clk = 33000000; 50 51 return 0; 52 } 53 54 void show_boot_progress(int val) 55 { 56 #if MIN_PORT80_KCLOCKS_DELAY 57 /* 58 * Scale the time counter reading to avoid using 64 bit arithmetics. 59 * Can't use get_timer() here becuase it could be not yet 60 * initialized or even implemented. 61 */ 62 if (!gd->arch.tsc_prev) { 63 gd->arch.tsc_base_kclocks = rdtsc() / 1000; 64 gd->arch.tsc_prev = 0; 65 } else { 66 uint32_t now; 67 68 do { 69 now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks; 70 } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY)); 71 gd->arch.tsc_prev = now; 72 } 73 #endif 74 outb(val, POST_PORT); 75 } 76 77 int print_cpuinfo(void) 78 { 79 return default_print_cpuinfo(); 80 } 81 82 int last_stage_init(void) 83 { 84 if (gd->flags & GD_FLG_COLD_BOOT) 85 timestamp_add_to_bootstage(); 86 87 return 0; 88 } 89 90 #ifndef CONFIG_SYS_NO_FLASH 91 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) 92 { 93 return 0; 94 } 95 #endif 96 97 int board_eth_init(bd_t *bis) 98 { 99 return pci_eth_init(bis); 100 } 101 102 #define MTRR_TYPE_WP 5 103 #define MTRRcap_MSR 0xfe 104 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) 105 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) 106 107 void board_final_cleanup(void) 108 { 109 /* Un-cache the ROM so the kernel has one 110 * more MTRR available. 111 * 112 * Coreboot should have assigned this to the 113 * top available variable MTRR. 114 */ 115 u8 top_mtrr = (native_read_msr(MTRRcap_MSR) & 0xff) - 1; 116 u8 top_type = native_read_msr(MTRRphysBase_MSR(top_mtrr)) & 0xff; 117 118 /* Make sure this MTRR is the correct Write-Protected type */ 119 if (top_type == MTRR_TYPE_WP) { 120 disable_caches(); 121 wrmsrl(MTRRphysBase_MSR(top_mtrr), 0); 122 wrmsrl(MTRRphysMask_MSR(top_mtrr), 0); 123 enable_caches(); 124 } 125 126 /* Issue SMI to Coreboot to lock down ME and registers */ 127 printf("Finalizing Coreboot\n"); 128 outb(0xcb, 0xb2); 129 } 130 131 void panic_puts(const char *str) 132 { 133 NS16550_t port = (NS16550_t)0x3f8; 134 135 NS16550_init(port, 1); 136 while (*str) 137 NS16550_putc(port, *str++); 138 } 139