1*a47a12beSStefan Roese /* 2*a47a12beSStefan Roese * Copyright 2008-2009 Freescale Semiconductor, Inc. 3*a47a12beSStefan Roese * 4*a47a12beSStefan Roese * This program is free software; you can redistribute it and/or 5*a47a12beSStefan Roese * modify it under the terms of the GNU General Public License 6*a47a12beSStefan Roese * Version 2 as published by the Free Software Foundation. 7*a47a12beSStefan Roese */ 8*a47a12beSStefan Roese 9*a47a12beSStefan Roese #ifndef _FSL_LAW_H_ 10*a47a12beSStefan Roese #define _FSL_LAW_H_ 11*a47a12beSStefan Roese 12*a47a12beSStefan Roese #include <asm/io.h> 13*a47a12beSStefan Roese 14*a47a12beSStefan Roese #define LAW_EN 0x80000000 15*a47a12beSStefan Roese 16*a47a12beSStefan Roese #define SET_LAW_ENTRY(idx, a, sz, trgt) \ 17*a47a12beSStefan Roese { .index = idx, .addr = a, .size = sz, .trgt_id = trgt } 18*a47a12beSStefan Roese 19*a47a12beSStefan Roese #define SET_LAW(a, sz, trgt) \ 20*a47a12beSStefan Roese { .index = -1, .addr = a, .size = sz, .trgt_id = trgt } 21*a47a12beSStefan Roese 22*a47a12beSStefan Roese enum law_size { 23*a47a12beSStefan Roese LAW_SIZE_4K = 0xb, 24*a47a12beSStefan Roese LAW_SIZE_8K, 25*a47a12beSStefan Roese LAW_SIZE_16K, 26*a47a12beSStefan Roese LAW_SIZE_32K, 27*a47a12beSStefan Roese LAW_SIZE_64K, 28*a47a12beSStefan Roese LAW_SIZE_128K, 29*a47a12beSStefan Roese LAW_SIZE_256K, 30*a47a12beSStefan Roese LAW_SIZE_512K, 31*a47a12beSStefan Roese LAW_SIZE_1M, 32*a47a12beSStefan Roese LAW_SIZE_2M, 33*a47a12beSStefan Roese LAW_SIZE_4M, 34*a47a12beSStefan Roese LAW_SIZE_8M, 35*a47a12beSStefan Roese LAW_SIZE_16M, 36*a47a12beSStefan Roese LAW_SIZE_32M, 37*a47a12beSStefan Roese LAW_SIZE_64M, 38*a47a12beSStefan Roese LAW_SIZE_128M, 39*a47a12beSStefan Roese LAW_SIZE_256M, 40*a47a12beSStefan Roese LAW_SIZE_512M, 41*a47a12beSStefan Roese LAW_SIZE_1G, 42*a47a12beSStefan Roese LAW_SIZE_2G, 43*a47a12beSStefan Roese LAW_SIZE_4G, 44*a47a12beSStefan Roese LAW_SIZE_8G, 45*a47a12beSStefan Roese LAW_SIZE_16G, 46*a47a12beSStefan Roese LAW_SIZE_32G, 47*a47a12beSStefan Roese }; 48*a47a12beSStefan Roese 49*a47a12beSStefan Roese #define law_size_bits(sz) (__ilog2_u64(sz) - 1) 50*a47a12beSStefan Roese 51*a47a12beSStefan Roese #ifdef CONFIG_FSL_CORENET 52*a47a12beSStefan Roese enum law_trgt_if { 53*a47a12beSStefan Roese LAW_TRGT_IF_PCIE_1 = 0x00, 54*a47a12beSStefan Roese LAW_TRGT_IF_PCIE_2 = 0x01, 55*a47a12beSStefan Roese LAW_TRGT_IF_PCIE_3 = 0x02, 56*a47a12beSStefan Roese LAW_TRGT_IF_RIO_1 = 0x08, 57*a47a12beSStefan Roese LAW_TRGT_IF_RIO_2 = 0x09, 58*a47a12beSStefan Roese 59*a47a12beSStefan Roese LAW_TRGT_IF_DDR_1 = 0x10, 60*a47a12beSStefan Roese LAW_TRGT_IF_DDR_2 = 0x11, /* 2nd controller */ 61*a47a12beSStefan Roese LAW_TRGT_IF_DDR_INTRLV = 0x14, 62*a47a12beSStefan Roese 63*a47a12beSStefan Roese LAW_TRGT_IF_BMAN = 0x18, 64*a47a12beSStefan Roese LAW_TRGT_IF_DCSR = 0x1d, 65*a47a12beSStefan Roese LAW_TRGT_IF_LBC = 0x1f, 66*a47a12beSStefan Roese LAW_TRGT_IF_QMAN = 0x3c, 67*a47a12beSStefan Roese }; 68*a47a12beSStefan Roese #define LAW_TRGT_IF_DDR LAW_TRGT_IF_DDR_1 69*a47a12beSStefan Roese #else 70*a47a12beSStefan Roese enum law_trgt_if { 71*a47a12beSStefan Roese LAW_TRGT_IF_PCI = 0x00, 72*a47a12beSStefan Roese LAW_TRGT_IF_PCI_2 = 0x01, 73*a47a12beSStefan Roese #ifndef CONFIG_MPC8641 74*a47a12beSStefan Roese LAW_TRGT_IF_PCIE_1 = 0x02, 75*a47a12beSStefan Roese #endif 76*a47a12beSStefan Roese #if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020) 77*a47a12beSStefan Roese LAW_TRGT_IF_PCIE_3 = 0x03, 78*a47a12beSStefan Roese #endif 79*a47a12beSStefan Roese LAW_TRGT_IF_LBC = 0x04, 80*a47a12beSStefan Roese LAW_TRGT_IF_CCSR = 0x08, 81*a47a12beSStefan Roese LAW_TRGT_IF_DDR_INTRLV = 0x0b, 82*a47a12beSStefan Roese LAW_TRGT_IF_RIO = 0x0c, 83*a47a12beSStefan Roese LAW_TRGT_IF_RIO_2 = 0x0d, 84*a47a12beSStefan Roese LAW_TRGT_IF_DDR = 0x0f, 85*a47a12beSStefan Roese LAW_TRGT_IF_DDR_2 = 0x16, /* 2nd controller */ 86*a47a12beSStefan Roese }; 87*a47a12beSStefan Roese #define LAW_TRGT_IF_DDR_1 LAW_TRGT_IF_DDR 88*a47a12beSStefan Roese #define LAW_TRGT_IF_PCI_1 LAW_TRGT_IF_PCI 89*a47a12beSStefan Roese #define LAW_TRGT_IF_PCIX LAW_TRGT_IF_PCI 90*a47a12beSStefan Roese #define LAW_TRGT_IF_PCIE_2 LAW_TRGT_IF_PCI_2 91*a47a12beSStefan Roese 92*a47a12beSStefan Roese #ifdef CONFIG_MPC8641 93*a47a12beSStefan Roese #define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI 94*a47a12beSStefan Roese #endif 95*a47a12beSStefan Roese 96*a47a12beSStefan Roese #if defined(CONFIG_MPC8572) || defined(CONFIG_P2020) 97*a47a12beSStefan Roese #define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI 98*a47a12beSStefan Roese #endif 99*a47a12beSStefan Roese #endif /* CONFIG_FSL_CORENET */ 100*a47a12beSStefan Roese 101*a47a12beSStefan Roese struct law_entry { 102*a47a12beSStefan Roese int index; 103*a47a12beSStefan Roese phys_addr_t addr; 104*a47a12beSStefan Roese enum law_size size; 105*a47a12beSStefan Roese enum law_trgt_if trgt_id; 106*a47a12beSStefan Roese }; 107*a47a12beSStefan Roese 108*a47a12beSStefan Roese extern void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id); 109*a47a12beSStefan Roese extern int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id); 110*a47a12beSStefan Roese extern int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id); 111*a47a12beSStefan Roese extern int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id); 112*a47a12beSStefan Roese extern struct law_entry find_law(phys_addr_t addr); 113*a47a12beSStefan Roese extern void disable_law(u8 idx); 114*a47a12beSStefan Roese extern void init_laws(void); 115*a47a12beSStefan Roese extern void print_laws(void); 116*a47a12beSStefan Roese 117*a47a12beSStefan Roese /* define in board code */ 118*a47a12beSStefan Roese extern struct law_entry law_table[]; 119*a47a12beSStefan Roese extern int num_law_entries; 120*a47a12beSStefan Roese #endif 121