Merge git://git.denx.de/u-boot-mpc85xx

powerpc: MPC8641: Remove macro CONFIG_MPC8641

Replace CONFIG_MPC8641 with ARCH_MPC8641 in Kconfig and clean up
existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>

powerpc: P2020: Remove macro CONFIG_P2020

Replace CONFIG_P2020 with ARCH_P2020 in Kconfig and clean up
existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>

powerpc: MPC8572: Remove macro CONFIG_MPC8572

Replace CONFIG_MPC8572 with ARCH_MPC8572 in Kconfig and clean up existing
macros.

Signed-off-by: York Sun <york.sun@nxp.com>

powerpc: BSC9131/2: Move CONFIG_BSC9131/2 to Kconfig options

Replace CONFIG_BSC9131, CONFIG_BSC9132 with ARCH_BSC9131, ARCH_BSC9132
Kconfig options.

Also drop #ifdef in BSC9131RDB.h since it is red

powerpc: BSC9131/2: Move CONFIG_BSC9131/2 to Kconfig options

Replace CONFIG_BSC9131, CONFIG_BSC9132 with ARCH_BSC9131, ARCH_BSC9132
Kconfig options.

Also drop #ifdef in BSC9131RDB.h since it is redundant.

Signed-off-by: York Sun <york.sun@nxp.com>

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Add more SPDX-License-Identifier tags

In a number of places we had wordings of the GPL (or LGPL in a few
cases) license text that were split in such a way that it wasn't caught
previously. Convert

Add more SPDX-License-Identifier tags

In a number of places we had wordings of the GPL (or LGPL in a few
cases) license text that were split in such a way that it wasn't caught
previously. Convert all of these to the correct SPDX-License-Identifier
tag.

Signed-off-by: Tom Rini <trini@konsulko.com>

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Merge git://git.denx.de/u-boot

powerpc: Remove __ilog2_u64 and ffs4 from bitops

Remove __ilog2_u64 and ffs4 from powerpc bitops to align with the
kernel implementation.

Use the generic __ffs64 instead of a custom powerpc impleme

powerpc: Remove __ilog2_u64 and ffs4 from bitops

Remove __ilog2_u64 and ffs4 from powerpc bitops to align with the
kernel implementation.

Use the generic __ffs64 instead of a custom powerpc implementation.

Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>

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Merge branch 'master' of git://git.denx.de/u-boot

Signed-off-by: Stefano Babic <sbabic@denx.de>

Conflicts:
boards.cfg

Merge branch 'u-boot/master' into 'u-boot-arm/master'

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

powerpc/mpc85xx: Add workaround to enable TDM on T1040

This is a workaround for 32 bit hardware limitation of TDM.
T1040 has 36 bit physical addressing, TDM DMAC register
are 32 bit wide but need to

powerpc/mpc85xx: Add workaround to enable TDM on T1040

This is a workaround for 32 bit hardware limitation of TDM.
T1040 has 36 bit physical addressing, TDM DMAC register
are 32 bit wide but need to store address of CCSR space
which lies beyond 32 bit address range. This workaround
creats a LAW to enable access of TDM DMA to CCSR by
mapping CCSR to overlap with DDR.
A hole of 16M is created in memory using device tree. This
workaround law is set only if "tdm" is defined in hwconfig.
Also disable POST tests and add LIODN for TDM

Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

powerpc/85xx: Add C29x SoC support

The Freescale C29x family is a high performance crypto co-processor.
It combines a single e500v2 core with necessary SEC engine. There're
three SoC types(C291, C29

powerpc/85xx: Add C29x SoC support

The Freescale C29x family is a high performance crypto co-processor.
It combines a single e500v2 core with necessary SEC engine. There're
three SoC types(C291, C292, C293) with the following features:

- 512K L2 Cache/SRAM and 512 KB platform SRAM
- DDR3/DDR3L 32bit DDR controller
- One PCI express (x1, x2, x4) Gen 2.0 Controller
- Trust Architecture 2.0
- SEC6.0 engine

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Po Liu <Po.Liu@freescale.com>

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board/bsc9132qds: Add DSP side tlb and laws

BSC9132QDS is a Freescale Reference Design Board for BSC9132 SoC which is a
integrated device that contains two powerpc e500v2 cores and two DSP
starcores

board/bsc9132qds: Add DSP side tlb and laws

BSC9132QDS is a Freescale Reference Design Board for BSC9132 SoC which is a
integrated device that contains two powerpc e500v2 cores and two DSP
starcores.

To support DSP starcore
-Creating LAW and TLB for DSP-CCSR space.
-Creating LAW for DSP-core subsystem M2 and M3 memory
-Creating LAW for 1GB DDR which is connected exclusively to DSP-cores

Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>

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board/bsc9131rdb: Add DSP side tlb and laws

BSC9131RDB is a Freescale Reference Design Board for
BSC9131 SoC which is a integrated device that contains
one powerpc e500v2 core and one DSP starcore.

board/bsc9131rdb: Add DSP side tlb and laws

BSC9131RDB is a Freescale Reference Design Board for
BSC9131 SoC which is a integrated device that contains
one powerpc e500v2 core and one DSP starcore.

To support DSP starcore
-Creating LAW and TLB for DSP-CCSR space.
-Creating LAW for DSP-core subsystem M2 memory

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

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Merge branch 'u-boot/master' into 'u-boot-arm/master'

Conflicts:
common/cmd_fpga.c
drivers/usb/host/ohci-at91.c

powerpc/b4860qds: Add LAW Target ID and Create LAW entry for Maple

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

Merge remote-tracking branch 'u-boot/master'

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

powerpc/mpc8xxx: Enable 3-way and 4-way DDR interleaving

Restructure DDR interleaving option to support 3 and 4 DDR controllers
for 2-, 3- and 4-way interleaving.

Signed-off-by: York Sun <yorksun@f

powerpc/mpc8xxx: Enable 3-way and 4-way DDR interleaving

Restructure DDR interleaving option to support 3 and 4 DDR controllers
for 2-, 3- and 4-way interleaving.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

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powerpc/mpc85xx: Add IFC LAW target ID for FSL High-End SoC

Freescale's High-End SoC are going to have Integrated Flash controller
(IFC)'s support.

So add IFC LAW target ID support for High-End SoC

powerpc/mpc85xx: Add IFC LAW target ID for FSL High-End SoC

Freescale's High-End SoC are going to have Integrated Flash controller
(IFC)'s support.

So add IFC LAW target ID support for High-End SoC or corenet SoC.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

Conflicts:
drivers/usb/host/ehci-pci.c

Signed-off-by: Wolfgang Denk <wd@denx.de>

powerpc/85xx: Add support for Freescale P1023/P1017 Processors

Add P1023 (dual core) & P1017 (single core) specific information:
* SERDES Table
* Added P1023/P1017 to cpu_type_list and SVR list
(f

powerpc/85xx: Add support for Freescale P1023/P1017 Processors

Add P1023 (dual core) & P1017 (single core) specific information:
* SERDES Table
* Added P1023/P1017 to cpu_type_list and SVR list
(fixed issue with P1013 not being sorted correctly).
* Added P1023/P1027 to config_mpc85xx.h
* Added new LAW type introduced on P1023/P1017
* Updated a few immap register/defines unique to P1023/P1017

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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powerpc/85xx: Add support for Integrated Flash Controller (IFC)

The Integrated Flash Controller (IFC) is used to access the external
NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four

powerpc/85xx: Add support for Integrated Flash Controller (IFC)

The Integrated Flash Controller (IFC) is used to access the external
NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip
selects are provided in IFC so that maximum of four Flash devices can be
hooked, but only one can be accessed at a given time.

Features supported by IFC are,
- Functional muxing of pins between NAND, NOR and GPCM
- Support memory banks of size 64KByte to 4 GBytes
- Write protection capability (only for NAND and NOR)
- Provision of Software Reset
- Flexible Timing programmability for every chip select
- NAND Machine
- x8/ x16 NAND Flash Interface
- SLC and MLC NAND Flash devices support with
configurable
page sizes of upto 4KB
- Internal SRAM of 9KB which is directly mapped and
availble at
boot time for NAND Boot
- Configurable block size
- Boot chip select (CS0) available at system reset
- NOR Machine
- Data bus width of 8/16/32
- Compatible with asynchronous NOR Flash
- Directly memory mapped
- Supports address data multiplexed (ADM) NOR device
- Boot chip select (CS0) available at system reset
- GPCM Machine (NORMAL GPCM Mode)
- Support for x8/16/32 bit device
- Compatible with general purpose addressable device
e.g. SRAM, ROM
- External clock is supported with programmable division
ratio
- GPCM Machine (Generic ASIC Mode)
- Support for x8/16/32 bit device
- Address and Data are shared on I/O bus
- Following Address and Data sequences can be supported
on I/O bus
- 32 bit I/O: AD
- 16 bit I/O: AADD
- 8 bit I/O : AAAADDDD
- Configurable Even/Odd Parity on Address/Data bus
supported

Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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