1a47a12beSStefan Roese /* 29ab87d04SKumar Gala * Copyright 2008-2010 Freescale Semiconductor, Inc. 3a47a12beSStefan Roese * 4a47a12beSStefan Roese * This program is free software; you can redistribute it and/or 5a47a12beSStefan Roese * modify it under the terms of the GNU General Public License 6a47a12beSStefan Roese * Version 2 as published by the Free Software Foundation. 7a47a12beSStefan Roese */ 8a47a12beSStefan Roese 9a47a12beSStefan Roese #ifndef _FSL_LAW_H_ 10a47a12beSStefan Roese #define _FSL_LAW_H_ 11a47a12beSStefan Roese 12a47a12beSStefan Roese #include <asm/io.h> 13a47a12beSStefan Roese 14a47a12beSStefan Roese #define LAW_EN 0x80000000 15a47a12beSStefan Roese 16a47a12beSStefan Roese #define SET_LAW_ENTRY(idx, a, sz, trgt) \ 17a47a12beSStefan Roese { .index = idx, .addr = a, .size = sz, .trgt_id = trgt } 18a47a12beSStefan Roese 19a47a12beSStefan Roese #define SET_LAW(a, sz, trgt) \ 20a47a12beSStefan Roese { .index = -1, .addr = a, .size = sz, .trgt_id = trgt } 21a47a12beSStefan Roese 22a47a12beSStefan Roese enum law_size { 23a47a12beSStefan Roese LAW_SIZE_4K = 0xb, 24a47a12beSStefan Roese LAW_SIZE_8K, 25a47a12beSStefan Roese LAW_SIZE_16K, 26a47a12beSStefan Roese LAW_SIZE_32K, 27a47a12beSStefan Roese LAW_SIZE_64K, 28a47a12beSStefan Roese LAW_SIZE_128K, 29a47a12beSStefan Roese LAW_SIZE_256K, 30a47a12beSStefan Roese LAW_SIZE_512K, 31a47a12beSStefan Roese LAW_SIZE_1M, 32a47a12beSStefan Roese LAW_SIZE_2M, 33a47a12beSStefan Roese LAW_SIZE_4M, 34a47a12beSStefan Roese LAW_SIZE_8M, 35a47a12beSStefan Roese LAW_SIZE_16M, 36a47a12beSStefan Roese LAW_SIZE_32M, 37a47a12beSStefan Roese LAW_SIZE_64M, 38a47a12beSStefan Roese LAW_SIZE_128M, 39a47a12beSStefan Roese LAW_SIZE_256M, 40a47a12beSStefan Roese LAW_SIZE_512M, 41a47a12beSStefan Roese LAW_SIZE_1G, 42a47a12beSStefan Roese LAW_SIZE_2G, 43a47a12beSStefan Roese LAW_SIZE_4G, 44a47a12beSStefan Roese LAW_SIZE_8G, 45a47a12beSStefan Roese LAW_SIZE_16G, 46a47a12beSStefan Roese LAW_SIZE_32G, 47a47a12beSStefan Roese }; 48a47a12beSStefan Roese 49a47a12beSStefan Roese #define law_size_bits(sz) (__ilog2_u64(sz) - 1) 50e71755f8SBecky Bruce #define lawar_size(x) (1ULL << ((x & 0x3f) + 1)) 51a47a12beSStefan Roese 52a47a12beSStefan Roese #ifdef CONFIG_FSL_CORENET 53a47a12beSStefan Roese enum law_trgt_if { 54a47a12beSStefan Roese LAW_TRGT_IF_PCIE_1 = 0x00, 55a47a12beSStefan Roese LAW_TRGT_IF_PCIE_2 = 0x01, 56a47a12beSStefan Roese LAW_TRGT_IF_PCIE_3 = 0x02, 579ab87d04SKumar Gala LAW_TRGT_IF_PCIE_4 = 0x03, 58a47a12beSStefan Roese LAW_TRGT_IF_RIO_1 = 0x08, 59a47a12beSStefan Roese LAW_TRGT_IF_RIO_2 = 0x09, 60a47a12beSStefan Roese 61a47a12beSStefan Roese LAW_TRGT_IF_DDR_1 = 0x10, 62a47a12beSStefan Roese LAW_TRGT_IF_DDR_2 = 0x11, /* 2nd controller */ 63a47a12beSStefan Roese LAW_TRGT_IF_DDR_INTRLV = 0x14, 64a47a12beSStefan Roese 65a47a12beSStefan Roese LAW_TRGT_IF_BMAN = 0x18, 66a47a12beSStefan Roese LAW_TRGT_IF_DCSR = 0x1d, 67a47a12beSStefan Roese LAW_TRGT_IF_LBC = 0x1f, 68a47a12beSStefan Roese LAW_TRGT_IF_QMAN = 0x3c, 69a47a12beSStefan Roese }; 70a47a12beSStefan Roese #define LAW_TRGT_IF_DDR LAW_TRGT_IF_DDR_1 71a47a12beSStefan Roese #else 72a47a12beSStefan Roese enum law_trgt_if { 73a47a12beSStefan Roese LAW_TRGT_IF_PCI = 0x00, 74a47a12beSStefan Roese LAW_TRGT_IF_PCI_2 = 0x01, 75a47a12beSStefan Roese #ifndef CONFIG_MPC8641 76a47a12beSStefan Roese LAW_TRGT_IF_PCIE_1 = 0x02, 77a47a12beSStefan Roese #endif 78a47a12beSStefan Roese #if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020) 79a47a12beSStefan Roese LAW_TRGT_IF_PCIE_3 = 0x03, 80a47a12beSStefan Roese #endif 81a47a12beSStefan Roese LAW_TRGT_IF_LBC = 0x04, 82a47a12beSStefan Roese LAW_TRGT_IF_CCSR = 0x08, 83a47a12beSStefan Roese LAW_TRGT_IF_DDR_INTRLV = 0x0b, 84a47a12beSStefan Roese LAW_TRGT_IF_RIO = 0x0c, 85a47a12beSStefan Roese LAW_TRGT_IF_RIO_2 = 0x0d, 86a47a12beSStefan Roese LAW_TRGT_IF_DDR = 0x0f, 87a47a12beSStefan Roese LAW_TRGT_IF_DDR_2 = 0x16, /* 2nd controller */ 88a47a12beSStefan Roese }; 89a47a12beSStefan Roese #define LAW_TRGT_IF_DDR_1 LAW_TRGT_IF_DDR 90a47a12beSStefan Roese #define LAW_TRGT_IF_PCI_1 LAW_TRGT_IF_PCI 91a47a12beSStefan Roese #define LAW_TRGT_IF_PCIX LAW_TRGT_IF_PCI 92a47a12beSStefan Roese #define LAW_TRGT_IF_PCIE_2 LAW_TRGT_IF_PCI_2 93*a09b9b68SKumar Gala #define LAW_TRGT_IF_RIO_1 LAW_TRGT_IF_RIO 94a47a12beSStefan Roese 95a47a12beSStefan Roese #ifdef CONFIG_MPC8641 96a47a12beSStefan Roese #define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI 97a47a12beSStefan Roese #endif 98a47a12beSStefan Roese 99a47a12beSStefan Roese #if defined(CONFIG_MPC8572) || defined(CONFIG_P2020) 100a47a12beSStefan Roese #define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI 101a47a12beSStefan Roese #endif 102a47a12beSStefan Roese #endif /* CONFIG_FSL_CORENET */ 103a47a12beSStefan Roese 104a47a12beSStefan Roese struct law_entry { 105a47a12beSStefan Roese int index; 106a47a12beSStefan Roese phys_addr_t addr; 107a47a12beSStefan Roese enum law_size size; 108a47a12beSStefan Roese enum law_trgt_if trgt_id; 109a47a12beSStefan Roese }; 110a47a12beSStefan Roese 111a47a12beSStefan Roese extern void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id); 112a47a12beSStefan Roese extern int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id); 113a47a12beSStefan Roese extern int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id); 114a47a12beSStefan Roese extern int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id); 115a47a12beSStefan Roese extern struct law_entry find_law(phys_addr_t addr); 116a47a12beSStefan Roese extern void disable_law(u8 idx); 117a47a12beSStefan Roese extern void init_laws(void); 118a47a12beSStefan Roese extern void print_laws(void); 119a47a12beSStefan Roese 120a47a12beSStefan Roese /* define in board code */ 121a47a12beSStefan Roese extern struct law_entry law_table[]; 122a47a12beSStefan Roese extern int num_law_entries; 123a47a12beSStefan Roese #endif 124