1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <linux/compiler.h> 26 #include <asm/processor.h> 27 28 #ifdef CONFIG_SYS_FSL_ERRATUM_A004849 29 /* 30 * This work-around is implemented in PBI, so just check to see if the 31 * work-around was actually applied. To do this, we check for specific data 32 * at specific addresses in DCSR. 33 * 34 * Array offsets[] contains a list of offsets within DCSR. According to the 35 * erratum document, the value at each offset should be 2. 36 */ 37 static void check_erratum_a4849(uint32_t svr) 38 { 39 void __iomem *dcsr = (void *)CONFIG_SYS_DCSRBAR + 0xb0000; 40 unsigned int i; 41 42 #if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041) 43 static const uint8_t offsets[] = { 44 0x50, 0x54, 0x58, 0x90, 0x94, 0x98 45 }; 46 #endif 47 #ifdef CONFIG_PPC_P4080 48 static const uint8_t offsets[] = { 49 0x60, 0x64, 0x68, 0x6c, 0xa0, 0xa4, 0xa8, 0xac 50 }; 51 #endif 52 uint32_t x108; /* The value that should be at offset 0x108 */ 53 54 for (i = 0; i < ARRAY_SIZE(offsets); i++) { 55 if (in_be32(dcsr + offsets[i]) != 2) { 56 printf("Work-around for Erratum A004849 is not enabled\n"); 57 return; 58 } 59 } 60 61 #if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041) 62 x108 = 0x12; 63 #endif 64 65 #ifdef CONFIG_PPC_P4080 66 /* 67 * For P4080, the erratum document says that the value at offset 0x108 68 * should be 0x12 on rev2, or 0x1c on rev3. 69 */ 70 if (SVR_MAJ(svr) == 2) 71 x108 = 0x12; 72 if (SVR_MAJ(svr) == 3) 73 x108 = 0x1c; 74 #endif 75 76 if (in_be32(dcsr + 0x108) != x108) { 77 printf("Work-around for Erratum A004849 is not enabled\n"); 78 return; 79 } 80 81 /* Everything matches, so the erratum work-around was applied */ 82 83 printf("Work-around for Erratum A004849 enabled\n"); 84 } 85 #endif 86 87 static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 88 { 89 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 90 extern int enable_cpu_a011_workaround; 91 #endif 92 __maybe_unused u32 svr = get_svr(); 93 94 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) 95 if (IS_SVR_REV(svr, 1, 0)) { 96 switch (SVR_SOC_VER(svr)) { 97 case SVR_P1013: 98 case SVR_P1022: 99 puts("Work-around for Erratum SATA A001 enabled\n"); 100 } 101 } 102 #endif 103 104 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) 105 puts("Work-around for Erratum SERDES8 enabled\n"); 106 #endif 107 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) 108 puts("Work-around for Erratum SERDES9 enabled\n"); 109 #endif 110 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES_A005) 111 puts("Work-around for Erratum SERDES-A005 enabled\n"); 112 #endif 113 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) 114 if (SVR_MAJ(svr) < 3) 115 puts("Work-around for Erratum CPU22 enabled\n"); 116 #endif 117 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 118 /* 119 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 120 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1 121 * The SVR has been checked by cpu_init_r(). 122 */ 123 if (enable_cpu_a011_workaround) 124 puts("Work-around for Erratum CPU-A011 enabled\n"); 125 #endif 126 #if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999) 127 puts("Work-around for Erratum CPU-A003999 enabled\n"); 128 #endif 129 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_A003474) 130 puts("Work-around for Erratum DDR-A003473 enabled\n"); 131 #endif 132 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) 133 puts("Work-around for DDR MSYNC_IN Erratum enabled\n"); 134 #endif 135 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC111) 136 puts("Work-around for Erratum ESDHC111 enabled\n"); 137 #endif 138 #ifdef CONFIG_SYS_FSL_ERRATUM_A004468 139 puts("Work-around for Erratum A004468 enabled\n"); 140 #endif 141 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135) 142 puts("Work-around for Erratum ESDHC135 enabled\n"); 143 #endif 144 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC13) 145 if (SVR_MAJ(svr) < 3) 146 puts("Work-around for Erratum ESDHC13 enabled\n"); 147 #endif 148 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001) 149 puts("Work-around for Erratum ESDHC-A001 enabled\n"); 150 #endif 151 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 152 puts("Work-around for Erratum CPC-A002 enabled\n"); 153 #endif 154 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 155 puts("Work-around for Erratum CPC-A003 enabled\n"); 156 #endif 157 #ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001 158 puts("Work-around for Erratum ELBC-A001 enabled\n"); 159 #endif 160 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003 161 puts("Work-around for Erratum DDR-A003 enabled\n"); 162 #endif 163 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115 164 puts("Work-around for Erratum DDR115 enabled\n"); 165 #endif 166 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 167 puts("Work-around for Erratum DDR111 enabled\n"); 168 puts("Work-around for Erratum DDR134 enabled\n"); 169 #endif 170 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769 171 puts("Work-around for Erratum IFC-A002769 enabled\n"); 172 #endif 173 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549 174 puts("Work-around for Erratum P1010-A003549 enabled\n"); 175 #endif 176 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 177 puts("Work-around for Erratum IFC A-003399 enabled\n"); 178 #endif 179 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 180 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) 181 puts("Work-around for Erratum NMG DDR120 enabled\n"); 182 #endif 183 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 184 puts("Work-around for Erratum NMG_LBC103 enabled\n"); 185 #endif 186 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 187 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) 188 puts("Work-around for Erratum NMG ETSEC129 enabled\n"); 189 #endif 190 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510 191 puts("Work-around for Erratum A004510 enabled\n"); 192 #endif 193 #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 194 puts("Work-around for Erratum SRIO-A004034 enabled\n"); 195 #endif 196 #ifdef CONFIG_SYS_FSL_ERRATUM_A_004934 197 puts("Work-around for Erratum A004934 enabled\n"); 198 #endif 199 #ifdef CONFIG_SYS_FSL_ERRATUM_A004849 200 /* This work-around is implemented in PBI, so just check for it */ 201 check_erratum_a4849(svr); 202 #endif 203 return 0; 204 } 205 206 U_BOOT_CMD( 207 errata, 1, 0, do_errata, 208 "Report errata workarounds", 209 "" 210 ); 211