1 /* 2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt 8 9 #include <common.h> 10 #include <errno.h> 11 12 #include "../xusb-padctl-common.h" 13 14 #include <asm/arch/clock.h> 15 16 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 17 18 #define XUSB_PADCTL_ELPG_PROGRAM 0x024 19 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 31) 20 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30) 21 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 29) 22 23 static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl) 24 { 25 u32 value; 26 27 if (padctl->enable++ > 0) 28 return 0; 29 30 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 31 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; 32 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 33 34 udelay(100); 35 36 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 37 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; 38 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 39 40 udelay(100); 41 42 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 43 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; 44 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 45 46 return 0; 47 } 48 49 static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl) 50 { 51 u32 value; 52 53 if (padctl->enable == 0) { 54 error("unbalanced enable/disable"); 55 return 0; 56 } 57 58 if (--padctl->enable > 0) 59 return 0; 60 61 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 62 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; 63 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 64 65 udelay(100); 66 67 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 68 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; 69 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 70 71 udelay(100); 72 73 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 74 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; 75 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 76 77 return 0; 78 } 79 80 static int phy_prepare(struct tegra_xusb_phy *phy) 81 { 82 int err; 83 84 err = tegra_xusb_padctl_enable(phy->padctl); 85 if (err < 0) 86 return err; 87 88 reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 0); 89 90 return 0; 91 } 92 93 static int phy_unprepare(struct tegra_xusb_phy *phy) 94 { 95 reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 1); 96 97 return tegra_xusb_padctl_disable(phy->padctl); 98 } 99 100 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360 101 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK (0xff << 20) 102 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(x) (((x) & 0xff) << 20) 103 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK (0x3 << 16) 104 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS (1 << 15) 105 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD (1 << 4) 106 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE (1 << 3) 107 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK (0x3 << 1) 108 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP(x) (((x) & 0x3) << 1) 109 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ (1 << 0) 110 111 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2 0x364 112 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL_MASK (0xffffff << 4) 113 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(x) (((x) & 0xffffff) << 4) 114 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD (1 << 2) 115 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE (1 << 1) 116 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN (1 << 0) 117 118 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4 0x36c 119 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_EN (1 << 15) 120 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK (0x3 << 12) 121 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL(x) (((x) & 0x3) << 12) 122 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLKBUF_EN (1 << 8) 123 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK (0xf << 4) 124 125 #define XUSB_PADCTL_UPHY_PLL_P0_CTL5 0x370 126 #define XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK (0xff << 16) 127 #define XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL(x) (((x) & 0xff) << 16) 128 129 #define XUSB_PADCTL_UPHY_PLL_P0_CTL8 0x37c 130 #define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE (1 << 31) 131 #define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD (1 << 15) 132 #define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN (1 << 13) 133 #define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN (1 << 12) 134 135 #define CLK_RST_XUSBIO_PLL_CFG0 0x51c 136 #define CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE (1 << 24) 137 #define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ (1 << 13) 138 #define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET (1 << 6) 139 #define CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL (1 << 2) 140 #define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0) 141 142 static int pcie_phy_enable(struct tegra_xusb_phy *phy) 143 { 144 struct tegra_xusb_padctl *padctl = phy->padctl; 145 unsigned long start; 146 u32 value; 147 148 debug("> %s(phy=%p)\n", __func__, phy); 149 150 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 151 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL_MASK; 152 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(0x136); 153 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 154 155 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5); 156 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK; 157 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL(0x2a); 158 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5); 159 160 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 161 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD; 162 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 163 164 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 165 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD; 166 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 167 168 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 169 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD; 170 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 171 172 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4); 173 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK; 174 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK; 175 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL(2); 176 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_EN; 177 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4); 178 179 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 180 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK; 181 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK; 182 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(25); 183 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 184 185 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 186 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ; 187 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 188 189 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 190 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK; 191 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 192 193 udelay(1); 194 195 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4); 196 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLKBUF_EN; 197 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4); 198 199 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 200 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN; 201 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 202 203 debug(" waiting for calibration\n"); 204 205 start = get_timer(0); 206 207 while (get_timer(start) < 250) { 208 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 209 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) 210 break; 211 } 212 213 debug(" done\n"); 214 215 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 216 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN; 217 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 218 219 debug(" waiting for calibration to stop\n"); 220 221 start = get_timer(0); 222 223 while (get_timer(start) < 250) { 224 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 225 if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) == 0) 226 break; 227 } 228 229 debug(" done\n"); 230 231 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 232 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE; 233 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 234 235 debug(" waiting for PLL to lock...\n"); 236 start = get_timer(0); 237 238 while (get_timer(start) < 250) { 239 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 240 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS) 241 break; 242 } 243 244 debug(" done\n"); 245 246 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 247 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN; 248 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN; 249 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 250 251 debug(" waiting for register calibration...\n"); 252 start = get_timer(0); 253 254 while (get_timer(start) < 250) { 255 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 256 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) 257 break; 258 } 259 260 debug(" done\n"); 261 262 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 263 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN; 264 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 265 266 debug(" waiting for register calibration to stop...\n"); 267 start = get_timer(0); 268 269 while (get_timer(start) < 250) { 270 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 271 if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) == 0) 272 break; 273 } 274 275 debug(" done\n"); 276 277 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 278 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN; 279 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 280 281 value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); 282 value &= ~CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL; 283 value &= ~CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL; 284 value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET; 285 value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ; 286 writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); 287 288 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 289 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD; 290 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 291 292 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 293 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD; 294 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 295 296 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 297 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD; 298 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 299 300 udelay(1); 301 302 value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); 303 value |= CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE; 304 writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); 305 306 debug("< %s()\n", __func__); 307 return 0; 308 } 309 310 static int pcie_phy_disable(struct tegra_xusb_phy *phy) 311 { 312 return 0; 313 } 314 315 static const struct tegra_xusb_phy_ops pcie_phy_ops = { 316 .prepare = phy_prepare, 317 .enable = pcie_phy_enable, 318 .disable = pcie_phy_disable, 319 .unprepare = phy_unprepare, 320 }; 321 322 static struct tegra_xusb_phy tegra210_phys[] = { 323 { 324 .type = TEGRA_XUSB_PADCTL_PCIE, 325 .ops = &pcie_phy_ops, 326 .padctl = &padctl, 327 }, 328 }; 329 330 static const struct tegra_xusb_padctl_soc tegra210_socdata = { 331 .lanes = NULL, 332 .num_lanes = 0, 333 .functions = NULL, 334 .num_functions = 0, 335 .phys = tegra210_phys, 336 .num_phys = ARRAY_SIZE(tegra210_phys), 337 }; 338 339 void tegra_xusb_padctl_init(const void *fdt) 340 { 341 int count, nodes[1]; 342 343 debug("> %s(fdt=%p)\n", __func__, fdt); 344 345 count = fdtdec_find_aliases_for_id(fdt, "padctl", 346 COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL, 347 nodes, ARRAY_SIZE(nodes)); 348 if (tegra_xusb_process_nodes(fdt, nodes, count, &tegra210_socdata)) 349 return; 350 351 debug("< %s()\n", __func__); 352 } 353