1 /* 2 * (C) Copyright 2015 3 * Kamil Lulko, <kamil.lulko@gmail.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/armv7m.h> 11 #include <asm/arch/stm32.h> 12 13 u32 get_cpu_rev(void) 14 { 15 return 0; 16 } 17 18 int arch_cpu_init(void) 19 { 20 configure_clocks(); 21 22 /* 23 * Configure the memory protection unit (MPU) 24 * 0x00000000 - 0xffffffff: Strong-order, Shareable 25 * 0xC0000000 - 0xC0800000: Normal, Outer and inner Non-cacheable 26 */ 27 28 /* Disable MPU */ 29 writel(0, &V7M_MPU->ctrl); 30 31 writel( 32 0x00000000 /* address */ 33 | 1 << 4 /* VALID */ 34 | 0 << 0 /* REGION */ 35 , &V7M_MPU->rbar 36 ); 37 38 /* Strong-order, Shareable */ 39 /* TEX=000, S=1, C=0, B=0*/ 40 writel( 41 (V7M_MPU_RASR_XN_ENABLE 42 | V7M_MPU_RASR_AP_RW_RW 43 | 0x01 << V7M_MPU_RASR_S_SHIFT 44 | 0x00 << V7M_MPU_RASR_TEX_SHIFT 45 | V7M_MPU_RASR_SIZE_4GB 46 | V7M_MPU_RASR_EN) 47 , &V7M_MPU->rasr 48 ); 49 50 writel( 51 0xC0000000 /* address */ 52 | 1 << 4 /* VALID */ 53 | 1 << 0 /* REGION */ 54 , &V7M_MPU->rbar 55 ); 56 57 /* Normal, Outer and inner Non-cacheable */ 58 /* TEX=001, S=0, C=0, B=0*/ 59 writel( 60 (V7M_MPU_RASR_XN_ENABLE 61 | V7M_MPU_RASR_AP_RW_RW 62 | 0x01 << V7M_MPU_RASR_TEX_SHIFT 63 | V7M_MPU_RASR_SIZE_8MB 64 | V7M_MPU_RASR_EN) 65 , &V7M_MPU->rasr 66 ); 67 68 /* Enable MPU */ 69 writel(V7M_MPU_CTRL_ENABLE | V7M_MPU_CTRL_HFNMIENA, &V7M_MPU->ctrl); 70 71 return 0; 72 } 73 74 void s_init(void) 75 { 76 } 77