| #
747c4c68 |
| 01-Jul-2017 |
Simon Glass <sjg@chromium.org> |
stm32: Correct positioning of declaration
The current code gives a warning:
arch/arm/mach-stm32/stm32f7/soc.c: In function 'arch_cpu_init':
arch/arm/mach-stm32/stm32f7/soc.c:38:2: error: 'for' loop
stm32: Correct positioning of declaration
The current code gives a warning:
arch/arm/mach-stm32/stm32f7/soc.c: In function 'arch_cpu_init':
arch/arm/mach-stm32/stm32f7/soc.c:38:2: error: 'for' loop initial
declarations are only allowed in C99 or C11 mode
for (int i = 0; i < ARRAY_SIZE(stm32_region_config); i++)
^
arch/arm/mach-stm32/stm32f7/soc.c:38:2: note: use option -std=c99,
-std=gnu99, -std=c11 or -std=gnu11 to compile your code
Fix it by moving the declaration to the top of the function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Series-cc trini
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|
| #
624b7101 |
| 03-May-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: configure mpu valid for f7 family
This configuration should be valid for all F7 family devices in general.
Here is the regions info:
- Region0 : 4GB : cacheable & executable.
- Region1
stm32f7: configure mpu valid for f7 family
This configuration should be valid for all F7 family devices in general.
Here is the regions info:
- Region0 : 4GB : cacheable & executable.
- Region1 : 512MB : text area : strogly ordered & executable.
- Region2 : 512MB : peripherals : device memory & non-executable.
- Region3 : 512MB : peripherals : device memory & non-executable.
- Region4 : 512MB : cortexM area: strongly ordered & non-executable.
Higher region number overrides the lower region configuration.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
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|
| #
33b78476 |
| 03-May-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32: use armv7m MPU configuration support
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
|
| #
dc11d83a |
| 27-Mar-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: enable instruction & data cache
It also enables commands for cache enable/disable/status.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.
stm32f7: enable instruction & data cache
It also enables commands for cache enable/disable/status.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
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|
| #
712f99a5 |
| 12-Feb-2017 |
Vikas Manocha <vikas.manocha@st.com> |
clk: stm32f7: add clock driver for stm32f7 family
add basic clock driver support for stm32f7 to enable clocks required by
the peripherals.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Review
clk: stm32f7: add clock driver for stm32f7 family
add basic clock driver support for stm32f7 to enable clocks required by
the peripherals.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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|
| #
25c1b135 |
| 07-Jul-2016 |
Toshifumi NISHINAGA <tnishinaga.dev@gmail.com> |
stm32: Add SDRAM support for stm32f746 discovery board
This patch adds SDRAM support for stm32f746 discovery board.
This patch depends on previous patch.
This patch is based on STM32F4 and emcraft's
stm32: Add SDRAM support for stm32f746 discovery board
This patch adds SDRAM support for stm32f746 discovery board.
This patch depends on previous patch.
This patch is based on STM32F4 and emcraft's[1].
[1]: https://github.com/EmcraftSystems/u-boot
Signed-off-by: Toshifumi NISHINAGA <tnishinaga.dev@gmail.com>
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| #
ba0a3c16 |
| 07-Jul-2016 |
Toshifumi NISHINAGA <tnishinaga.dev@gmail.com> |
stm32: clk: Add 200MHz clock configuration for stm32f746 discovery board
This patch adds 200MHz clock configuration for stm32f746 discovery board.
This patch is based on STM32F4 and emcraft's[1].
[
stm32: clk: Add 200MHz clock configuration for stm32f746 discovery board
This patch adds 200MHz clock configuration for stm32f746 discovery board.
This patch is based on STM32F4 and emcraft's[1].
[1]: https://github.com/EmcraftSystems/u-boot
Signed-off-by: Toshifumi NISHINAGA <tnishinaga.dev@gmail.com>
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