1*ca62d2e1SMarek Vasut /* 2*ca62d2e1SMarek Vasut * Copyright (C) 2015 Marek Vasut <marex@denx.de> 3*ca62d2e1SMarek Vasut * 4*ca62d2e1SMarek Vasut * SPDX-License-Identifier: GPL-2.0+ 5*ca62d2e1SMarek Vasut */ 6*ca62d2e1SMarek Vasut 7*ca62d2e1SMarek Vasut #include <common.h> 8*ca62d2e1SMarek Vasut #include <asm/arch/clock_manager.h> 9*ca62d2e1SMarek Vasut #include <qts/pll_config.h> 10*ca62d2e1SMarek Vasut 11*ca62d2e1SMarek Vasut #define MAIN_VCO_BASE ( \ 12*ca62d2e1SMarek Vasut (CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \ 13*ca62d2e1SMarek Vasut CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \ 14*ca62d2e1SMarek Vasut (CONFIG_HPS_MAINPLLGRP_VCO_NUMER << \ 15*ca62d2e1SMarek Vasut CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) \ 16*ca62d2e1SMarek Vasut ) 17*ca62d2e1SMarek Vasut 18*ca62d2e1SMarek Vasut #define PERI_VCO_BASE ( \ 19*ca62d2e1SMarek Vasut (CONFIG_HPS_PERPLLGRP_VCO_PSRC << \ 20*ca62d2e1SMarek Vasut CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) | \ 21*ca62d2e1SMarek Vasut (CONFIG_HPS_PERPLLGRP_VCO_DENOM << \ 22*ca62d2e1SMarek Vasut CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) | \ 23*ca62d2e1SMarek Vasut (CONFIG_HPS_PERPLLGRP_VCO_NUMER << \ 24*ca62d2e1SMarek Vasut CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) \ 25*ca62d2e1SMarek Vasut ) 26*ca62d2e1SMarek Vasut 27*ca62d2e1SMarek Vasut #define SDR_VCO_BASE ( \ 28*ca62d2e1SMarek Vasut (CONFIG_HPS_SDRPLLGRP_VCO_SSRC << \ 29*ca62d2e1SMarek Vasut CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) | \ 30*ca62d2e1SMarek Vasut (CONFIG_HPS_SDRPLLGRP_VCO_DENOM << \ 31*ca62d2e1SMarek Vasut CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) | \ 32*ca62d2e1SMarek Vasut (CONFIG_HPS_SDRPLLGRP_VCO_NUMER << \ 33*ca62d2e1SMarek Vasut CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \ 34*ca62d2e1SMarek Vasut ) 35*ca62d2e1SMarek Vasut 36*ca62d2e1SMarek Vasut static const struct cm_config cm_default_cfg = { 37*ca62d2e1SMarek Vasut /* main group */ 38*ca62d2e1SMarek Vasut MAIN_VCO_BASE, 39*ca62d2e1SMarek Vasut (CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT << 40*ca62d2e1SMarek Vasut CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET), 41*ca62d2e1SMarek Vasut (CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT << 42*ca62d2e1SMarek Vasut CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET), 43*ca62d2e1SMarek Vasut (CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT << 44*ca62d2e1SMarek Vasut CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET), 45*ca62d2e1SMarek Vasut (CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT << 46*ca62d2e1SMarek Vasut CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET), 47*ca62d2e1SMarek Vasut (CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT << 48*ca62d2e1SMarek Vasut CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET), 49*ca62d2e1SMarek Vasut (CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT << 50*ca62d2e1SMarek Vasut CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET), 51*ca62d2e1SMarek Vasut (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK << 52*ca62d2e1SMarek Vasut CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) | 53*ca62d2e1SMarek Vasut (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK << 54*ca62d2e1SMarek Vasut CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) | 55*ca62d2e1SMarek Vasut (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK << 56*ca62d2e1SMarek Vasut CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) | 57*ca62d2e1SMarek Vasut (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK << 58*ca62d2e1SMarek Vasut CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET), 59*ca62d2e1SMarek Vasut (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK << 60*ca62d2e1SMarek Vasut CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) | 61*ca62d2e1SMarek Vasut (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK << 62*ca62d2e1SMarek Vasut CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET), 63*ca62d2e1SMarek Vasut (CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK << 64*ca62d2e1SMarek Vasut CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET), 65*ca62d2e1SMarek Vasut (CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP << 66*ca62d2e1SMarek Vasut CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) | 67*ca62d2e1SMarek Vasut (CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP << 68*ca62d2e1SMarek Vasut CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET), 69*ca62d2e1SMarek Vasut 70*ca62d2e1SMarek Vasut /* peripheral group */ 71*ca62d2e1SMarek Vasut PERI_VCO_BASE, 72*ca62d2e1SMarek Vasut (CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT << 73*ca62d2e1SMarek Vasut CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET), 74*ca62d2e1SMarek Vasut (CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT << 75*ca62d2e1SMarek Vasut CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET), 76*ca62d2e1SMarek Vasut (CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT << 77*ca62d2e1SMarek Vasut CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET), 78*ca62d2e1SMarek Vasut (CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT << 79*ca62d2e1SMarek Vasut CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET), 80*ca62d2e1SMarek Vasut (CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT << 81*ca62d2e1SMarek Vasut CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET), 82*ca62d2e1SMarek Vasut (CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT << 83*ca62d2e1SMarek Vasut CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET), 84*ca62d2e1SMarek Vasut (CONFIG_HPS_PERPLLGRP_DIV_USBCLK << 85*ca62d2e1SMarek Vasut CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) | 86*ca62d2e1SMarek Vasut (CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK << 87*ca62d2e1SMarek Vasut CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) | 88*ca62d2e1SMarek Vasut (CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK << 89*ca62d2e1SMarek Vasut CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) | 90*ca62d2e1SMarek Vasut (CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK << 91*ca62d2e1SMarek Vasut CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET), 92*ca62d2e1SMarek Vasut (CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK << 93*ca62d2e1SMarek Vasut CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET), 94*ca62d2e1SMarek Vasut (CONFIG_HPS_PERPLLGRP_SRC_QSPI << 95*ca62d2e1SMarek Vasut CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) | 96*ca62d2e1SMarek Vasut (CONFIG_HPS_PERPLLGRP_SRC_NAND << 97*ca62d2e1SMarek Vasut CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) | 98*ca62d2e1SMarek Vasut (CONFIG_HPS_PERPLLGRP_SRC_SDMMC << 99*ca62d2e1SMarek Vasut CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET), 100*ca62d2e1SMarek Vasut 101*ca62d2e1SMarek Vasut /* sdram pll group */ 102*ca62d2e1SMarek Vasut SDR_VCO_BASE, 103*ca62d2e1SMarek Vasut (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE << 104*ca62d2e1SMarek Vasut CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) | 105*ca62d2e1SMarek Vasut (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT << 106*ca62d2e1SMarek Vasut CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET), 107*ca62d2e1SMarek Vasut (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE << 108*ca62d2e1SMarek Vasut CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) | 109*ca62d2e1SMarek Vasut (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT << 110*ca62d2e1SMarek Vasut CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET), 111*ca62d2e1SMarek Vasut (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE << 112*ca62d2e1SMarek Vasut CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) | 113*ca62d2e1SMarek Vasut (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT << 114*ca62d2e1SMarek Vasut CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET), 115*ca62d2e1SMarek Vasut (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE << 116*ca62d2e1SMarek Vasut CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) | 117*ca62d2e1SMarek Vasut (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT << 118*ca62d2e1SMarek Vasut CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET), 119*ca62d2e1SMarek Vasut }; 120*ca62d2e1SMarek Vasut 121*ca62d2e1SMarek Vasut const struct cm_config * const cm_get_default_config(void) 122*ca62d2e1SMarek Vasut { 123*ca62d2e1SMarek Vasut return &cm_default_cfg; 124*ca62d2e1SMarek Vasut } 125*ca62d2e1SMarek Vasut 126*ca62d2e1SMarek Vasut const unsigned int cm_get_osc_clk_hz(const int osc) 127*ca62d2e1SMarek Vasut { 128*ca62d2e1SMarek Vasut if (osc == 1) 129*ca62d2e1SMarek Vasut return CONFIG_HPS_CLK_OSC1_HZ; 130*ca62d2e1SMarek Vasut else if (osc == 2) 131*ca62d2e1SMarek Vasut return CONFIG_HPS_CLK_OSC2_HZ; 132*ca62d2e1SMarek Vasut else 133*ca62d2e1SMarek Vasut return 0; 134*ca62d2e1SMarek Vasut } 135*ca62d2e1SMarek Vasut 136*ca62d2e1SMarek Vasut const unsigned int cm_get_f2s_per_ref_clk_hz(void) 137*ca62d2e1SMarek Vasut { 138*ca62d2e1SMarek Vasut return CONFIG_HPS_CLK_F2S_PER_REF_HZ; 139*ca62d2e1SMarek Vasut } 140*ca62d2e1SMarek Vasut 141*ca62d2e1SMarek Vasut const unsigned int cm_get_f2s_sdr_ref_clk_hz(void) 142*ca62d2e1SMarek Vasut { 143*ca62d2e1SMarek Vasut return CONFIG_HPS_CLK_F2S_SDR_REF_HZ; 144*ca62d2e1SMarek Vasut } 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