1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2023 Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <spl.h> 8 #include <asm/io.h> 9 #include <asm/arch/cpu.h> 10 #include <asm/arch/hardware.h> 11 #include <asm/arch/ioc_rk3588.h> 12 #include <dt-bindings/clock/rk3588-cru.h> 13 #include <pci.h> 14 #include <asm/arch/rk_atags.h> 15 16 #ifndef CONFIG_SPL_LOAD_FIT_ADDRESS 17 #error "SPL_LOAD_FIT_ADDRESS not defined!" 18 #endif 19 20 #define printep(fmt, ...) \ 21 do { \ 22 printf("RKEP: %d - ", readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x2c) / 24); \ 23 printf(fmt, ##__VA_ARGS__); \ 24 } while (0) 25 26 #ifdef CONFIG_ROCKCHIP_RK3588 27 #define PCIE_SNPS_DBI_BASE 0xf5000000 28 #define PCIE_SNPS_APB_BASE 0xfe150000 29 #define PCIE_SNPS_IATU_BASE 0xa40300000 30 31 #define PCI_RESBAR 0x2e8 32 #elif CONFIG_ROCKCHIP_RK3568 33 #define PCIE_SNPS_DBI_BASE 0xf6000000 34 #define PCIE_SNPS_APB_BASE 0xfe280000 35 #define PCIE_SNPS_IATU_BASE 0x3c0b00000 36 37 #define PCI_RESBAR 0x2b8 38 #else 39 #error "this soc is not support pcie ep!" 40 #endif 41 42 #define RKEP_BAR0_ADDR 0x3c000000 43 #define RKEP_BAR2_ADDR CONFIG_SPL_LOAD_FIT_ADDRESS 44 #define RKEP_BAR0_CMD_ADDR (RKEP_BAR0_ADDR + 0x400) 45 #define RKEP_BOOT_MAGIC 0x524b4550 /* RKEP */ 46 #define RKEP_CMD_LOADER_RUN 0x524b4501 47 48 #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ 49 #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ 50 #define PCI_EXP_LNKCTL2_TLS 0x000f 51 #define PCI_EXP_LNKCAP_SLS 0x0000000f 52 53 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 54 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 55 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 56 57 /* Synopsys-specific PCIe configuration registers */ 58 #define PCIE_PORT_LINK_CONTROL 0x710 59 #define PORT_LINK_MODE_MASK (0x3f << 16) 60 #define PORT_LINK_MODE_1_LANES (0x1 << 16) 61 #define PORT_LINK_MODE_2_LANES (0x3 << 16) 62 #define PORT_LINK_MODE_4_LANES (0x7 << 16) 63 #define PORT_LINK_MODE_8_LANES (0xf << 16) 64 65 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C 66 #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) 67 #define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8) 68 #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) 69 #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8) 70 #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8) 71 #define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8) 72 73 #define PCIE_DIRECT_SPEED_CHANGE (0x1 << 17) 74 75 #define LINK_WAIT_IATU 10000 76 #define PCIE_ATU_ENABLE (0x1 << 31) 77 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30 | 1 << 19) 78 #define PCIE_ATU_UNR_REGION_CTRL1 0x00 79 #define PCIE_ATU_UNR_REGION_CTRL2 0x04 80 #define PCIE_ATU_CPU_ADDR_LOW 0x14 81 #define PCIE_ATU_CPU_ADDR_HIGH 0x18 82 83 /* SRNS: Use Separate refclk(internal clock) instead of from RC */ 84 // #define PCIE_ENABLE_SRNS_PLL_REFCLK 85 86 struct rkpcie_cmd { 87 u32 cmd; 88 u32 size; 89 u32 data[6]; 90 }; 91 92 /* rkep device mode status definition */ 93 #define RKEP_MODE_BOOTROM 1 94 #define RKEP_MODE_LOADER 2 95 #define RKEP_MODE_KERNEL 3 96 97 /* Common status */ 98 #define RKEP_SMODE_INIT 0 99 #define RKEP_SMODE_LNKRDY 1 100 #define RKEP_SMODE_LNKUP 2 101 #define RKEP_SMODE_ERR 0xff 102 /* Firmware download status */ 103 #define RKEP_SMODE_FWDLRDY 0x10 104 #define RKEP_SMODE_FWDLDONE 0x11 105 /* Application status*/ 106 #define RKEP_SMODE_APPRDY 0x20 107 108 struct rkpcie_boot { 109 /* magic: "RKEP" */ 110 u32 magic; 111 u32 version; 112 struct { 113 u16 mode; 114 u16 submode; 115 } devmode; 116 /* Size of ATAGS for cap */ 117 u32 cap_size; 118 struct { 119 u8 cmd; 120 u8 status; 121 /* Error code for current CMD */ 122 u16 opcode; 123 } cmd_status; 124 u32 reserved[2]; 125 /* RK ATAGS, for mem and other info */ 126 struct tag cap; 127 /* offset 0x400 */ 128 struct rkpcie_cmd cmd; 129 }; 130 131 static void pcie_inbound_config(void) 132 { 133 u64 base = PCIE_SNPS_IATU_BASE + 0x100; 134 u32 val; 135 char i; 136 137 /* BAR0: RKEP_BAR0_ADDR */ 138 writel(RKEP_BAR0_ADDR, base + PCIE_ATU_CPU_ADDR_LOW); 139 writel(0, base + PCIE_ATU_CPU_ADDR_HIGH); 140 writel(0, base + PCIE_ATU_UNR_REGION_CTRL1); 141 /* PCIE_ATU_UNR_REGION_CTRL2 */ 142 writel(PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE | (0 << 8), 143 base + PCIE_ATU_UNR_REGION_CTRL2); 144 for (i = 0; i < 5; i++) { 145 val = readl(base + PCIE_ATU_UNR_REGION_CTRL2); 146 if (val & PCIE_ATU_ENABLE) 147 break; 148 udelay(LINK_WAIT_IATU); 149 } 150 printep("BAR0: 0x%x\n", RKEP_BAR0_ADDR); 151 152 /* BAR2: RKEP_BAR2_ADDR */ 153 writel(RKEP_BAR2_ADDR, base + PCIE_ATU_CPU_ADDR_LOW + 0x200); 154 writel(0, base + PCIE_ATU_CPU_ADDR_HIGH + 0x200); 155 writel(0, base + PCIE_ATU_UNR_REGION_CTRL1 + 0x200); 156 writel(PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE | (2 << 8), 157 base + PCIE_ATU_UNR_REGION_CTRL2 + 0x200); 158 for (i = 0; i < 5; i++) { 159 val = readl(base + PCIE_ATU_UNR_REGION_CTRL2 + 0x200); 160 if (val & PCIE_ATU_ENABLE) 161 break; 162 udelay(LINK_WAIT_IATU); 163 } 164 printep("BAR2: 0x%x%x\n", 0, RKEP_BAR2_ADDR); 165 166 /* BAR4 is wired reg, no need iATU */ 167 } 168 169 static int rockchip_pcie_ep_set_bar_flag(void *dbi_base, u32 barno, int flags) 170 { 171 u32 reg; 172 173 reg = PCI_BASE_ADDRESS_0 + (4 * barno); 174 175 /* Disabled the upper 32bits BAR to make a 64bits bar pair */ 176 if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) 177 writel(0, dbi_base + reg + 0x100000 + 4); 178 179 writel(flags, dbi_base + reg); 180 if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) 181 writel(0, dbi_base + reg + 4); 182 183 return 0; 184 } 185 186 static void pcie_bar_init(void *dbi_base) 187 { 188 void *resbar_base; 189 u32 val; 190 191 writel(0, dbi_base + 0x10); 192 writel(0, dbi_base + 0x14); 193 writel(0, dbi_base + 0x18); 194 writel(0, dbi_base + 0x1c); 195 writel(0, dbi_base + 0x20); 196 writel(0, dbi_base + 0x24); 197 198 /* Disable ASPM */ 199 val = readl(dbi_base + 0x7c); 200 val &= ~(3 << 10); 201 writel(val, dbi_base + 0x7c); 202 203 /* Resize BAR0 to support 4M 32bits */ 204 resbar_base = dbi_base + PCI_RESBAR; 205 writel(0x40, resbar_base + 0x4); 206 writel(0x2c0, resbar_base + 0x8); 207 /* BAR2: 64M 64bits */ 208 writel(0x400, resbar_base + 0x14); 209 writel(0x6c0, resbar_base + 0x18); 210 /* BAR4: Fixed for EP wired register, 1M 32bits */ 211 writel(0x10, resbar_base + 0x24); 212 writel(0xc0, resbar_base + 0x28); 213 /* Set flags */ 214 rockchip_pcie_ep_set_bar_flag(dbi_base, 0, PCI_BASE_ADDRESS_MEM_TYPE_32); 215 rockchip_pcie_ep_set_bar_flag(dbi_base, 2, 216 PCI_BASE_ADDRESS_MEM_PREFETCH | PCI_BASE_ADDRESS_MEM_TYPE_64); 217 rockchip_pcie_ep_set_bar_flag(dbi_base, 4, PCI_BASE_ADDRESS_MEM_TYPE_32); 218 219 /* Close bar1 bar5 */ 220 writel(0x0, dbi_base + 0x100000 + 0x14); 221 //writel(0x0, dbi_base + 0x100000 + 0x18); 222 //writel(0x0, dbi_base + 0x100000 + 0x1c); 223 //writel(0x0, dbi_base + 0x100000 + 0x20); 224 writel(0x0, dbi_base + 0x100000 + 0x24); 225 /* Close ROM BAR */ 226 writel(0x0, dbi_base + 0x100000 + 0x30); 227 } 228 229 static void pcie_bar0_header_init(void) 230 { 231 struct rkpcie_boot *bh = (struct rkpcie_boot *)RKEP_BAR0_ADDR; 232 233 bh->magic = RKEP_BOOT_MAGIC; 234 bh->version = 0x100; 235 bh->devmode.mode = RKEP_MODE_LOADER; 236 bh->devmode.submode = RKEP_SMODE_INIT; 237 bh->cap_size = 0; 238 239 memset((char *)RKEP_BAR0_CMD_ADDR, 0, sizeof(struct rkpcie_cmd)); 240 } 241 242 static void pcie_link_set_max_speed(void *dbi_base, u32 link_gen) 243 { 244 u32 cap, ctrl2, link_speed; 245 u8 offset = 0x70; 246 247 cap = readl(dbi_base + offset + PCI_EXP_LNKCAP); 248 ctrl2 = readl(dbi_base + offset + PCI_EXP_LNKCTL2); 249 ctrl2 &= ~PCI_EXP_LNKCTL2_TLS; 250 251 link_speed = link_gen; 252 253 cap &= ~((u32)PCI_EXP_LNKCAP_SLS); 254 writel(ctrl2 | link_speed, dbi_base + offset + PCI_EXP_LNKCTL2); 255 writel(cap | link_speed, dbi_base + offset + PCI_EXP_LNKCAP); 256 } 257 258 static void pcie_link_set_lanes(void *dbi_base, u32 lanes) 259 { 260 u32 val; 261 262 /* Set the number of lanes */ 263 val = readl(dbi_base + PCIE_PORT_LINK_CONTROL); 264 val &= ~PORT_LINK_MODE_MASK; 265 switch (lanes) { 266 case 1: 267 val |= PORT_LINK_MODE_1_LANES; 268 break; 269 case 2: 270 val |= PORT_LINK_MODE_2_LANES; 271 break; 272 case 4: 273 val |= PORT_LINK_MODE_4_LANES; 274 break; 275 default: 276 printf("RKEP: num-lanes %u: invalid value\n", lanes); 277 return; 278 } 279 writel(val, dbi_base + PCIE_PORT_LINK_CONTROL); 280 281 /* Set link width speed control register */ 282 val = readl(dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); 283 val &= ~PORT_LOGIC_LINK_WIDTH_MASK; 284 switch (lanes) { 285 case 1: 286 val |= PORT_LOGIC_LINK_WIDTH_1_LANES; 287 break; 288 case 2: 289 val |= PORT_LOGIC_LINK_WIDTH_2_LANES; 290 break; 291 case 4: 292 val |= PORT_LOGIC_LINK_WIDTH_4_LANES; 293 break; 294 } 295 296 val |= PCIE_DIRECT_SPEED_CHANGE; 297 298 writel(val, dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); 299 } 300 301 static void pcie_devmode_update(int mode, int submode) 302 { 303 struct rkpcie_boot *bh = (struct rkpcie_boot *)RKEP_BAR0_ADDR; 304 305 bh->devmode.mode = mode; 306 bh->devmode.submode = submode; 307 flush_dcache_range(RKEP_BAR0_ADDR, RKEP_BAR0_ADDR + 64); 308 } 309 310 #ifdef CONFIG_SPL_RAM_DEVICE 311 static void pcie_wait_for_fw(void) 312 { 313 struct rkpcie_cmd *cmd = (struct rkpcie_cmd *)(RKEP_BAR0_CMD_ADDR); 314 int val; 315 int i = 0; 316 317 printep("Link ready! Waiting RC to download Firmware:\n"); 318 printep("Download uboot.img to BAR2+0\n"); 319 printep("Download boot.img to BAR2+0x400000\n"); 320 printep("Send CMD_LOADER_RUN to BAR0+0x400\n"); 321 while (1) { 322 invalidate_dcache_range(RKEP_BAR0_CMD_ADDR, 323 RKEP_BAR0_CMD_ADDR + 32); 324 val = readl(&cmd->cmd); 325 if (val == RKEP_CMD_LOADER_RUN) 326 break; 327 i++; 328 if (!(i % 10)) 329 printep("Waiting for FW, CMD: %x\n", val); 330 mdelay(100); 331 } 332 /* Invalidate Cache for firmware area: BAR2, 64MB */ 333 invalidate_dcache_range(RKEP_BAR2_ADDR, RKEP_BAR2_ADDR + 0x4000000); 334 printep("Firmware Download complete!\n"); 335 } 336 337 static void pcie_update_atags(void) 338 { 339 struct tag_ram_partition t_ram_part; 340 341 if (!atags_is_available()) { 342 printep("RKEP: No ATAGS data found, create new!\n"); 343 atags_destroy(); 344 } 345 346 /* ram partition */ 347 memset(&t_ram_part, 0, sizeof(t_ram_part)); 348 t_ram_part.version = 0; 349 t_ram_part.count = 1; 350 strcpy(t_ram_part.part[0].name, "boot"); 351 t_ram_part.part[0].start = RKEP_BAR2_ADDR + 0x400000; /* 4M offset */ 352 t_ram_part.part[0].size = 0x3c00000; /* 60M size */ 353 atags_set_tag(ATAG_RAM_PARTITION, &t_ram_part); 354 } 355 356 void rockchip_pcie_ep_get_firmware(void) 357 { 358 pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_FWDLRDY); 359 pcie_wait_for_fw(); 360 pcie_update_atags(); 361 pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_FWDLDONE); 362 } 363 #endif 364 365 #ifdef CONFIG_ROCKCHIP_RK3588 366 #define BUS_IOC_GPIO3D_IOMUX_SEL_H 0xfd5f807c 367 #define GPIO3_BASE 0xfec40000 368 #define GPIO3_SWPORT_DR_H (GPIO3_BASE + 0x4) 369 #define GPIO3_SWPORT_DDR_H (GPIO3_BASE + 0xc) 370 371 static void pcie_board_init(void) 372 { 373 /* Enable AU5426 buffer chip on EVB4v10 */ 374 /* Set GPIO3D4 to gpio output HIGH mode PCIE20_CLK_PWREN */ 375 writel(0xf << 16, BUS_IOC_GPIO3D_IOMUX_SEL_H); 376 writel(0x10001000, GPIO3_SWPORT_DDR_H); 377 writel(0x10001000, GPIO3_SWPORT_DR_H); 378 udelay(100); 379 } 380 381 #define PHY_MODE_PCIE_AGGREGATION 4 /* PCIe3x4 */ 382 #define PHY_MODE_PCIE_NANBNB 0 /* P1:PCIe3x2 + P0:PCIe3x2 */ 383 #define PHY_MODE_PCIE_NANBBI 1 /* P1:PCIe3x2 + P0:PCIe3x1*2 */ 384 #define PHY_MODE_PCIE_NABINB 2 /* P1:PCIe3x1*2 + P0:PCIe3x2 */ 385 #define PHY_MODE_PCIE_NABIBI 3 /* P1:PCIe3x1*2 + P0:PCIe3x1*2 */ 386 387 #define PHY_MODE_PCIE PHY_MODE_PCIE_AGGREGATION 388 389 #define CRU_BASE_ADDR 0xfd7c0000 390 #define CRU_SOFTRST_CON32 (CRU_BASE_ADDR + 0x0a80) 391 #define CRU_SOFTRST_CON33 (CRU_BASE_ADDR + 0x0a84) 392 #define CRU_SOFTRST_CON34 (CRU_BASE_ADDR + 0x0a88) 393 #define CRU_GATE_CON32 (CRU_BASE_ADDR + 0x0880) 394 #define CRU_GATE_CON33 (CRU_BASE_ADDR + 0x0884) 395 #define CRU_GATE_CON34 (CRU_BASE_ADDR + 0x0888) 396 #define CRU_GATE_CON38 (CRU_BASE_ADDR + 0x0898) 397 #define CRU_GATE_CON39 (CRU_BASE_ADDR + 0x089c) 398 #define PHPTOPCRU_BASE_ADDR 0xfd7c8000 399 #define PHPTOPCRU_SOFTRST_CON00 (PHPTOPCRU_BASE_ADDR + 0x0a00) 400 #define PHPTOPCRU_GATE_CON00 (PHPTOPCRU_BASE_ADDR + 0x0800) 401 #define PCIE3PHY_GRF_BASE 0xfd5b8000 402 #define RK3588_PCIE3PHY_GRF_CMN_CON0 (PCIE3PHY_GRF_BASE + 0x0000) 403 #define PCIE3PHY_GRF_PHY0_CON6 (PCIE3PHY_GRF_BASE + 0x0118) 404 #define PCIE3PHY_GRF_PHY1_CON6 (PCIE3PHY_GRF_BASE + 0x0218) 405 #define PCIE3PHY_GRF_PHY0_LN0_CON1 (PCIE3PHY_GRF_BASE + 0x1004) 406 #define PCIE3PHY_GRF_PHY0_LN1_CON1 (PCIE3PHY_GRF_BASE + 0x1104) 407 #define PCIE3PHY_GRF_PHY1_LN0_CON1 (PCIE3PHY_GRF_BASE + 0x2004) 408 #define PCIE3PHY_GRF_PHY1_LN1_CON1 (PCIE3PHY_GRF_BASE + 0x2104) 409 #define FIREWALL_PCIE_MASTER_SEC 0xfe0300f0 410 #define FIREWALL_PCIE_ACCESS 0xfd586040 411 #define CRU_PHYREF_ALT_GATE_CON (CRU_BASE_ADDR + 0x0c38) 412 #define PMU1_GRF_BASE 0xfd58a000 413 #define PMU_PWR_GATE_SFTCON1 0xfd8d8150 414 #define PMU1_IOC_BASE 0xfd5F0000 415 #define CRU_GLB_RST_CON_OFFSET (0xC10U) 416 #define CRU_GLB_SRST_FST_VALUE_OFFSET (0xC08U) 417 418 void pcie_first_reset(void) 419 { 420 printep("Fst Reset\n"); 421 mdelay(1); 422 423 writel(0xFFDF, CRU_BASE_ADDR + CRU_GLB_RST_CON_OFFSET); 424 writel(0xffffffff, PMU1_GRF_BASE + 0x4); // reset width 425 writel(0x30003000, PMU1_GRF_BASE + 0x1c); // pmu1_grf pmu1_ioc hiold 426 writel(0x00f00020, PMU1_IOC_BASE + 0x0); //select tsad_shut_m0 iomux 427 writel(0xFDB9, CRU_BASE_ADDR + CRU_GLB_SRST_FST_VALUE_OFFSET); 428 429 while (1) 430 ; 431 } 432 433 static void pcie_cru_init(void) 434 { 435 u32 phy0_mplla, phy1_mplla, t0 = 0, t1 = 0; 436 u32 i, timeout = 500; 437 438 /* Enable power domain: PD_PCIE & PD_PHP */ 439 writel(0x1 << 23 | 0x1 << 21, PMU_PWR_GATE_SFTCON1); 440 441 /* FixMe init 3.0 PHY */ 442 /* Phy mode: Aggregation NBNB */ 443 writel((0x7 << 16) | PHY_MODE_PCIE, RK3588_PCIE3PHY_GRF_CMN_CON0); 444 printep("PHY Mode 0x%x\n", readl(RK3588_PCIE3PHY_GRF_CMN_CON0) & 7); 445 /* Enable clock and sfreset for Controller and PHY */ 446 writel(0xffff0000, CRU_SOFTRST_CON32); 447 writel(0xffff0000, CRU_SOFTRST_CON33); 448 writel(0xffff0000, CRU_SOFTRST_CON34); 449 writel(0xffff0000, CRU_GATE_CON32); 450 writel(0xffff0000, CRU_GATE_CON33); 451 writel(0xffff0000, CRU_GATE_CON34); 452 writel(0xffff0000, CRU_GATE_CON38); 453 writel(0xffff0000, CRU_GATE_CON39); 454 455 writel((0x1 << 24), PHPTOPCRU_SOFTRST_CON00); 456 writel(0xffff0000, PHPTOPCRU_GATE_CON00); 457 458 /* PHY Reset */ 459 writel((0x1 << 10) | (0x1 << 26), PHPTOPCRU_SOFTRST_CON00); 460 461 udelay(1); 462 463 #ifdef PCIE_ENABLE_SRNS_PLL_REFCLK 464 writel(0x000f0000, CRU_PHYREF_ALT_GATE_CON); 465 466 /* PHY0 & PHY1 use internal clock */ 467 writel(0x0 | (0x1 << 18), PCIE3PHY_GRF_PHY0_CON6); 468 writel(0x0 | (0x1 << 18), PCIE3PHY_GRF_PHY1_CON6); 469 470 /* phy0_rx0_cmn_refclk_mod */ 471 writel((0x0) | (0x1 << 23), PCIE3PHY_GRF_PHY0_LN0_CON1); 472 /* phy1_rx0_cmn_refclk_mod */ 473 writel((0x0) | (0x1 << 23), PCIE3PHY_GRF_PHY0_LN1_CON1); 474 /* phy0_rx0_cmn_refclk_mod */ 475 writel((0x0) | (0x1 << 23), PCIE3PHY_GRF_PHY1_LN0_CON1); 476 /* phy1_rx0_cmn_refclk_mod */ 477 writel((0x0) | (0x1 << 23), PCIE3PHY_GRF_PHY1_LN1_CON1); 478 #endif 479 480 udelay(1000); 481 482 /* Deassert PCIe PMA output clamp mode */ 483 writel((0x1 << 8) | (0x1 << 24), RK3588_PCIE3PHY_GRF_CMN_CON0); 484 485 /* Deassert PHY Reset */ 486 writel((0x1 << 26), PHPTOPCRU_SOFTRST_CON00); 487 488 /* S-Phy: waiting for phy locked */ 489 for (i = 0; i < timeout; i++) { 490 phy0_mplla = readl(PCIE3PHY_GRF_BASE + 0x904); 491 phy1_mplla = readl(PCIE3PHY_GRF_BASE + 0xA04); 492 493 if (phy0_mplla != t0 || phy1_mplla != t1) { 494 printep("RKEP: GRF:904=%x, a04=%x...\n", phy0_mplla, phy1_mplla); 495 496 t0 = phy0_mplla; 497 t1 = phy1_mplla; 498 if (((PHY_MODE_PCIE == PHY_MODE_PCIE_AGGREGATION) && (phy0_mplla == 0xF && phy1_mplla == 0xF)) || 499 ((PHY_MODE_PCIE != PHY_MODE_PCIE_AGGREGATION) && (phy0_mplla == 0xF))) 500 break; 501 } 502 503 udelay(10); 504 } 505 506 if (i >= timeout) { 507 printep("lock fail\n"); 508 mdelay(1); 509 pcie_first_reset(); 510 } 511 512 /* PHY config: no config need for snps3.0phy */ 513 } 514 515 static void pcie_firewall_init(void) 516 { 517 /* Enable PCIe Access in firewall and master secure mode */ 518 writel(0xffff0000, FIREWALL_PCIE_MASTER_SEC); 519 writel(0x03000000, FIREWALL_PCIE_ACCESS); 520 } 521 #elif CONFIG_ROCKCHIP_RK3568 522 523 static void pcie_board_init(void) 524 { 525 /* to-do */ 526 } 527 528 static const u16 phy_fw[] = { 529 #include "./../../../drivers/phy/phy-rockchip-snps-pcie3.fw" 530 }; 531 532 #define GRF_PCIE30PHY_RK3568_CON1 0x4 533 #define GRF_PCIE30PHY_RK3568_CON3 0xC 534 #define GRF_PCIE30PHY_RK3568_CON4 0x10 535 #define GRF_PCIE30PHY_RK3568_CON5 0x14 536 #define GRF_PCIE30PHY_RK3568_CON6 0x18 537 #define GRF_PCIE30PHY_RK3568_CON9 0x24 538 #define GRF_PCIE30PHY_RK3568_STATUS0 0x80 539 #define RK3568_SRAM_INIT_DONE(reg) ((reg) & BIT(14)) 540 541 #define PMUCRU_BASE 0xFDD00000 542 #define PMUCRU_PMUGATE_CON02 (PMUCRU_BASE + 0x188) 543 544 #define CRU_BASE 0xFDD20000 545 #define CRU_GATE_CON12 (CRU_BASE + 0x330) 546 #define CRU_GATE_CON13 (CRU_BASE + 0x334) 547 #define CRU_GATE_CON33 (CRU_BASE + 0x384) 548 #define CRU_SOFTRST_CON12 (CRU_BASE + 0x430) 549 #define CRU_SOFTRST_CON27 (CRU_BASE + 0x46c) 550 #define CRU_GLB_SRST_FST_OFFSET (0xD4U) 551 552 #define PCIE30_PHY_GRF 0xFDCB8000 553 554 #define SYS_GRF_BASE 0xFDC60000 555 556 void pcie_first_reset(void) 557 { 558 printep("Fst Reset\n"); 559 mdelay(1); 560 561 writel(0x00040004, CRU_BASE + 0x104); 562 writel(0x00700010, CRU_BASE); 563 writel(0x00100010, SYS_GRF_BASE + 0x508); 564 writel(0xFDB9, CRU_BASE + CRU_GLB_SRST_FST_OFFSET); 565 566 while (1) 567 ; 568 } 569 570 void pcie_cru_init(void) 571 { 572 u32 i, reg, timeout = 500; 573 void __iomem *mmio = (void __iomem *)0xFE8C0000; 574 u32 phy0_status0, phy0_status1, t0 = 0, t1 = 0; 575 576 /* Enable phy and controoler clk */ 577 writel(0xffff0000, PMUCRU_PMUGATE_CON02); 578 writel(0xffff0000, CRU_GATE_CON12); 579 writel(0xffff0000, CRU_GATE_CON13); 580 writel(0xffff0000, CRU_GATE_CON33); 581 writel(0xffff0000, CRU_SOFTRST_CON27); 582 583 writel(0x40004000, CRU_SOFTRST_CON27); 584 writel(0x80008000, PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON9); 585 586 writel((0x1 << 15) | (0x1 << 31), 587 PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON9); //map to access sram 588 589 #ifdef PCIE_ENABLE_SRNS_PLL_REFCLK 590 /* use internal clock */ 591 writel(0x0 | (0x1 << 31), PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON3); 592 593 /* rx0_cmn_refclk_mode disabled */ 594 writel((0x0) | (0x1 << 25), PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON5); 595 /* rx1_cmn_refclk_mode disabled */ 596 writel((0x0) | (0x1 << 25), PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON6); 597 #endif 598 599 writel((0x0 << 14) | (0x1 << (14 + 16)), 600 PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON4); //sdram_ld_done 601 writel((0x0 << 13) | (0x1 << (13 + 16)), 602 PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON4); //sdram_bypass 603 604 writel(0x40000000, CRU_SOFTRST_CON27); 605 606 udelay(5); 607 printep("RKEP: sram initial\n"); 608 while (1) { 609 reg = readl(PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_STATUS0); 610 if (RK3568_SRAM_INIT_DONE(reg)) 611 break; 612 } 613 printep("RKEP: sram init done\n"); 614 615 writel((0x3 << 8) | (0x3 << (8 + 16)), 616 PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON9); //map to access sram 617 for (i = 0; i < ARRAY_SIZE(phy_fw); i++) 618 writel(phy_fw[i], mmio + (i << 2)); 619 620 printep("RKEP: snps pcie3phy FW update! size %ld\n", ARRAY_SIZE(phy_fw)); 621 writel((0x0 << 8) | (0x3 << (8 + 16)), 622 PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON9); 623 writel((0x1 << 14) | (0x1 << (14 + 16)), 624 PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON4); //sdram_ld_done 625 626 writel(0xffff0000, CRU_SOFTRST_CON12); 627 writel(0x100010, PCIE_SNPS_APB_BASE + 0x180); 628 629 /* S-Phy: waiting for phy locked */ 630 for (i = 0; i < timeout; i++) { 631 phy0_status0 = readl(PCIE30_PHY_GRF + 0x80); 632 phy0_status1 = readl(PCIE30_PHY_GRF + 0x84); 633 634 if (phy0_status0 != t0 || phy0_status1 != t1) { 635 printep("RKEP: GRF:0x80=%x, 0x84=%x...\n", phy0_status0, phy0_status1); 636 637 t0 = phy0_status0; 638 t1 = phy0_status1; 639 if (RK3568_SRAM_INIT_DONE(phy0_status0)) 640 break; 641 } 642 643 udelay(10); 644 } 645 646 if (i >= timeout) { 647 printep("lock fail\n"); 648 mdelay(1); 649 pcie_first_reset(); 650 } 651 652 udelay(1); 653 } 654 655 static void pcie_firewall_init(void) 656 { 657 } 658 #endif 659 660 static void pcie_ep_init(void) 661 { 662 u32 val; 663 void *dbi_base = (void *)PCIE_SNPS_DBI_BASE; 664 u64 apb_base = PCIE_SNPS_APB_BASE; 665 int i, retries = 0, phy_linkup; 666 667 #ifdef PCIE_ENABLE_SRNS_PLL_REFCLK 668 printep("RefClock in SRNS clock mode\n"); 669 #else 670 printep("RefClock in common clock_mode\n"); 671 #endif 672 673 /* 674 * ltssm_enable enhance mode and enable delaying the link training 675 * after Hot Reset 676 */ 677 writel(0x120012, apb_base + 0x180); 678 679 /* Unmask pm_turnoff_int */ 680 writel(0x04000000, apb_base + 0x18); 681 682 /* PortLorgic DBI_RO_WR_EN */ 683 val = readl((dbi_base + 0x8bc)); 684 val |= 0x1; 685 writel(val, dbi_base + 0x8bc); 686 687 reinit: 688 pcie_bar_init(dbi_base); 689 pcie_inbound_config(); 690 691 /* Device PID, DID */ 692 writel(0x1d87, dbi_base + 0x00); 693 writel(0x356a, dbi_base + 0x02); 694 /* Device Class: Processing accelerators */ 695 writel(0x1200, dbi_base + 0x0a); 696 697 pcie_link_set_max_speed(dbi_base, PCI_EXP_LNKCTL2_TLS_8_0GT); 698 699 #ifdef CONFIG_ROCKCHIP_RK3588 700 pcie_link_set_lanes(dbi_base, 4); 701 #elif CONFIG_ROCKCHIP_RK3568 702 pcie_link_set_lanes(dbi_base, 2); 703 #endif 704 705 /* EP mode */ 706 writel(0xf00000, apb_base); 707 udelay(100); 708 709 /* Enable EP mem/io access */ 710 val = readl(dbi_base + 0x4); 711 writel(val | 0x6, dbi_base + 0x4); 712 713 val = readl(apb_base + 0x10); 714 if (val & 0x4) { 715 printep("Link is reset, int status misc=%x\n", val); 716 retries++; 717 } 718 719 if (retries) /* Set app_dly2_done to enable app_ltssm_enable */ 720 writel(0x80008, apb_base + 0x180); 721 else /* Enable LTSSM */ 722 writel(0xc000c, apb_base); 723 printep("init PCIe fast Link up\n"); 724 pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_LNKRDY); 725 726 /* Waiting for Link up */ 727 phy_linkup = 0; 728 while (1) { 729 val = readl(apb_base + 0x300); 730 if (((val & 0x3ffff) & ((0x3 << 16))) == 0x30000) 731 break; 732 733 if (((val & 0x3ffff) & ((0x3 << 16))) == 0x10000) 734 phy_linkup = 1; 735 736 if (val == 0 && phy_linkup) 737 pcie_first_reset(); 738 739 udelay(10); 740 } 741 printep("Link up %x\n", val); 742 mdelay(3); 743 744 /* Wait for link stable */ 745 for (i = 0; i < 10000; i++) { 746 val = readl(apb_base + 0x10); 747 if (val & 0x4) { 748 writel(0x4, apb_base + 0x10); 749 printep("Link is reset, int status misc=%x\n", val); 750 if (retries < 3) { 751 retries++; 752 goto reinit; 753 } else { 754 break; 755 } 756 } 757 758 /* L2 */ 759 val = readl(apb_base + 0x4); 760 if (val & 0x400) { 761 writel(0x4, apb_base + 0x10); 762 pcie_first_reset(); 763 } 764 udelay(1); 765 } 766 printep("Done\n"); 767 pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_LNKUP); 768 } 769 770 void rockchip_pcie_ep_init(void) 771 { 772 u32 val; 773 774 printf("\nRKEP: Init PCIe EP\n"); 775 pcie_bar0_header_init(); 776 777 #ifdef CONFIG_ROCKCHIP_RK3588 778 writel(0x1 << 23 | 0x1 << 21, PMU_PWR_GATE_SFTCON1); 779 udelay(10); 780 #endif 781 782 pcie_firewall_init(); 783 /* Re-in pcie initial */ 784 val = readl(PCIE_SNPS_APB_BASE + 0x300); 785 if (((val & 0x3ffff) & ((0x3 << 16))) == 0x30000) { 786 printf("RKEP: already link up\n"); 787 pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_LNKUP); 788 return; 789 } 790 791 pcie_board_init(); 792 /* CRU and PHY Init */ 793 pcie_cru_init(); 794 795 pcie_ep_init(); 796 } 797