1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2023 Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <spl.h> 8 #include <asm/io.h> 9 #include <asm/arch/cpu.h> 10 #include <asm/arch/hardware.h> 11 #include <asm/arch/ioc_rk3588.h> 12 #include <dt-bindings/clock/rk3588-cru.h> 13 #include <pci.h> 14 #include <asm/arch/rk_atags.h> 15 16 #ifndef CONFIG_SPL_LOAD_FIT_ADDRESS 17 #error "SPL_LOAD_FIT_ADDRESS not defined!" 18 #endif 19 20 #define printep(fmt, ...) \ 21 do { \ 22 printf("RKEP: %d - ", readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x2c) / 24); \ 23 printf(fmt, ##__VA_ARGS__); \ 24 } while (0) 25 26 #define RKEP_BAR0_ADDR 0x3c000000 27 #define RKEP_BAR2_ADDR CONFIG_SPL_LOAD_FIT_ADDRESS 28 #define RKEP_BAR0_CMD_ADDR (RKEP_BAR0_ADDR + 0x400) 29 #define RKEP_BOOT_MAGIC 0x524b4550 /* RKEP */ 30 #define RKEP_CMD_LOADER_RUN 0x524b4501 31 32 #define PCIE_SNPS_DBI_BASE 0xf5000000 33 #define PCIE_SNPS_APB_BASE 0xfe150000 34 #define PCIE_SNPS_IATU_BASE 0xa40300000 35 36 #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ 37 #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ 38 #define PCI_EXP_LNKCTL2_TLS 0x000f 39 #define PCI_EXP_LNKCAP_SLS 0x0000000f 40 41 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 42 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 43 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 44 45 /* Synopsys-specific PCIe configuration registers */ 46 #define PCIE_PORT_LINK_CONTROL 0x710 47 #define PORT_LINK_MODE_MASK (0x3f << 16) 48 #define PORT_LINK_MODE_1_LANES (0x1 << 16) 49 #define PORT_LINK_MODE_2_LANES (0x3 << 16) 50 #define PORT_LINK_MODE_4_LANES (0x7 << 16) 51 #define PORT_LINK_MODE_8_LANES (0xf << 16) 52 53 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C 54 #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) 55 #define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8) 56 #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) 57 #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8) 58 #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8) 59 #define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8) 60 61 #define PCIE_DIRECT_SPEED_CHANGE (0x1 << 17) 62 63 #define LINK_WAIT_IATU 10000 64 #define PCIE_ATU_ENABLE (0x1 << 31) 65 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30 | 1 << 19) 66 #define PCIE_ATU_UNR_REGION_CTRL1 0x00 67 #define PCIE_ATU_UNR_REGION_CTRL2 0x04 68 #define PCIE_ATU_CPU_ADDR_LOW 0x14 69 #define PCIE_ATU_CPU_ADDR_HIGH 0x18 70 71 /* SRNS: Use Separate refclk(internal clock) instead of from RC */ 72 // #define PCIE_ENABLE_SRNS_PLL_REFCLK 73 74 struct rkpcie_cmd { 75 u32 cmd; 76 u32 size; 77 u32 data[6]; 78 }; 79 80 /* rkep device mode status definition */ 81 #define RKEP_MODE_BOOTROM 1 82 #define RKEP_MODE_LOADER 2 83 #define RKEP_MODE_KERNEL 3 84 85 /* Common status */ 86 #define RKEP_SMODE_INIT 0 87 #define RKEP_SMODE_LNKRDY 1 88 #define RKEP_SMODE_LNKUP 2 89 #define RKEP_SMODE_ERR 0xff 90 /* Firmware download status */ 91 #define RKEP_SMODE_FWDLRDY 0x10 92 #define RKEP_SMODE_FWDLDONE 0x11 93 /* Application status*/ 94 #define RKEP_SMODE_APPRDY 0x20 95 96 struct rkpcie_boot { 97 /* magic: "RKEP" */ 98 u32 magic; 99 u32 version; 100 struct { 101 u16 mode; 102 u16 submode; 103 } devmode; 104 /* Size of ATAGS for cap */ 105 u32 cap_size; 106 struct { 107 u8 cmd; 108 u8 status; 109 /* Error code for current CMD */ 110 u16 opcode; 111 } cmd_status; 112 u32 reserved[2]; 113 /* RK ATAGS, for mem and other info */ 114 struct tag cap; 115 /* offset 0x400 */ 116 struct rkpcie_cmd cmd; 117 }; 118 119 static void pcie_inbound_config(void) 120 { 121 u64 base = PCIE_SNPS_IATU_BASE + 0x100; 122 u32 val; 123 char i; 124 125 /* BAR0: RKEP_BAR0_ADDR */ 126 writel(RKEP_BAR0_ADDR, base + PCIE_ATU_CPU_ADDR_LOW); 127 writel(0, base + PCIE_ATU_CPU_ADDR_HIGH); 128 writel(0, base + PCIE_ATU_UNR_REGION_CTRL1); 129 /* PCIE_ATU_UNR_REGION_CTRL2 */ 130 writel(PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE | (0 << 8), 131 base + PCIE_ATU_UNR_REGION_CTRL2); 132 for (i = 0; i < 5; i++) { 133 val = readl(base + PCIE_ATU_UNR_REGION_CTRL2); 134 if (val & PCIE_ATU_ENABLE) 135 break; 136 udelay(LINK_WAIT_IATU); 137 } 138 printep("BAR0: 0x%x\n", RKEP_BAR0_ADDR); 139 140 /* BAR2: RKEP_BAR2_ADDR */ 141 writel(RKEP_BAR2_ADDR, base + PCIE_ATU_CPU_ADDR_LOW + 0x200); 142 writel(0, base + PCIE_ATU_CPU_ADDR_HIGH + 0x200); 143 writel(0, base + PCIE_ATU_UNR_REGION_CTRL1 + 0x200); 144 writel(PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE | (2 << 8), 145 base + PCIE_ATU_UNR_REGION_CTRL2 + 0x200); 146 for (i = 0; i < 5; i++) { 147 val = readl(base + PCIE_ATU_UNR_REGION_CTRL2 + 0x200); 148 if (val & PCIE_ATU_ENABLE) 149 break; 150 udelay(LINK_WAIT_IATU); 151 } 152 printep("BAR2: 0x%x%x\n", 0, RKEP_BAR2_ADDR); 153 154 /* BAR4 is wired reg, no need iATU */ 155 } 156 157 #define PHY_MODE_PCIE_AGGREGATION 4 /* PCIe3x4 */ 158 #define PHY_MODE_PCIE_NANBNB 0 /* P1:PCIe3x2 + P0:PCIe3x2 */ 159 #define PHY_MODE_PCIE_NANBBI 1 /* P1:PCIe3x2 + P0:PCIe3x1*2 */ 160 #define PHY_MODE_PCIE_NABINB 2 /* P1:PCIe3x1*2 + P0:PCIe3x2 */ 161 #define PHY_MODE_PCIE_NABIBI 3 /* P1:PCIe3x1*2 + P0:PCIe3x1*2 */ 162 163 #define CRU_BASE_ADDR 0xfd7c0000 164 #define CRU_SOFTRST_CON32 (CRU_BASE_ADDR + 0x0a80) 165 #define CRU_SOFTRST_CON33 (CRU_BASE_ADDR + 0x0a84) 166 #define CRU_SOFTRST_CON34 (CRU_BASE_ADDR + 0x0a88) 167 #define CRU_GATE_CON32 (CRU_BASE_ADDR + 0x0880) 168 #define CRU_GATE_CON33 (CRU_BASE_ADDR + 0x0884) 169 #define CRU_GATE_CON34 (CRU_BASE_ADDR + 0x0888) 170 #define CRU_GATE_CON38 (CRU_BASE_ADDR + 0x0898) 171 #define CRU_GATE_CON39 (CRU_BASE_ADDR + 0x089c) 172 #define PHPTOPCRU_BASE_ADDR 0xfd7c8000 173 #define PHPTOPCRU_SOFTRST_CON00 (PHPTOPCRU_BASE_ADDR + 0x0a00) 174 #define PHPTOPCRU_GATE_CON00 (PHPTOPCRU_BASE_ADDR + 0x0800) 175 #define PCIE3PHY_GRF_BASE 0xfd5b8000 176 #define RK3588_PCIE3PHY_GRF_CMN_CON0 (PCIE3PHY_GRF_BASE + 0x0000) 177 #define PCIE3PHY_GRF_PHY0_CON6 (PCIE3PHY_GRF_BASE + 0x0118) 178 #define PCIE3PHY_GRF_PHY1_CON6 (PCIE3PHY_GRF_BASE + 0x0218) 179 #define PCIE3PHY_GRF_PHY0_LN0_CON1 (PCIE3PHY_GRF_BASE + 0x1004) 180 #define PCIE3PHY_GRF_PHY0_LN1_CON1 (PCIE3PHY_GRF_BASE + 0x1104) 181 #define PCIE3PHY_GRF_PHY1_LN0_CON1 (PCIE3PHY_GRF_BASE + 0x2004) 182 #define PCIE3PHY_GRF_PHY1_LN1_CON1 (PCIE3PHY_GRF_BASE + 0x2104) 183 #define FIREWALL_PCIE_MASTER_SEC 0xfe0300f0 184 #define FIREWALL_PCIE_ACCESS 0xfe586040 185 #define CRU_PHYREF_ALT_GATE_CON (CRU_BASE_ADDR + 0x0c38) 186 #define PMU_PWR_GATE_SFTCON1 0xfd8d8150 187 static void pcie_cru_init(void) 188 { 189 /* Enable power domain: PD_PCIE & PD_PHP */ 190 writel(0x1 << 23 | 0x1 << 21, PMU_PWR_GATE_SFTCON1); 191 192 /* FixMe init 3.0 PHY */ 193 /* Phy mode: Aggregation NBNB */ 194 writel((0x7 << 16) | PHY_MODE_PCIE_AGGREGATION, RK3588_PCIE3PHY_GRF_CMN_CON0); 195 printep("PHY Mode 0x%x\n", readl(RK3588_PCIE3PHY_GRF_CMN_CON0) & 7); 196 /* Enable clock and sfreset for Controller and PHY */ 197 writel(0xffff0000, CRU_SOFTRST_CON32); 198 writel(0xffff0000, CRU_SOFTRST_CON33); 199 writel(0xffff0000, CRU_SOFTRST_CON34); 200 writel(0xffff0000, CRU_GATE_CON32); 201 writel(0xffff0000, CRU_GATE_CON33); 202 writel(0xffff0000, CRU_GATE_CON34); 203 writel(0xffff0000, CRU_GATE_CON38); 204 writel(0xffff0000, CRU_GATE_CON39); 205 206 writel((0x1 << 24), PHPTOPCRU_SOFTRST_CON00); 207 writel(0xffff0000, PHPTOPCRU_GATE_CON00); 208 209 /* PHY Reset */ 210 writel((0x1 << 10) | (0x1 << 26), PHPTOPCRU_SOFTRST_CON00); 211 212 udelay(1); 213 214 #ifdef PCIE_ENABLE_SRNS_PLL_REFCLK 215 writel(0x000f0000, CRU_PHYREF_ALT_GATE_CON); 216 217 /* PHY0 & PHY1 use internal clock */ 218 writel(0x0 | (0x1 << 18), PCIE3PHY_GRF_PHY0_CON6); 219 writel(0x0 | (0x1 << 18), PCIE3PHY_GRF_PHY1_CON6); 220 221 /* phy0_rx0_cmn_refclk_mod */ 222 writel((0x0) | (0x1 << 23), PCIE3PHY_GRF_PHY0_LN0_CON1); 223 /* phy1_rx0_cmn_refclk_mod */ 224 writel((0x0) | (0x1 << 23), PCIE3PHY_GRF_PHY0_LN1_CON1); 225 /* phy0_rx0_cmn_refclk_mod */ 226 writel((0x0) | (0x1 << 23), PCIE3PHY_GRF_PHY1_LN0_CON1); 227 /* phy1_rx0_cmn_refclk_mod */ 228 writel((0x0) | (0x1 << 23), PCIE3PHY_GRF_PHY1_LN1_CON1); 229 #endif 230 231 udelay(1000); 232 233 /* Deassert PCIe PMA output clamp mode */ 234 writel((0x1 << 8) | (0x1 << 24), RK3588_PCIE3PHY_GRF_CMN_CON0); 235 236 /* Deassert PHY Reset */ 237 writel((0x1 << 26), PHPTOPCRU_SOFTRST_CON00); 238 239 /* PHY config: no config need for snps3.0phy */ 240 241 /* Enable PCIe Access in firewall and master secure mode */ 242 writel(0xffff0000, FIREWALL_PCIE_MASTER_SEC); 243 writel(0x01800000, FIREWALL_PCIE_ACCESS); 244 } 245 246 #define BUS_IOC_GPIO3D_IOMUX_SEL_H 0xfd5f807c 247 #define GPIO3_BASE 0xfec40000 248 #define GPIO3_SWPORT_DR_H (GPIO3_BASE + 0x4) 249 #define GPIO3_SWPORT_DDR_H (GPIO3_BASE + 0xc) 250 251 static void pcie_board_init(void) 252 { 253 /* Enable AU5426 buffer chip on EVB4v10 */ 254 /* Set GPIO3D4 to gpio output HIGH mode PCIE20_CLK_PWREN */ 255 writel(0xf << 16, BUS_IOC_GPIO3D_IOMUX_SEL_H); 256 writel(0x10001000, GPIO3_SWPORT_DDR_H); 257 writel(0x10001000, GPIO3_SWPORT_DR_H); 258 udelay(100); 259 } 260 261 static int rockchip_pcie_ep_set_bar_flag(void *dbi_base, u32 barno, int flags) 262 { 263 u32 reg; 264 265 reg = PCI_BASE_ADDRESS_0 + (4 * barno); 266 267 /* Disabled the upper 32bits BAR to make a 64bits bar pair */ 268 if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) 269 writel(0, dbi_base + reg + 0x100000 + 4); 270 271 writel(flags, dbi_base + reg); 272 if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) 273 writel(0, dbi_base + reg + 4); 274 275 return 0; 276 } 277 278 static void pcie_bar_init(void *dbi_base) 279 { 280 void *resbar_base; 281 282 writel(0, dbi_base + 0x10); 283 writel(0, dbi_base + 0x14); 284 writel(0, dbi_base + 0x18); 285 writel(0, dbi_base + 0x1c); 286 writel(0, dbi_base + 0x20); 287 writel(0, dbi_base + 0x24); 288 289 /* Resize BAR0 to support 4M 32bits */ 290 resbar_base = dbi_base + 0x2e8; 291 writel(0xfffff0, resbar_base + 0x4); 292 writel(0x2c0, resbar_base + 0x8); 293 /* BAR2: 64M 64bits */ 294 writel(0xfffff0, resbar_base + 0x14); 295 writel(0x6c0, resbar_base + 0x18); 296 /* BAR4: Fixed for EP wired register, 1M 32bits */ 297 writel(0xfffff0, resbar_base + 0x24); 298 writel(0xc0, resbar_base + 0x28); 299 /* Set flags */ 300 rockchip_pcie_ep_set_bar_flag(dbi_base, 0, PCI_BASE_ADDRESS_MEM_TYPE_32); 301 rockchip_pcie_ep_set_bar_flag(dbi_base, 2, 302 PCI_BASE_ADDRESS_MEM_PREFETCH | PCI_BASE_ADDRESS_MEM_TYPE_64); 303 rockchip_pcie_ep_set_bar_flag(dbi_base, 4, PCI_BASE_ADDRESS_MEM_TYPE_32); 304 305 /* Close bar1 bar3 bar5 */ 306 writel(0x0, dbi_base + 0x100000 + 0x14); 307 //writel(0x0, dbi_base + 0x100000 + 0x18); 308 writel(0x0, dbi_base + 0x100000 + 0x1c); 309 //writel(0x0, dbi_base + 0x100000 + 0x20); 310 writel(0x0, dbi_base + 0x100000 + 0x24); 311 /* Close ROM BAR */ 312 writel(0x0, dbi_base + 0x100000 + 0x30); 313 } 314 315 static void pcie_bar0_header_init(void) 316 { 317 struct rkpcie_boot *bh = (struct rkpcie_boot *)RKEP_BAR0_ADDR; 318 319 bh->magic = RKEP_BOOT_MAGIC; 320 bh->version = 0x100; 321 bh->devmode.mode = RKEP_MODE_LOADER; 322 bh->devmode.submode = RKEP_SMODE_INIT; 323 bh->cap_size = 0; 324 325 memset((char *)RKEP_BAR0_CMD_ADDR, 0, sizeof(struct rkpcie_cmd)); 326 } 327 328 static void pcie_link_set_max_speed(void *dbi_base, u32 link_gen) 329 { 330 u32 cap, ctrl2, link_speed; 331 u8 offset = 0x70; 332 333 cap = readl(dbi_base + offset + PCI_EXP_LNKCAP); 334 ctrl2 = readl(dbi_base + offset + PCI_EXP_LNKCTL2); 335 ctrl2 &= ~PCI_EXP_LNKCTL2_TLS; 336 337 link_speed = link_gen; 338 339 cap &= ~((u32)PCI_EXP_LNKCAP_SLS); 340 writel(ctrl2 | link_speed, dbi_base + offset + PCI_EXP_LNKCTL2); 341 writel(cap | link_speed, dbi_base + offset + PCI_EXP_LNKCAP); 342 } 343 344 static void pcie_link_set_lanes(void *dbi_base, u32 lanes) 345 { 346 u32 val; 347 348 /* Set the number of lanes */ 349 val = readl(dbi_base + PCIE_PORT_LINK_CONTROL); 350 val &= ~PORT_LINK_MODE_MASK; 351 switch (lanes) { 352 case 1: 353 val |= PORT_LINK_MODE_1_LANES; 354 break; 355 case 2: 356 val |= PORT_LINK_MODE_2_LANES; 357 break; 358 case 4: 359 val |= PORT_LINK_MODE_4_LANES; 360 break; 361 default: 362 printf("num-lanes %u: invalid value\n", lanes); 363 return; 364 } 365 writel(val, dbi_base + PCIE_PORT_LINK_CONTROL); 366 367 /* Set link width speed control register */ 368 val = readl(dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); 369 val &= ~PORT_LOGIC_LINK_WIDTH_MASK; 370 switch (lanes) { 371 case 1: 372 val |= PORT_LOGIC_LINK_WIDTH_1_LANES; 373 break; 374 case 2: 375 val |= PORT_LOGIC_LINK_WIDTH_2_LANES; 376 break; 377 case 4: 378 val |= PORT_LOGIC_LINK_WIDTH_4_LANES; 379 break; 380 } 381 382 val |= PCIE_DIRECT_SPEED_CHANGE; 383 384 writel(val, dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); 385 } 386 387 static void pcie_devmode_update(int mode, int submode) 388 { 389 struct rkpcie_boot *bh = (struct rkpcie_boot *)RKEP_BAR0_ADDR; 390 391 bh->devmode.mode = mode; 392 bh->devmode.submode = submode; 393 flush_dcache_range(RKEP_BAR0_ADDR, RKEP_BAR0_ADDR + 64); 394 } 395 396 #ifdef CONFIG_SPL_RAM_DEVICE 397 static void pcie_wait_for_fw(void) 398 { 399 struct rkpcie_cmd *cmd = (struct rkpcie_cmd *)(RKEP_BAR0_CMD_ADDR); 400 int val; 401 int i = 0; 402 403 printep("Link ready! Waiting RC to download Firmware:\n"); 404 printep("Download uboot.img to BAR2+0\n"); 405 printep("Download boot.img to BAR2+0x400000\n"); 406 printep("Send CMD_LOADER_RUN to BAR0+0x400\n"); 407 while (1) { 408 invalidate_dcache_range(RKEP_BAR0_CMD_ADDR, 409 RKEP_BAR0_CMD_ADDR + 32); 410 val = readl(&cmd->cmd); 411 if (val == RKEP_CMD_LOADER_RUN) 412 break; 413 i++; 414 if (!(i % 10)) 415 printep("Waiting for FW, CMD: %x\n", val); 416 mdelay(100); 417 } 418 /* Invalidate Cache for firmware area: BAR2, 64MB */ 419 invalidate_dcache_range(RKEP_BAR2_ADDR, RKEP_BAR2_ADDR + 0x4000000); 420 printep("Firmware Download complete!\n"); 421 } 422 423 static void pcie_update_atags(void) 424 { 425 struct tag_ram_partition t_ram_part; 426 427 if (!atags_is_available()) { 428 printf("No ATAGS data found, create new!\n"); 429 atags_destroy(); 430 } 431 432 /* ram partition */ 433 memset(&t_ram_part, 0, sizeof(t_ram_part)); 434 t_ram_part.version = 0; 435 t_ram_part.count = 1; 436 strcpy(t_ram_part.part[0].name, "boot"); 437 t_ram_part.part[0].start = RKEP_BAR2_ADDR + 0x400000; /* 4M offset */ 438 t_ram_part.part[0].size = 0x3c00000; /* 60M size */ 439 atags_set_tag(ATAG_RAM_PARTITION, &t_ram_part); 440 } 441 442 void rockchip_pcie_ep_get_firmware(void) 443 { 444 pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_FWDLRDY); 445 pcie_wait_for_fw(); 446 pcie_update_atags(); 447 pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_FWDLDONE); 448 } 449 #endif 450 451 static void pcie_ep_init(void) 452 { 453 u32 val; 454 void *dbi_base = (void *)PCIE_SNPS_DBI_BASE; 455 u64 apb_base = PCIE_SNPS_APB_BASE; 456 int i, retries = 0; 457 458 #ifdef PCIE_ENABLE_SRNS_PLL_REFCLK 459 printep("RefClock in SRNS clock mode\n"); 460 #else 461 printep("RefClock in common clock_mode\n"); 462 #endif 463 464 /* 465 * ltssm_enable enhance mode and enable delaying the link training 466 * after Hot Reset 467 */ 468 writel(0x120012, apb_base + 0x180); 469 470 /* Unmask pm_turnoff_int */ 471 writel(0x04000000, apb_base + 0x18); 472 473 /* PortLorgic DBI_RO_WR_EN */ 474 val = readl((dbi_base + 0x8bc)); 475 val |= 0x1; 476 writel(val, dbi_base + 0x8bc); 477 478 reinit: 479 pcie_bar_init(dbi_base); 480 pcie_inbound_config(); 481 482 /* Device PID, DID */ 483 writel(0x1d87, dbi_base + 0x00); 484 writel(0x356a, dbi_base + 0x02); 485 /* Device Class: Processing accelerators */ 486 writel(0x1200, dbi_base + 0x0a); 487 488 pcie_link_set_max_speed(dbi_base, PCI_EXP_LNKCTL2_TLS_8_0GT); 489 pcie_link_set_lanes(dbi_base, 4); 490 491 /* EP mode */ 492 writel(0xf00000, apb_base); 493 udelay(100); 494 495 /* Enable EP mem/io access */ 496 val = readl(dbi_base + 0x4); 497 writel(val | 0x6, dbi_base + 0x4); 498 499 if (retries) /* Set app_dly2_done to enable app_ltssm_enable */ 500 writel(0x80008, apb_base + 0x180); 501 else /* Enable LTSSM */ 502 writel(0xc000c, apb_base); 503 printep("init PCIe fast Link up\n"); 504 pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_LNKRDY); 505 506 /* Waiting for Link up */ 507 while (1) { 508 val = readl(apb_base + 0x300); 509 if (((val & 0x3ffff) & ((0x3 << 16) | 0x11)) == 0x30011) 510 break; 511 mdelay(1); 512 } 513 printep("Link up %x\n", val); 514 mdelay(3); 515 516 /* Wait for link stable */ 517 for (i = 0; i < 10000; i++) { 518 val = readl(apb_base + 0x10); 519 if (val & 0x4) { 520 writel(0x4, apb_base + 0x10); 521 printep("Link is reset, int status misc=%x\n", val); 522 if (retries < 3) { 523 retries++; 524 goto reinit; 525 } else { 526 break; 527 } 528 } 529 udelay(1); 530 } 531 printep("Done\n"); 532 pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_LNKUP); 533 } 534 535 void rockchip_pcie_ep_init(void) 536 { 537 printf("\nRKEP: Init PCIe EP\n"); 538 pcie_bar0_header_init(); 539 540 /* 541 * TODO: Move board_init/cru_init to soc level if more SoCs available 542 */ 543 pcie_board_init(); 544 /* CRU and PHY Init */ 545 pcie_cru_init(); 546 547 pcie_ep_init(); 548 } 549