1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2023 Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <spl.h> 8 #include <asm/io.h> 9 #include <asm/arch/cpu.h> 10 #include <asm/arch/hardware.h> 11 #include <asm/arch/ioc_rk3588.h> 12 #include <dt-bindings/clock/rk3588-cru.h> 13 #include <pci.h> 14 #include <asm/arch/rk_atags.h> 15 16 #ifndef CONFIG_SPL_LOAD_FIT_ADDRESS 17 #error "SPL_LOAD_FIT_ADDRESS not defined!" 18 #endif 19 20 #define printep(fmt, ...) \ 21 do { \ 22 printf("RKEP: %d - ", readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x2c) / 24); \ 23 printf(fmt, ##__VA_ARGS__); \ 24 } while (0) 25 26 #ifdef CONFIG_ROCKCHIP_RK3588 27 #define PCIE_SNPS_DBI_BASE 0xf5000000 28 #define PCIE_SNPS_APB_BASE 0xfe150000 29 #define PCIE_SNPS_IATU_BASE 0xa40300000 30 31 #define PCI_RESBAR 0x2e8 32 #elif CONFIG_ROCKCHIP_RK3568 33 #define PCIE_SNPS_DBI_BASE 0xf6000000 34 #define PCIE_SNPS_APB_BASE 0xfe280000 35 #define PCIE_SNPS_IATU_BASE 0x3c0b00000 36 37 #define PCI_RESBAR 0x2b8 38 #else 39 #error "this soc is not support pcie ep!" 40 #endif 41 42 #define RKEP_BAR0_ADDR 0x3c000000 43 #define RKEP_BAR2_ADDR CONFIG_SPL_LOAD_FIT_ADDRESS 44 #define RKEP_BAR0_CMD_ADDR (RKEP_BAR0_ADDR + 0x400) 45 #define RKEP_BOOT_MAGIC 0x524b4550 /* RKEP */ 46 #define RKEP_CMD_LOADER_RUN 0x524b4501 47 48 #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ 49 #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ 50 #define PCI_EXP_LNKCTL2_TLS 0x000f 51 #define PCI_EXP_LNKCAP_SLS 0x0000000f 52 53 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 54 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 55 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 56 57 /* Synopsys-specific PCIe configuration registers */ 58 #define PCIE_PORT_LINK_CONTROL 0x710 59 #define PORT_LINK_MODE_MASK (0x3f << 16) 60 #define PORT_LINK_MODE_1_LANES (0x1 << 16) 61 #define PORT_LINK_MODE_2_LANES (0x3 << 16) 62 #define PORT_LINK_MODE_4_LANES (0x7 << 16) 63 #define PORT_LINK_MODE_8_LANES (0xf << 16) 64 65 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C 66 #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) 67 #define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8) 68 #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) 69 #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8) 70 #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8) 71 #define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8) 72 73 #define PCIE_DIRECT_SPEED_CHANGE (0x1 << 17) 74 75 #define LINK_WAIT_IATU 10000 76 #define PCIE_ATU_ENABLE (0x1 << 31) 77 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30 | 1 << 19) 78 #define PCIE_ATU_UNR_REGION_CTRL1 0x00 79 #define PCIE_ATU_UNR_REGION_CTRL2 0x04 80 #define PCIE_ATU_CPU_ADDR_LOW 0x14 81 #define PCIE_ATU_CPU_ADDR_HIGH 0x18 82 83 /* SRNS: Use Separate refclk(internal clock) instead of from RC */ 84 // #define PCIE_ENABLE_SRNS_PLL_REFCLK 85 86 struct rkpcie_cmd { 87 u32 cmd; 88 u32 size; 89 u32 data[6]; 90 }; 91 92 /* rkep device mode status definition */ 93 #define RKEP_MODE_BOOTROM 1 94 #define RKEP_MODE_LOADER 2 95 #define RKEP_MODE_KERNEL 3 96 97 /* Common status */ 98 #define RKEP_SMODE_INIT 0 99 #define RKEP_SMODE_LNKRDY 1 100 #define RKEP_SMODE_LNKUP 2 101 #define RKEP_SMODE_ERR 0xff 102 /* Firmware download status */ 103 #define RKEP_SMODE_FWDLRDY 0x10 104 #define RKEP_SMODE_FWDLDONE 0x11 105 /* Application status*/ 106 #define RKEP_SMODE_APPRDY 0x20 107 108 struct rkpcie_boot { 109 /* magic: "RKEP" */ 110 u32 magic; 111 u32 version; 112 struct { 113 u16 mode; 114 u16 submode; 115 } devmode; 116 /* Size of ATAGS for cap */ 117 u32 cap_size; 118 struct { 119 u8 cmd; 120 u8 status; 121 /* Error code for current CMD */ 122 u16 opcode; 123 } cmd_status; 124 u32 reserved[2]; 125 /* RK ATAGS, for mem and other info */ 126 struct tag cap; 127 /* offset 0x400 */ 128 struct rkpcie_cmd cmd; 129 }; 130 131 static void pcie_inbound_config(void) 132 { 133 u64 base = PCIE_SNPS_IATU_BASE + 0x100; 134 u32 val; 135 char i; 136 137 /* BAR0: RKEP_BAR0_ADDR */ 138 writel(RKEP_BAR0_ADDR, base + PCIE_ATU_CPU_ADDR_LOW); 139 writel(0, base + PCIE_ATU_CPU_ADDR_HIGH); 140 writel(0, base + PCIE_ATU_UNR_REGION_CTRL1); 141 /* PCIE_ATU_UNR_REGION_CTRL2 */ 142 writel(PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE | (0 << 8), 143 base + PCIE_ATU_UNR_REGION_CTRL2); 144 for (i = 0; i < 5; i++) { 145 val = readl(base + PCIE_ATU_UNR_REGION_CTRL2); 146 if (val & PCIE_ATU_ENABLE) 147 break; 148 udelay(LINK_WAIT_IATU); 149 } 150 printep("BAR0: 0x%x\n", RKEP_BAR0_ADDR); 151 152 /* BAR2: RKEP_BAR2_ADDR */ 153 writel(RKEP_BAR2_ADDR, base + PCIE_ATU_CPU_ADDR_LOW + 0x200); 154 writel(0, base + PCIE_ATU_CPU_ADDR_HIGH + 0x200); 155 writel(0, base + PCIE_ATU_UNR_REGION_CTRL1 + 0x200); 156 writel(PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE | (2 << 8), 157 base + PCIE_ATU_UNR_REGION_CTRL2 + 0x200); 158 for (i = 0; i < 5; i++) { 159 val = readl(base + PCIE_ATU_UNR_REGION_CTRL2 + 0x200); 160 if (val & PCIE_ATU_ENABLE) 161 break; 162 udelay(LINK_WAIT_IATU); 163 } 164 printep("BAR2: 0x%x%x\n", 0, RKEP_BAR2_ADDR); 165 166 /* BAR4 is wired reg, no need iATU */ 167 } 168 169 static int rockchip_pcie_ep_set_bar_flag(void *dbi_base, u32 barno, int flags) 170 { 171 u32 reg; 172 173 reg = PCI_BASE_ADDRESS_0 + (4 * barno); 174 175 /* Disabled the upper 32bits BAR to make a 64bits bar pair */ 176 if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) 177 writel(0, dbi_base + reg + 0x100000 + 4); 178 179 writel(flags, dbi_base + reg); 180 if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) 181 writel(0, dbi_base + reg + 4); 182 183 return 0; 184 } 185 186 static void pcie_bar_init(void *dbi_base) 187 { 188 void *resbar_base; 189 190 writel(0, dbi_base + 0x10); 191 writel(0, dbi_base + 0x14); 192 writel(0, dbi_base + 0x18); 193 writel(0, dbi_base + 0x1c); 194 writel(0, dbi_base + 0x20); 195 writel(0, dbi_base + 0x24); 196 197 /* Resize BAR0 to support 4M 32bits */ 198 resbar_base = dbi_base + PCI_RESBAR; 199 writel(0xfffff0, resbar_base + 0x4); 200 writel(0x2c0, resbar_base + 0x8); 201 /* BAR2: 64M 64bits */ 202 writel(0xfffff0, resbar_base + 0x14); 203 writel(0x6c0, resbar_base + 0x18); 204 /* BAR4: Fixed for EP wired register, 1M 32bits */ 205 writel(0xfffff0, resbar_base + 0x24); 206 writel(0xc0, resbar_base + 0x28); 207 /* Set flags */ 208 rockchip_pcie_ep_set_bar_flag(dbi_base, 0, PCI_BASE_ADDRESS_MEM_TYPE_32); 209 rockchip_pcie_ep_set_bar_flag(dbi_base, 2, 210 PCI_BASE_ADDRESS_MEM_PREFETCH | PCI_BASE_ADDRESS_MEM_TYPE_64); 211 rockchip_pcie_ep_set_bar_flag(dbi_base, 4, PCI_BASE_ADDRESS_MEM_TYPE_32); 212 213 /* Close bar1 bar3 bar5 */ 214 writel(0x0, dbi_base + 0x100000 + 0x14); 215 //writel(0x0, dbi_base + 0x100000 + 0x18); 216 writel(0x0, dbi_base + 0x100000 + 0x1c); 217 //writel(0x0, dbi_base + 0x100000 + 0x20); 218 writel(0x0, dbi_base + 0x100000 + 0x24); 219 /* Close ROM BAR */ 220 writel(0x0, dbi_base + 0x100000 + 0x30); 221 } 222 223 static void pcie_bar0_header_init(void) 224 { 225 struct rkpcie_boot *bh = (struct rkpcie_boot *)RKEP_BAR0_ADDR; 226 227 bh->magic = RKEP_BOOT_MAGIC; 228 bh->version = 0x100; 229 bh->devmode.mode = RKEP_MODE_LOADER; 230 bh->devmode.submode = RKEP_SMODE_INIT; 231 bh->cap_size = 0; 232 233 memset((char *)RKEP_BAR0_CMD_ADDR, 0, sizeof(struct rkpcie_cmd)); 234 } 235 236 static void pcie_link_set_max_speed(void *dbi_base, u32 link_gen) 237 { 238 u32 cap, ctrl2, link_speed; 239 u8 offset = 0x70; 240 241 cap = readl(dbi_base + offset + PCI_EXP_LNKCAP); 242 ctrl2 = readl(dbi_base + offset + PCI_EXP_LNKCTL2); 243 ctrl2 &= ~PCI_EXP_LNKCTL2_TLS; 244 245 link_speed = link_gen; 246 247 cap &= ~((u32)PCI_EXP_LNKCAP_SLS); 248 writel(ctrl2 | link_speed, dbi_base + offset + PCI_EXP_LNKCTL2); 249 writel(cap | link_speed, dbi_base + offset + PCI_EXP_LNKCAP); 250 } 251 252 static void pcie_link_set_lanes(void *dbi_base, u32 lanes) 253 { 254 u32 val; 255 256 /* Set the number of lanes */ 257 val = readl(dbi_base + PCIE_PORT_LINK_CONTROL); 258 val &= ~PORT_LINK_MODE_MASK; 259 switch (lanes) { 260 case 1: 261 val |= PORT_LINK_MODE_1_LANES; 262 break; 263 case 2: 264 val |= PORT_LINK_MODE_2_LANES; 265 break; 266 case 4: 267 val |= PORT_LINK_MODE_4_LANES; 268 break; 269 default: 270 printf("RKEP: num-lanes %u: invalid value\n", lanes); 271 return; 272 } 273 writel(val, dbi_base + PCIE_PORT_LINK_CONTROL); 274 275 /* Set link width speed control register */ 276 val = readl(dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); 277 val &= ~PORT_LOGIC_LINK_WIDTH_MASK; 278 switch (lanes) { 279 case 1: 280 val |= PORT_LOGIC_LINK_WIDTH_1_LANES; 281 break; 282 case 2: 283 val |= PORT_LOGIC_LINK_WIDTH_2_LANES; 284 break; 285 case 4: 286 val |= PORT_LOGIC_LINK_WIDTH_4_LANES; 287 break; 288 } 289 290 val |= PCIE_DIRECT_SPEED_CHANGE; 291 292 writel(val, dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); 293 } 294 295 static void pcie_devmode_update(int mode, int submode) 296 { 297 struct rkpcie_boot *bh = (struct rkpcie_boot *)RKEP_BAR0_ADDR; 298 299 bh->devmode.mode = mode; 300 bh->devmode.submode = submode; 301 flush_dcache_range(RKEP_BAR0_ADDR, RKEP_BAR0_ADDR + 64); 302 } 303 304 #ifdef CONFIG_SPL_RAM_DEVICE 305 static void pcie_wait_for_fw(void) 306 { 307 struct rkpcie_cmd *cmd = (struct rkpcie_cmd *)(RKEP_BAR0_CMD_ADDR); 308 int val; 309 int i = 0; 310 311 printep("Link ready! Waiting RC to download Firmware:\n"); 312 printep("Download uboot.img to BAR2+0\n"); 313 printep("Download boot.img to BAR2+0x400000\n"); 314 printep("Send CMD_LOADER_RUN to BAR0+0x400\n"); 315 while (1) { 316 invalidate_dcache_range(RKEP_BAR0_CMD_ADDR, 317 RKEP_BAR0_CMD_ADDR + 32); 318 val = readl(&cmd->cmd); 319 if (val == RKEP_CMD_LOADER_RUN) 320 break; 321 i++; 322 if (!(i % 10)) 323 printep("Waiting for FW, CMD: %x\n", val); 324 mdelay(100); 325 } 326 /* Invalidate Cache for firmware area: BAR2, 64MB */ 327 invalidate_dcache_range(RKEP_BAR2_ADDR, RKEP_BAR2_ADDR + 0x4000000); 328 printep("Firmware Download complete!\n"); 329 } 330 331 static void pcie_update_atags(void) 332 { 333 struct tag_ram_partition t_ram_part; 334 335 if (!atags_is_available()) { 336 printf("RKEP: No ATAGS data found, create new!\n"); 337 atags_destroy(); 338 } 339 340 /* ram partition */ 341 memset(&t_ram_part, 0, sizeof(t_ram_part)); 342 t_ram_part.version = 0; 343 t_ram_part.count = 1; 344 strcpy(t_ram_part.part[0].name, "boot"); 345 t_ram_part.part[0].start = RKEP_BAR2_ADDR + 0x400000; /* 4M offset */ 346 t_ram_part.part[0].size = 0x3c00000; /* 60M size */ 347 atags_set_tag(ATAG_RAM_PARTITION, &t_ram_part); 348 } 349 350 void rockchip_pcie_ep_get_firmware(void) 351 { 352 pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_FWDLRDY); 353 pcie_wait_for_fw(); 354 pcie_update_atags(); 355 pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_FWDLDONE); 356 } 357 #endif 358 359 #ifdef CONFIG_ROCKCHIP_RK3588 360 #define BUS_IOC_GPIO3D_IOMUX_SEL_H 0xfd5f807c 361 #define GPIO3_BASE 0xfec40000 362 #define GPIO3_SWPORT_DR_H (GPIO3_BASE + 0x4) 363 #define GPIO3_SWPORT_DDR_H (GPIO3_BASE + 0xc) 364 365 static void pcie_board_init(void) 366 { 367 /* Enable AU5426 buffer chip on EVB4v10 */ 368 /* Set GPIO3D4 to gpio output HIGH mode PCIE20_CLK_PWREN */ 369 writel(0xf << 16, BUS_IOC_GPIO3D_IOMUX_SEL_H); 370 writel(0x10001000, GPIO3_SWPORT_DDR_H); 371 writel(0x10001000, GPIO3_SWPORT_DR_H); 372 udelay(100); 373 } 374 375 #define PHY_MODE_PCIE_AGGREGATION 4 /* PCIe3x4 */ 376 #define PHY_MODE_PCIE_NANBNB 0 /* P1:PCIe3x2 + P0:PCIe3x2 */ 377 #define PHY_MODE_PCIE_NANBBI 1 /* P1:PCIe3x2 + P0:PCIe3x1*2 */ 378 #define PHY_MODE_PCIE_NABINB 2 /* P1:PCIe3x1*2 + P0:PCIe3x2 */ 379 #define PHY_MODE_PCIE_NABIBI 3 /* P1:PCIe3x1*2 + P0:PCIe3x1*2 */ 380 381 #define CRU_BASE_ADDR 0xfd7c0000 382 #define CRU_SOFTRST_CON32 (CRU_BASE_ADDR + 0x0a80) 383 #define CRU_SOFTRST_CON33 (CRU_BASE_ADDR + 0x0a84) 384 #define CRU_SOFTRST_CON34 (CRU_BASE_ADDR + 0x0a88) 385 #define CRU_GATE_CON32 (CRU_BASE_ADDR + 0x0880) 386 #define CRU_GATE_CON33 (CRU_BASE_ADDR + 0x0884) 387 #define CRU_GATE_CON34 (CRU_BASE_ADDR + 0x0888) 388 #define CRU_GATE_CON38 (CRU_BASE_ADDR + 0x0898) 389 #define CRU_GATE_CON39 (CRU_BASE_ADDR + 0x089c) 390 #define PHPTOPCRU_BASE_ADDR 0xfd7c8000 391 #define PHPTOPCRU_SOFTRST_CON00 (PHPTOPCRU_BASE_ADDR + 0x0a00) 392 #define PHPTOPCRU_GATE_CON00 (PHPTOPCRU_BASE_ADDR + 0x0800) 393 #define PCIE3PHY_GRF_BASE 0xfd5b8000 394 #define RK3588_PCIE3PHY_GRF_CMN_CON0 (PCIE3PHY_GRF_BASE + 0x0000) 395 #define PCIE3PHY_GRF_PHY0_CON6 (PCIE3PHY_GRF_BASE + 0x0118) 396 #define PCIE3PHY_GRF_PHY1_CON6 (PCIE3PHY_GRF_BASE + 0x0218) 397 #define PCIE3PHY_GRF_PHY0_LN0_CON1 (PCIE3PHY_GRF_BASE + 0x1004) 398 #define PCIE3PHY_GRF_PHY0_LN1_CON1 (PCIE3PHY_GRF_BASE + 0x1104) 399 #define PCIE3PHY_GRF_PHY1_LN0_CON1 (PCIE3PHY_GRF_BASE + 0x2004) 400 #define PCIE3PHY_GRF_PHY1_LN1_CON1 (PCIE3PHY_GRF_BASE + 0x2104) 401 #define FIREWALL_PCIE_MASTER_SEC 0xfe0300f0 402 #define FIREWALL_PCIE_ACCESS 0xfe586040 403 #define CRU_PHYREF_ALT_GATE_CON (CRU_BASE_ADDR + 0x0c38) 404 #define PMU_PWR_GATE_SFTCON1 0xfd8d8150 405 static void pcie_cru_init(void) 406 { 407 u32 phy0_mplla, phy1_mplla, t0 = 0, t1 = 0; 408 u32 i, timeout = 500; 409 410 /* Enable power domain: PD_PCIE & PD_PHP */ 411 writel(0x1 << 23 | 0x1 << 21, PMU_PWR_GATE_SFTCON1); 412 413 /* FixMe init 3.0 PHY */ 414 /* Phy mode: Aggregation NBNB */ 415 writel((0x7 << 16) | PHY_MODE_PCIE_AGGREGATION, RK3588_PCIE3PHY_GRF_CMN_CON0); 416 printep("PHY Mode 0x%x\n", readl(RK3588_PCIE3PHY_GRF_CMN_CON0) & 7); 417 /* Enable clock and sfreset for Controller and PHY */ 418 writel(0xffff0000, CRU_SOFTRST_CON32); 419 writel(0xffff0000, CRU_SOFTRST_CON33); 420 writel(0xffff0000, CRU_SOFTRST_CON34); 421 writel(0xffff0000, CRU_GATE_CON32); 422 writel(0xffff0000, CRU_GATE_CON33); 423 writel(0xffff0000, CRU_GATE_CON34); 424 writel(0xffff0000, CRU_GATE_CON38); 425 writel(0xffff0000, CRU_GATE_CON39); 426 427 writel((0x1 << 24), PHPTOPCRU_SOFTRST_CON00); 428 writel(0xffff0000, PHPTOPCRU_GATE_CON00); 429 430 /* PHY Reset */ 431 writel((0x1 << 10) | (0x1 << 26), PHPTOPCRU_SOFTRST_CON00); 432 433 udelay(1); 434 435 #ifdef PCIE_ENABLE_SRNS_PLL_REFCLK 436 writel(0x000f0000, CRU_PHYREF_ALT_GATE_CON); 437 438 /* PHY0 & PHY1 use internal clock */ 439 writel(0x0 | (0x1 << 18), PCIE3PHY_GRF_PHY0_CON6); 440 writel(0x0 | (0x1 << 18), PCIE3PHY_GRF_PHY1_CON6); 441 442 /* phy0_rx0_cmn_refclk_mod */ 443 writel((0x0) | (0x1 << 23), PCIE3PHY_GRF_PHY0_LN0_CON1); 444 /* phy1_rx0_cmn_refclk_mod */ 445 writel((0x0) | (0x1 << 23), PCIE3PHY_GRF_PHY0_LN1_CON1); 446 /* phy0_rx0_cmn_refclk_mod */ 447 writel((0x0) | (0x1 << 23), PCIE3PHY_GRF_PHY1_LN0_CON1); 448 /* phy1_rx0_cmn_refclk_mod */ 449 writel((0x0) | (0x1 << 23), PCIE3PHY_GRF_PHY1_LN1_CON1); 450 #endif 451 452 udelay(1000); 453 454 /* Deassert PCIe PMA output clamp mode */ 455 writel((0x1 << 8) | (0x1 << 24), RK3588_PCIE3PHY_GRF_CMN_CON0); 456 457 /* Deassert PHY Reset */ 458 writel((0x1 << 26), PHPTOPCRU_SOFTRST_CON00); 459 460 /* S-Phy: waiting for phy locked */ 461 for (i = 0; i < timeout; i++) { 462 phy0_mplla = readl(PCIE3PHY_GRF_BASE + 0x904); 463 phy1_mplla = readl(PCIE3PHY_GRF_BASE + 0xA04); 464 465 if (phy0_mplla != t0 || phy1_mplla != t1) { 466 printf("RKEP: GRF:904=%x, a04=%x...\n", phy0_mplla, phy1_mplla); 467 468 t0 = phy0_mplla; 469 t1 = phy1_mplla; 470 if (phy0_mplla == 0xF && phy1_mplla == 0xF) 471 break; 472 } 473 474 udelay(10); 475 } 476 477 /* PHY config: no config need for snps3.0phy */ 478 479 /* Enable PCIe Access in firewall and master secure mode */ 480 writel(0xffff0000, FIREWALL_PCIE_MASTER_SEC); 481 writel(0x01800000, FIREWALL_PCIE_ACCESS); 482 } 483 #elif CONFIG_ROCKCHIP_RK3568 484 485 static void pcie_board_init(void) 486 { 487 /* to-do */ 488 } 489 490 static const u16 phy_fw[] = { 491 #include "./../../../drivers/phy/phy-rockchip-snps-pcie3.fw" 492 }; 493 494 #define GRF_PCIE30PHY_RK3568_CON1 0x4 495 #define GRF_PCIE30PHY_RK3568_CON3 0xC 496 #define GRF_PCIE30PHY_RK3568_CON4 0x10 497 #define GRF_PCIE30PHY_RK3568_CON5 0x14 498 #define GRF_PCIE30PHY_RK3568_CON6 0x18 499 #define GRF_PCIE30PHY_RK3568_CON9 0x24 500 #define GRF_PCIE30PHY_RK3568_STATUS0 0x80 501 #define RK3568_SRAM_INIT_DONE(reg) ((reg) & BIT(14)) 502 503 #define PMUCRU_BASE 0xFDD00000 504 #define PMUCRU_PMUGATE_CON02 (PMUCRU_BASE + 0x188) 505 506 #define CRU_BASE 0xFDD20000 507 #define CRU_GATE_CON12 (CRU_BASE + 0x330) 508 #define CRU_GATE_CON13 (CRU_BASE + 0x334) 509 #define CRU_GATE_CON33 (CRU_BASE + 0x384) 510 #define CRU_SOFTRST_CON12 (CRU_BASE + 0x430) 511 #define CRU_SOFTRST_CON27 (CRU_BASE + 0x46c) 512 513 #define PCIE30_PHY_GRF 0xFDCB8000 514 515 void pcie_cru_init(void) 516 { 517 u32 i, reg; 518 void __iomem *mmio = (void __iomem *)0xFE8C0000; 519 520 /* Enable phy and controoler clk */ 521 writel(0xffff0000, PMUCRU_PMUGATE_CON02); 522 writel(0xffff0000, CRU_GATE_CON12); 523 writel(0xffff0000, CRU_GATE_CON13); 524 writel(0xffff0000, CRU_GATE_CON33); 525 writel(0xffff0000, CRU_SOFTRST_CON27); 526 527 writel(0x40004000, CRU_SOFTRST_CON27); 528 writel(0x80008000, PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON9); 529 530 writel((0x1 << 15) | (0x1 << 31), 531 PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON9); //map to access sram 532 533 #ifdef PCIE_ENABLE_SRNS_PLL_REFCLK 534 /* use internal clock */ 535 writel(0x0 | (0x1 << 31), PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON3); 536 537 /* rx0_cmn_refclk_mode disabled */ 538 writel((0x0) | (0x1 << 25), PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON5); 539 /* rx1_cmn_refclk_mode disabled */ 540 writel((0x0) | (0x1 << 25), PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON6); 541 #endif 542 543 writel((0x0 << 14) | (0x1 << (14 + 16)), 544 PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON4); //sdram_ld_done 545 writel((0x0 << 13) | (0x1 << (13 + 16)), 546 PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON4); //sdram_bypass 547 548 writel(0x40000000, CRU_SOFTRST_CON27); 549 550 udelay(5); 551 printf("RKEP: sram initial\n"); 552 while (1) { 553 reg = readl(PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_STATUS0); 554 if (RK3568_SRAM_INIT_DONE(reg)) 555 break; 556 } 557 printf("RKEP: sram init done\n"); 558 559 writel((0x3 << 8) | (0x3 << (8 + 16)), 560 PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON9); //map to access sram 561 for (i = 0; i < ARRAY_SIZE(phy_fw); i++) 562 writel(phy_fw[i], mmio + (i << 2)); 563 564 printf("RKEP: snps pcie3phy FW update! size %ld\n", ARRAY_SIZE(phy_fw)); 565 writel((0x0 << 8) | (0x3 << (8 + 16)), 566 PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON9); 567 writel((0x1 << 14) | (0x1 << (14 + 16)), 568 PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON4); //sdram_ld_done 569 570 writel(0xffff0000, CRU_SOFTRST_CON12); 571 writel(0x100010, PCIE_SNPS_APB_BASE + 0x180); 572 573 udelay(1); 574 } 575 #endif 576 577 static void pcie_ep_init(void) 578 { 579 u32 val; 580 void *dbi_base = (void *)PCIE_SNPS_DBI_BASE; 581 u64 apb_base = PCIE_SNPS_APB_BASE; 582 int i, retries = 0; 583 584 #ifdef PCIE_ENABLE_SRNS_PLL_REFCLK 585 printep("RefClock in SRNS clock mode\n"); 586 #else 587 printep("RefClock in common clock_mode\n"); 588 #endif 589 590 /* 591 * ltssm_enable enhance mode and enable delaying the link training 592 * after Hot Reset 593 */ 594 writel(0x120012, apb_base + 0x180); 595 596 /* Unmask pm_turnoff_int */ 597 writel(0x04000000, apb_base + 0x18); 598 599 /* PortLorgic DBI_RO_WR_EN */ 600 val = readl((dbi_base + 0x8bc)); 601 val |= 0x1; 602 writel(val, dbi_base + 0x8bc); 603 604 reinit: 605 pcie_bar_init(dbi_base); 606 pcie_inbound_config(); 607 608 /* Device PID, DID */ 609 writel(0x1d87, dbi_base + 0x00); 610 writel(0x356a, dbi_base + 0x02); 611 /* Device Class: Processing accelerators */ 612 writel(0x1200, dbi_base + 0x0a); 613 614 pcie_link_set_max_speed(dbi_base, PCI_EXP_LNKCTL2_TLS_8_0GT); 615 616 #ifdef CONFIG_ROCKCHIP_RK3588 617 pcie_link_set_lanes(dbi_base, 4); 618 #elif CONFIG_ROCKCHIP_RK3568 619 pcie_link_set_lanes(dbi_base, 2); 620 #endif 621 622 /* EP mode */ 623 writel(0xf00000, apb_base); 624 udelay(100); 625 626 /* Enable EP mem/io access */ 627 val = readl(dbi_base + 0x4); 628 writel(val | 0x6, dbi_base + 0x4); 629 630 if (retries) /* Set app_dly2_done to enable app_ltssm_enable */ 631 writel(0x80008, apb_base + 0x180); 632 else /* Enable LTSSM */ 633 writel(0xc000c, apb_base); 634 printep("init PCIe fast Link up\n"); 635 pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_LNKRDY); 636 637 /* Waiting for Link up */ 638 while (1) { 639 val = readl(apb_base + 0x300); 640 if (((val & 0x3ffff) & ((0x3 << 16) | 0x11)) == 0x30011) 641 break; 642 mdelay(1); 643 } 644 printep("Link up %x\n", val); 645 mdelay(3); 646 647 /* Wait for link stable */ 648 for (i = 0; i < 10000; i++) { 649 val = readl(apb_base + 0x10); 650 if (val & 0x4) { 651 writel(0x4, apb_base + 0x10); 652 printep("Link is reset, int status misc=%x\n", val); 653 if (retries < 3) { 654 retries++; 655 goto reinit; 656 } else { 657 break; 658 } 659 } 660 udelay(1); 661 } 662 printep("Done\n"); 663 pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_LNKUP); 664 } 665 666 void rockchip_pcie_ep_init(void) 667 { 668 u32 val; 669 670 printf("\nRKEP: Init PCIe EP\n"); 671 pcie_bar0_header_init(); 672 673 #ifdef CONFIG_ROCKCHIP_RK3588 674 writel(0x1 << 23 | 0x1 << 21, PMU_PWR_GATE_SFTCON1); 675 udelay(10); 676 #endif 677 /* Re-in pcie initial */ 678 val = readl(PCIE_SNPS_APB_BASE + 0x300); 679 if (((val & 0x3ffff) & ((0x3 << 16))) == 0x30000) { 680 printf("RKEP: already link up\n"); 681 return; 682 } 683 684 pcie_board_init(); 685 /* CRU and PHY Init */ 686 pcie_cru_init(); 687 688 pcie_ep_init(); 689 } 690