1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2023 Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <spl.h> 8 #include <asm/io.h> 9 #include <asm/arch/cpu.h> 10 #include <asm/arch/hardware.h> 11 #include <asm/arch/ioc_rk3588.h> 12 #include <dt-bindings/clock/rk3588-cru.h> 13 #include <pci.h> 14 #include <asm/arch/rk_atags.h> 15 16 #ifndef CONFIG_SPL_LOAD_FIT_ADDRESS 17 #error "SPL_LOAD_FIT_ADDRESS not defined!" 18 #endif 19 20 #define printep(fmt, ...) \ 21 do { \ 22 printf("RKEP: %d - ", readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x2c) / 24); \ 23 printf(fmt, ##__VA_ARGS__); \ 24 } while (0) 25 26 #ifdef CONFIG_ROCKCHIP_RK3588 27 #define PCIE_SNPS_DBI_BASE 0xf5000000 28 #define PCIE_SNPS_APB_BASE 0xfe150000 29 #define PCIE_SNPS_IATU_BASE 0xa40300000 30 31 #define PCI_RESBAR 0x2e8 32 #elif CONFIG_ROCKCHIP_RK3568 33 #define PCIE_SNPS_DBI_BASE 0xf6000000 34 #define PCIE_SNPS_APB_BASE 0xfe280000 35 #define PCIE_SNPS_IATU_BASE 0x3c0b00000 36 37 #define PCI_RESBAR 0x2b8 38 #else 39 #error "this soc is not support pcie ep!" 40 #endif 41 42 #define RKEP_BAR0_ADDR 0x3c000000 43 #define RKEP_BAR2_ADDR CONFIG_SPL_LOAD_FIT_ADDRESS 44 #define RKEP_BAR0_CMD_ADDR (RKEP_BAR0_ADDR + 0x400) 45 #define RKEP_BOOT_MAGIC 0x524b4550 /* RKEP */ 46 #define RKEP_CMD_LOADER_RUN 0x524b4501 47 48 #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ 49 #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ 50 #define PCI_EXP_LNKCTL2_TLS 0x000f 51 #define PCI_EXP_LNKCAP_SLS 0x0000000f 52 53 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 54 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 55 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 56 57 /* Synopsys-specific PCIe configuration registers */ 58 #define PCIE_PORT_LINK_CONTROL 0x710 59 #define PORT_LINK_MODE_MASK (0x3f << 16) 60 #define PORT_LINK_MODE_1_LANES (0x1 << 16) 61 #define PORT_LINK_MODE_2_LANES (0x3 << 16) 62 #define PORT_LINK_MODE_4_LANES (0x7 << 16) 63 #define PORT_LINK_MODE_8_LANES (0xf << 16) 64 65 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C 66 #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) 67 #define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8) 68 #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) 69 #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8) 70 #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8) 71 #define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8) 72 73 #define PCIE_DIRECT_SPEED_CHANGE (0x1 << 17) 74 75 #define LINK_WAIT_IATU 10000 76 #define PCIE_ATU_ENABLE (0x1 << 31) 77 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30 | 1 << 19) 78 #define PCIE_ATU_UNR_REGION_CTRL1 0x00 79 #define PCIE_ATU_UNR_REGION_CTRL2 0x04 80 #define PCIE_ATU_CPU_ADDR_LOW 0x14 81 #define PCIE_ATU_CPU_ADDR_HIGH 0x18 82 83 /* SRNS: Use Separate refclk(internal clock) instead of from RC */ 84 // #define PCIE_ENABLE_SRNS_PLL_REFCLK 85 86 struct rkpcie_cmd { 87 u32 cmd; 88 u32 size; 89 u32 data[6]; 90 }; 91 92 /* rkep device mode status definition */ 93 #define RKEP_MODE_BOOTROM 1 94 #define RKEP_MODE_LOADER 2 95 #define RKEP_MODE_KERNEL 3 96 97 /* Common status */ 98 #define RKEP_SMODE_INIT 0 99 #define RKEP_SMODE_LNKRDY 1 100 #define RKEP_SMODE_LNKUP 2 101 #define RKEP_SMODE_ERR 0xff 102 /* Firmware download status */ 103 #define RKEP_SMODE_FWDLRDY 0x10 104 #define RKEP_SMODE_FWDLDONE 0x11 105 /* Application status*/ 106 #define RKEP_SMODE_APPRDY 0x20 107 108 struct rkpcie_boot { 109 /* magic: "RKEP" */ 110 u32 magic; 111 u32 version; 112 struct { 113 u16 mode; 114 u16 submode; 115 } devmode; 116 /* Size of ATAGS for cap */ 117 u32 cap_size; 118 struct { 119 u8 cmd; 120 u8 status; 121 /* Error code for current CMD */ 122 u16 opcode; 123 } cmd_status; 124 u32 reserved[2]; 125 /* RK ATAGS, for mem and other info */ 126 struct tag cap; 127 /* offset 0x400 */ 128 struct rkpcie_cmd cmd; 129 }; 130 131 static void pcie_inbound_config(void) 132 { 133 u64 base = PCIE_SNPS_IATU_BASE + 0x100; 134 u32 val; 135 char i; 136 137 /* BAR0: RKEP_BAR0_ADDR */ 138 writel(RKEP_BAR0_ADDR, base + PCIE_ATU_CPU_ADDR_LOW); 139 writel(0, base + PCIE_ATU_CPU_ADDR_HIGH); 140 writel(0, base + PCIE_ATU_UNR_REGION_CTRL1); 141 /* PCIE_ATU_UNR_REGION_CTRL2 */ 142 writel(PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE | (0 << 8), 143 base + PCIE_ATU_UNR_REGION_CTRL2); 144 for (i = 0; i < 5; i++) { 145 val = readl(base + PCIE_ATU_UNR_REGION_CTRL2); 146 if (val & PCIE_ATU_ENABLE) 147 break; 148 udelay(LINK_WAIT_IATU); 149 } 150 printep("BAR0: 0x%x\n", RKEP_BAR0_ADDR); 151 152 /* BAR2: RKEP_BAR2_ADDR */ 153 writel(RKEP_BAR2_ADDR, base + PCIE_ATU_CPU_ADDR_LOW + 0x200); 154 writel(0, base + PCIE_ATU_CPU_ADDR_HIGH + 0x200); 155 writel(0, base + PCIE_ATU_UNR_REGION_CTRL1 + 0x200); 156 writel(PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE | (2 << 8), 157 base + PCIE_ATU_UNR_REGION_CTRL2 + 0x200); 158 for (i = 0; i < 5; i++) { 159 val = readl(base + PCIE_ATU_UNR_REGION_CTRL2 + 0x200); 160 if (val & PCIE_ATU_ENABLE) 161 break; 162 udelay(LINK_WAIT_IATU); 163 } 164 printep("BAR2: 0x%x%x\n", 0, RKEP_BAR2_ADDR); 165 166 /* BAR4 is wired reg, no need iATU */ 167 } 168 169 static int rockchip_pcie_ep_set_bar_flag(void *dbi_base, u32 barno, int flags) 170 { 171 u32 reg; 172 173 reg = PCI_BASE_ADDRESS_0 + (4 * barno); 174 175 /* Disabled the upper 32bits BAR to make a 64bits bar pair */ 176 if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) 177 writel(0, dbi_base + reg + 0x100000 + 4); 178 179 writel(flags, dbi_base + reg); 180 if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) 181 writel(0, dbi_base + reg + 4); 182 183 return 0; 184 } 185 186 static void pcie_bar_init(void *dbi_base) 187 { 188 void *resbar_base; 189 190 writel(0, dbi_base + 0x10); 191 writel(0, dbi_base + 0x14); 192 writel(0, dbi_base + 0x18); 193 writel(0, dbi_base + 0x1c); 194 writel(0, dbi_base + 0x20); 195 writel(0, dbi_base + 0x24); 196 197 /* Disable ASPM */ 198 val = readl(dbi_base + 0x7c); 199 val &= ~(3 << 10); 200 writel(val, dbi_base + 0x7c); 201 202 /* Resize BAR0 to support 4M 32bits */ 203 resbar_base = dbi_base + PCI_RESBAR; 204 writel(0xfffff0, resbar_base + 0x4); 205 writel(0x2c0, resbar_base + 0x8); 206 /* BAR2: 64M 64bits */ 207 writel(0xfffff0, resbar_base + 0x14); 208 writel(0x6c0, resbar_base + 0x18); 209 /* BAR4: Fixed for EP wired register, 1M 32bits */ 210 writel(0xfffff0, resbar_base + 0x24); 211 writel(0xc0, resbar_base + 0x28); 212 /* Set flags */ 213 rockchip_pcie_ep_set_bar_flag(dbi_base, 0, PCI_BASE_ADDRESS_MEM_TYPE_32); 214 rockchip_pcie_ep_set_bar_flag(dbi_base, 2, 215 PCI_BASE_ADDRESS_MEM_PREFETCH | PCI_BASE_ADDRESS_MEM_TYPE_64); 216 rockchip_pcie_ep_set_bar_flag(dbi_base, 4, PCI_BASE_ADDRESS_MEM_TYPE_32); 217 218 /* Close bar1 bar3 bar5 */ 219 writel(0x0, dbi_base + 0x100000 + 0x14); 220 //writel(0x0, dbi_base + 0x100000 + 0x18); 221 writel(0x0, dbi_base + 0x100000 + 0x1c); 222 //writel(0x0, dbi_base + 0x100000 + 0x20); 223 writel(0x0, dbi_base + 0x100000 + 0x24); 224 /* Close ROM BAR */ 225 writel(0x0, dbi_base + 0x100000 + 0x30); 226 } 227 228 static void pcie_bar0_header_init(void) 229 { 230 struct rkpcie_boot *bh = (struct rkpcie_boot *)RKEP_BAR0_ADDR; 231 232 bh->magic = RKEP_BOOT_MAGIC; 233 bh->version = 0x100; 234 bh->devmode.mode = RKEP_MODE_LOADER; 235 bh->devmode.submode = RKEP_SMODE_INIT; 236 bh->cap_size = 0; 237 238 memset((char *)RKEP_BAR0_CMD_ADDR, 0, sizeof(struct rkpcie_cmd)); 239 } 240 241 static void pcie_link_set_max_speed(void *dbi_base, u32 link_gen) 242 { 243 u32 cap, ctrl2, link_speed; 244 u8 offset = 0x70; 245 246 cap = readl(dbi_base + offset + PCI_EXP_LNKCAP); 247 ctrl2 = readl(dbi_base + offset + PCI_EXP_LNKCTL2); 248 ctrl2 &= ~PCI_EXP_LNKCTL2_TLS; 249 250 link_speed = link_gen; 251 252 cap &= ~((u32)PCI_EXP_LNKCAP_SLS); 253 writel(ctrl2 | link_speed, dbi_base + offset + PCI_EXP_LNKCTL2); 254 writel(cap | link_speed, dbi_base + offset + PCI_EXP_LNKCAP); 255 } 256 257 static void pcie_link_set_lanes(void *dbi_base, u32 lanes) 258 { 259 u32 val; 260 261 /* Set the number of lanes */ 262 val = readl(dbi_base + PCIE_PORT_LINK_CONTROL); 263 val &= ~PORT_LINK_MODE_MASK; 264 switch (lanes) { 265 case 1: 266 val |= PORT_LINK_MODE_1_LANES; 267 break; 268 case 2: 269 val |= PORT_LINK_MODE_2_LANES; 270 break; 271 case 4: 272 val |= PORT_LINK_MODE_4_LANES; 273 break; 274 default: 275 printf("RKEP: num-lanes %u: invalid value\n", lanes); 276 return; 277 } 278 writel(val, dbi_base + PCIE_PORT_LINK_CONTROL); 279 280 /* Set link width speed control register */ 281 val = readl(dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); 282 val &= ~PORT_LOGIC_LINK_WIDTH_MASK; 283 switch (lanes) { 284 case 1: 285 val |= PORT_LOGIC_LINK_WIDTH_1_LANES; 286 break; 287 case 2: 288 val |= PORT_LOGIC_LINK_WIDTH_2_LANES; 289 break; 290 case 4: 291 val |= PORT_LOGIC_LINK_WIDTH_4_LANES; 292 break; 293 } 294 295 val |= PCIE_DIRECT_SPEED_CHANGE; 296 297 writel(val, dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); 298 } 299 300 static void pcie_devmode_update(int mode, int submode) 301 { 302 struct rkpcie_boot *bh = (struct rkpcie_boot *)RKEP_BAR0_ADDR; 303 304 bh->devmode.mode = mode; 305 bh->devmode.submode = submode; 306 flush_dcache_range(RKEP_BAR0_ADDR, RKEP_BAR0_ADDR + 64); 307 } 308 309 #ifdef CONFIG_SPL_RAM_DEVICE 310 static void pcie_wait_for_fw(void) 311 { 312 struct rkpcie_cmd *cmd = (struct rkpcie_cmd *)(RKEP_BAR0_CMD_ADDR); 313 int val; 314 int i = 0; 315 316 printep("Link ready! Waiting RC to download Firmware:\n"); 317 printep("Download uboot.img to BAR2+0\n"); 318 printep("Download boot.img to BAR2+0x400000\n"); 319 printep("Send CMD_LOADER_RUN to BAR0+0x400\n"); 320 while (1) { 321 invalidate_dcache_range(RKEP_BAR0_CMD_ADDR, 322 RKEP_BAR0_CMD_ADDR + 32); 323 val = readl(&cmd->cmd); 324 if (val == RKEP_CMD_LOADER_RUN) 325 break; 326 i++; 327 if (!(i % 10)) 328 printep("Waiting for FW, CMD: %x\n", val); 329 mdelay(100); 330 } 331 /* Invalidate Cache for firmware area: BAR2, 64MB */ 332 invalidate_dcache_range(RKEP_BAR2_ADDR, RKEP_BAR2_ADDR + 0x4000000); 333 printep("Firmware Download complete!\n"); 334 } 335 336 static void pcie_update_atags(void) 337 { 338 struct tag_ram_partition t_ram_part; 339 340 if (!atags_is_available()) { 341 printfep("RKEP: No ATAGS data found, create new!\n"); 342 atags_destroy(); 343 } 344 345 /* ram partition */ 346 memset(&t_ram_part, 0, sizeof(t_ram_part)); 347 t_ram_part.version = 0; 348 t_ram_part.count = 1; 349 strcpy(t_ram_part.part[0].name, "boot"); 350 t_ram_part.part[0].start = RKEP_BAR2_ADDR + 0x400000; /* 4M offset */ 351 t_ram_part.part[0].size = 0x3c00000; /* 60M size */ 352 atags_set_tag(ATAG_RAM_PARTITION, &t_ram_part); 353 } 354 355 void rockchip_pcie_ep_get_firmware(void) 356 { 357 pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_FWDLRDY); 358 pcie_wait_for_fw(); 359 pcie_update_atags(); 360 pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_FWDLDONE); 361 } 362 #endif 363 364 #ifdef CONFIG_ROCKCHIP_RK3588 365 #define BUS_IOC_GPIO3D_IOMUX_SEL_H 0xfd5f807c 366 #define GPIO3_BASE 0xfec40000 367 #define GPIO3_SWPORT_DR_H (GPIO3_BASE + 0x4) 368 #define GPIO3_SWPORT_DDR_H (GPIO3_BASE + 0xc) 369 370 static void pcie_board_init(void) 371 { 372 /* Enable AU5426 buffer chip on EVB4v10 */ 373 /* Set GPIO3D4 to gpio output HIGH mode PCIE20_CLK_PWREN */ 374 writel(0xf << 16, BUS_IOC_GPIO3D_IOMUX_SEL_H); 375 writel(0x10001000, GPIO3_SWPORT_DDR_H); 376 writel(0x10001000, GPIO3_SWPORT_DR_H); 377 udelay(100); 378 } 379 380 #define PHY_MODE_PCIE_AGGREGATION 4 /* PCIe3x4 */ 381 #define PHY_MODE_PCIE_NANBNB 0 /* P1:PCIe3x2 + P0:PCIe3x2 */ 382 #define PHY_MODE_PCIE_NANBBI 1 /* P1:PCIe3x2 + P0:PCIe3x1*2 */ 383 #define PHY_MODE_PCIE_NABINB 2 /* P1:PCIe3x1*2 + P0:PCIe3x2 */ 384 #define PHY_MODE_PCIE_NABIBI 3 /* P1:PCIe3x1*2 + P0:PCIe3x1*2 */ 385 386 #define CRU_BASE_ADDR 0xfd7c0000 387 #define CRU_SOFTRST_CON32 (CRU_BASE_ADDR + 0x0a80) 388 #define CRU_SOFTRST_CON33 (CRU_BASE_ADDR + 0x0a84) 389 #define CRU_SOFTRST_CON34 (CRU_BASE_ADDR + 0x0a88) 390 #define CRU_GATE_CON32 (CRU_BASE_ADDR + 0x0880) 391 #define CRU_GATE_CON33 (CRU_BASE_ADDR + 0x0884) 392 #define CRU_GATE_CON34 (CRU_BASE_ADDR + 0x0888) 393 #define CRU_GATE_CON38 (CRU_BASE_ADDR + 0x0898) 394 #define CRU_GATE_CON39 (CRU_BASE_ADDR + 0x089c) 395 #define PHPTOPCRU_BASE_ADDR 0xfd7c8000 396 #define PHPTOPCRU_SOFTRST_CON00 (PHPTOPCRU_BASE_ADDR + 0x0a00) 397 #define PHPTOPCRU_GATE_CON00 (PHPTOPCRU_BASE_ADDR + 0x0800) 398 #define PCIE3PHY_GRF_BASE 0xfd5b8000 399 #define RK3588_PCIE3PHY_GRF_CMN_CON0 (PCIE3PHY_GRF_BASE + 0x0000) 400 #define PCIE3PHY_GRF_PHY0_CON6 (PCIE3PHY_GRF_BASE + 0x0118) 401 #define PCIE3PHY_GRF_PHY1_CON6 (PCIE3PHY_GRF_BASE + 0x0218) 402 #define PCIE3PHY_GRF_PHY0_LN0_CON1 (PCIE3PHY_GRF_BASE + 0x1004) 403 #define PCIE3PHY_GRF_PHY0_LN1_CON1 (PCIE3PHY_GRF_BASE + 0x1104) 404 #define PCIE3PHY_GRF_PHY1_LN0_CON1 (PCIE3PHY_GRF_BASE + 0x2004) 405 #define PCIE3PHY_GRF_PHY1_LN1_CON1 (PCIE3PHY_GRF_BASE + 0x2104) 406 #define FIREWALL_PCIE_MASTER_SEC 0xfe0300f0 407 #define FIREWALL_PCIE_ACCESS 0xfe586040 408 #define CRU_PHYREF_ALT_GATE_CON (CRU_BASE_ADDR + 0x0c38) 409 #define PMU1_GRF_BASE 0xfd58a000 410 #define PMU_PWR_GATE_SFTCON1 0xfd8d8150 411 #define PMU1_IOC_BASE 0xfd5F0000 412 #define CRU_GLB_RST_CON_OFFSET (0xC10U) 413 #define CRU_GLB_SRST_FST_VALUE_OFFSET (0xC08U) 414 415 void pcie_first_reset(void) 416 { 417 printep("Fst Reset\n"); 418 mdelay(1); 419 420 writel(0xFFDF, CRU_BASE_ADDR + CRU_GLB_RST_CON_OFFSET); 421 writel(0xffffffff, PMU1_GRF_BASE + 0x4); // reset width 422 writel(0x30003000, PMU1_GRF_BASE + 0x1c); // pmu1_grf pmu1_ioc hiold 423 writel(0x00f00020, PMU1_IOC_BASE + 0x0); //select tsad_shut_m0 iomux 424 writel(0xFDB9, CRU_BASE_ADDR + CRU_GLB_SRST_FST_VALUE_OFFSET); 425 426 while (1) 427 ; 428 } 429 430 static void pcie_cru_init(void) 431 { 432 u32 phy0_mplla, phy1_mplla, t0 = 0, t1 = 0; 433 u32 i, timeout = 500; 434 435 /* Enable power domain: PD_PCIE & PD_PHP */ 436 writel(0x1 << 23 | 0x1 << 21, PMU_PWR_GATE_SFTCON1); 437 438 /* FixMe init 3.0 PHY */ 439 /* Phy mode: Aggregation NBNB */ 440 writel((0x7 << 16) | PHY_MODE_PCIE_AGGREGATION, RK3588_PCIE3PHY_GRF_CMN_CON0); 441 printep("PHY Mode 0x%x\n", readl(RK3588_PCIE3PHY_GRF_CMN_CON0) & 7); 442 /* Enable clock and sfreset for Controller and PHY */ 443 writel(0xffff0000, CRU_SOFTRST_CON32); 444 writel(0xffff0000, CRU_SOFTRST_CON33); 445 writel(0xffff0000, CRU_SOFTRST_CON34); 446 writel(0xffff0000, CRU_GATE_CON32); 447 writel(0xffff0000, CRU_GATE_CON33); 448 writel(0xffff0000, CRU_GATE_CON34); 449 writel(0xffff0000, CRU_GATE_CON38); 450 writel(0xffff0000, CRU_GATE_CON39); 451 452 writel((0x1 << 24), PHPTOPCRU_SOFTRST_CON00); 453 writel(0xffff0000, PHPTOPCRU_GATE_CON00); 454 455 /* PHY Reset */ 456 writel((0x1 << 10) | (0x1 << 26), PHPTOPCRU_SOFTRST_CON00); 457 458 udelay(1); 459 460 #ifdef PCIE_ENABLE_SRNS_PLL_REFCLK 461 writel(0x000f0000, CRU_PHYREF_ALT_GATE_CON); 462 463 /* PHY0 & PHY1 use internal clock */ 464 writel(0x0 | (0x1 << 18), PCIE3PHY_GRF_PHY0_CON6); 465 writel(0x0 | (0x1 << 18), PCIE3PHY_GRF_PHY1_CON6); 466 467 /* phy0_rx0_cmn_refclk_mod */ 468 writel((0x0) | (0x1 << 23), PCIE3PHY_GRF_PHY0_LN0_CON1); 469 /* phy1_rx0_cmn_refclk_mod */ 470 writel((0x0) | (0x1 << 23), PCIE3PHY_GRF_PHY0_LN1_CON1); 471 /* phy0_rx0_cmn_refclk_mod */ 472 writel((0x0) | (0x1 << 23), PCIE3PHY_GRF_PHY1_LN0_CON1); 473 /* phy1_rx0_cmn_refclk_mod */ 474 writel((0x0) | (0x1 << 23), PCIE3PHY_GRF_PHY1_LN1_CON1); 475 #endif 476 477 udelay(1000); 478 479 /* Deassert PCIe PMA output clamp mode */ 480 writel((0x1 << 8) | (0x1 << 24), RK3588_PCIE3PHY_GRF_CMN_CON0); 481 482 /* Deassert PHY Reset */ 483 writel((0x1 << 26), PHPTOPCRU_SOFTRST_CON00); 484 485 /* S-Phy: waiting for phy locked */ 486 for (i = 0; i < timeout; i++) { 487 phy0_mplla = readl(PCIE3PHY_GRF_BASE + 0x904); 488 phy1_mplla = readl(PCIE3PHY_GRF_BASE + 0xA04); 489 490 if (phy0_mplla != t0 || phy1_mplla != t1) { 491 printep("RKEP: GRF:904=%x, a04=%x...\n", phy0_mplla, phy1_mplla); 492 493 t0 = phy0_mplla; 494 t1 = phy1_mplla; 495 if (phy0_mplla == 0xF && phy1_mplla == 0xF) 496 break; 497 } 498 499 udelay(10); 500 } 501 502 if (i >= timeout) { 503 printep("lock fail\n"); 504 mdelay(1); 505 pcie_first_reset(); 506 } 507 508 /* PHY config: no config need for snps3.0phy */ 509 } 510 511 static void pcie_firewall_init(void) 512 { 513 /* Enable PCIe Access in firewall and master secure mode */ 514 writel(0xffff0000, FIREWALL_PCIE_MASTER_SEC); 515 writel(0x01800000, FIREWALL_PCIE_ACCESS); 516 } 517 #elif CONFIG_ROCKCHIP_RK3568 518 519 static void pcie_board_init(void) 520 { 521 /* to-do */ 522 } 523 524 static const u16 phy_fw[] = { 525 #include "./../../../drivers/phy/phy-rockchip-snps-pcie3.fw" 526 }; 527 528 #define GRF_PCIE30PHY_RK3568_CON1 0x4 529 #define GRF_PCIE30PHY_RK3568_CON3 0xC 530 #define GRF_PCIE30PHY_RK3568_CON4 0x10 531 #define GRF_PCIE30PHY_RK3568_CON5 0x14 532 #define GRF_PCIE30PHY_RK3568_CON6 0x18 533 #define GRF_PCIE30PHY_RK3568_CON9 0x24 534 #define GRF_PCIE30PHY_RK3568_STATUS0 0x80 535 #define RK3568_SRAM_INIT_DONE(reg) ((reg) & BIT(14)) 536 537 #define PMUCRU_BASE 0xFDD00000 538 #define PMUCRU_PMUGATE_CON02 (PMUCRU_BASE + 0x188) 539 540 #define CRU_BASE 0xFDD20000 541 #define CRU_GATE_CON12 (CRU_BASE + 0x330) 542 #define CRU_GATE_CON13 (CRU_BASE + 0x334) 543 #define CRU_GATE_CON33 (CRU_BASE + 0x384) 544 #define CRU_SOFTRST_CON12 (CRU_BASE + 0x430) 545 #define CRU_SOFTRST_CON27 (CRU_BASE + 0x46c) 546 #define CRU_GLB_SRST_FST_OFFSET (0xD4U) 547 548 #define PCIE30_PHY_GRF 0xFDCB8000 549 550 #define SYS_GRF_BASE 0xFDC60000 551 552 void pcie_first_reset(void) 553 { 554 printep("Fst Reset\n"); 555 mdelay(1); 556 557 writel(0x00040004, CRU_BASE + 0x104); 558 writel(0x00700010, CRU_BASE); 559 writel(0x00100010, SYS_GRF_BASE + 0x508); 560 writel(0xFDB9, CRU_BASE + CRU_GLB_SRST_FST_OFFSET); 561 562 while (1) 563 ; 564 } 565 566 void pcie_cru_init(void) 567 { 568 u32 i, reg, timeout = 500; 569 void __iomem *mmio = (void __iomem *)0xFE8C0000; 570 u32 phy0_status0, phy0_status1, t0 = 0, t1 = 0; 571 572 /* Enable phy and controoler clk */ 573 writel(0xffff0000, PMUCRU_PMUGATE_CON02); 574 writel(0xffff0000, CRU_GATE_CON12); 575 writel(0xffff0000, CRU_GATE_CON13); 576 writel(0xffff0000, CRU_GATE_CON33); 577 writel(0xffff0000, CRU_SOFTRST_CON27); 578 579 writel(0x40004000, CRU_SOFTRST_CON27); 580 writel(0x80008000, PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON9); 581 582 writel((0x1 << 15) | (0x1 << 31), 583 PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON9); //map to access sram 584 585 #ifdef PCIE_ENABLE_SRNS_PLL_REFCLK 586 /* use internal clock */ 587 writel(0x0 | (0x1 << 31), PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON3); 588 589 /* rx0_cmn_refclk_mode disabled */ 590 writel((0x0) | (0x1 << 25), PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON5); 591 /* rx1_cmn_refclk_mode disabled */ 592 writel((0x0) | (0x1 << 25), PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON6); 593 #endif 594 595 writel((0x0 << 14) | (0x1 << (14 + 16)), 596 PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON4); //sdram_ld_done 597 writel((0x0 << 13) | (0x1 << (13 + 16)), 598 PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON4); //sdram_bypass 599 600 writel(0x40000000, CRU_SOFTRST_CON27); 601 602 udelay(5); 603 printfep("RKEP: sram initial\n"); 604 while (1) { 605 reg = readl(PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_STATUS0); 606 if (RK3568_SRAM_INIT_DONE(reg)) 607 break; 608 } 609 printfep("RKEP: sram init done\n"); 610 611 writel((0x3 << 8) | (0x3 << (8 + 16)), 612 PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON9); //map to access sram 613 for (i = 0; i < ARRAY_SIZE(phy_fw); i++) 614 writel(phy_fw[i], mmio + (i << 2)); 615 616 printfep("RKEP: snps pcie3phy FW update! size %ld\n", ARRAY_SIZE(phy_fw)); 617 writel((0x0 << 8) | (0x3 << (8 + 16)), 618 PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON9); 619 writel((0x1 << 14) | (0x1 << (14 + 16)), 620 PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON4); //sdram_ld_done 621 622 writel(0xffff0000, CRU_SOFTRST_CON12); 623 writel(0x100010, PCIE_SNPS_APB_BASE + 0x180); 624 625 /* S-Phy: waiting for phy locked */ 626 for (i = 0; i < timeout; i++) { 627 phy0_status0 = readl(PCIE30_PHY_GRF + 0x80); 628 phy0_status1 = readl(PCIE30_PHY_GRF + 0x84); 629 630 if (phy0_status0 != t0 || phy0_status1 != t1) { 631 printep("RKEP: GRF:0x80=%x, 0x84=%x...\n", phy0_status0, phy0_status1); 632 633 t0 = phy0_status0; 634 t1 = phy0_status1; 635 if (RK3568_SRAM_INIT_DONE(phy0_status0)) 636 break; 637 } 638 639 udelay(10); 640 } 641 642 if (i >= timeout) { 643 printep("lock fail\n"); 644 mdelay(1); 645 pcie_first_reset(); 646 } 647 648 udelay(1); 649 } 650 651 static void pcie_firewall_init(void) 652 { 653 } 654 #endif 655 656 static void pcie_ep_init(void) 657 { 658 u32 val; 659 void *dbi_base = (void *)PCIE_SNPS_DBI_BASE; 660 u64 apb_base = PCIE_SNPS_APB_BASE; 661 int i, retries = 0; 662 663 #ifdef PCIE_ENABLE_SRNS_PLL_REFCLK 664 printep("RefClock in SRNS clock mode\n"); 665 #else 666 printep("RefClock in common clock_mode\n"); 667 #endif 668 669 /* 670 * ltssm_enable enhance mode and enable delaying the link training 671 * after Hot Reset 672 */ 673 writel(0x120012, apb_base + 0x180); 674 675 /* Unmask pm_turnoff_int */ 676 writel(0x04000000, apb_base + 0x18); 677 678 /* PortLorgic DBI_RO_WR_EN */ 679 val = readl((dbi_base + 0x8bc)); 680 val |= 0x1; 681 writel(val, dbi_base + 0x8bc); 682 683 reinit: 684 pcie_bar_init(dbi_base); 685 pcie_inbound_config(); 686 687 /* Device PID, DID */ 688 writel(0x1d87, dbi_base + 0x00); 689 writel(0x356a, dbi_base + 0x02); 690 /* Device Class: Processing accelerators */ 691 writel(0x1200, dbi_base + 0x0a); 692 693 pcie_link_set_max_speed(dbi_base, PCI_EXP_LNKCTL2_TLS_8_0GT); 694 695 #ifdef CONFIG_ROCKCHIP_RK3588 696 pcie_link_set_lanes(dbi_base, 4); 697 #elif CONFIG_ROCKCHIP_RK3568 698 pcie_link_set_lanes(dbi_base, 2); 699 #endif 700 701 /* EP mode */ 702 writel(0xf00000, apb_base); 703 udelay(100); 704 705 /* Enable EP mem/io access */ 706 val = readl(dbi_base + 0x4); 707 writel(val | 0x6, dbi_base + 0x4); 708 709 if (retries) /* Set app_dly2_done to enable app_ltssm_enable */ 710 writel(0x80008, apb_base + 0x180); 711 else /* Enable LTSSM */ 712 writel(0xc000c, apb_base); 713 printep("init PCIe fast Link up\n"); 714 pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_LNKRDY); 715 716 /* Waiting for Link up */ 717 while (1) { 718 val = readl(apb_base + 0x300); 719 if (((val & 0x3ffff) & ((0x3 << 16) | 0x11)) == 0x30011) 720 break; 721 mdelay(1); 722 } 723 printep("Link up %x\n", val); 724 mdelay(3); 725 726 /* Wait for link stable */ 727 for (i = 0; i < 10000; i++) { 728 val = readl(apb_base + 0x10); 729 if (val & 0x4) { 730 writel(0x4, apb_base + 0x10); 731 printep("Link is reset, int status misc=%x\n", val); 732 if (retries < 3) { 733 retries++; 734 goto reinit; 735 } else { 736 break; 737 } 738 } 739 udelay(1); 740 } 741 printep("Done\n"); 742 pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_LNKUP); 743 } 744 745 void rockchip_pcie_ep_init(void) 746 { 747 u32 val; 748 749 printf("\nRKEP: Init PCIe EP\n"); 750 pcie_bar0_header_init(); 751 752 #ifdef CONFIG_ROCKCHIP_RK3588 753 writel(0x1 << 23 | 0x1 << 21, PMU_PWR_GATE_SFTCON1); 754 udelay(10); 755 #endif 756 757 pcie_firewall_init(); 758 /* Re-in pcie initial */ 759 val = readl(PCIE_SNPS_APB_BASE + 0x300); 760 if (((val & 0x3ffff) & ((0x3 << 16))) == 0x30000) { 761 printf("RKEP: already link up\n"); 762 pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_LNKUP); 763 return; 764 } 765 766 pcie_board_init(); 767 /* CRU and PHY Init */ 768 pcie_cru_init(); 769 770 pcie_ep_init(); 771 } 772