1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <debug_uart.h> 9 #include <dm.h> 10 #include <key.h> 11 #include <misc.h> 12 #include <ram.h> 13 #include <spl.h> 14 #include <optee_include/OpteeClientInterface.h> 15 #include <asm/arch/bootrom.h> 16 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 17 #include <asm/arch/rk_atags.h> 18 #endif 19 #include <asm/arch/sdram.h> 20 #include <asm/arch/boot_mode.h> 21 #include <asm/arch-rockchip/sys_proto.h> 22 #include <asm/io.h> 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 void board_return_to_bootrom(void) 27 { 28 back_to_bootrom(BROM_BOOT_NEXTSTAGE); 29 } 30 31 __weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { 32 }; 33 34 const char *board_spl_was_booted_from(void) 35 { 36 u32 bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR); 37 const char *bootdevice_ofpath = NULL; 38 39 if (bootdevice_brom_id < ARRAY_SIZE(boot_devices)) 40 bootdevice_ofpath = boot_devices[bootdevice_brom_id]; 41 42 if (bootdevice_ofpath) 43 debug("%s: brom_bootdevice_id %x maps to '%s'\n", 44 __func__, bootdevice_brom_id, bootdevice_ofpath); 45 else 46 debug("%s: failed to resolve brom_bootdevice_id %x\n", 47 __func__, bootdevice_brom_id); 48 49 return bootdevice_ofpath; 50 } 51 52 u32 spl_boot_device(void) 53 { 54 u32 boot_device = BOOT_DEVICE_MMC1; 55 56 #if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \ 57 defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \ 58 defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) 59 return BOOT_DEVICE_SPI; 60 #endif 61 if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)) 62 return BOOT_DEVICE_BOOTROM; 63 64 return boot_device; 65 } 66 67 u32 spl_boot_mode(const u32 boot_device) 68 { 69 return MMCSD_MODE_RAW; 70 } 71 72 __weak void rockchip_stimer_init(void) 73 { 74 /* If Timer already enabled, don't re-init it */ 75 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x10); 76 if ( reg & 0x1 ) 77 return; 78 #ifndef CONFIG_ARM64 79 asm volatile("mcr p15, 0, %0, c14, c0, 0" 80 : : "r"(COUNTER_FREQUENCY)); 81 #endif 82 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + 0x10); 83 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); 84 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); 85 writel(1, CONFIG_ROCKCHIP_STIMER_BASE + 0x10); 86 } 87 88 __weak int arch_cpu_init(void) 89 { 90 return 0; 91 } 92 93 __weak int rk_board_init_f(void) 94 { 95 return 0; 96 } 97 98 #ifndef CONFIG_SPL_LIBGENERIC_SUPPORT 99 void udelay(unsigned long usec) 100 { 101 __udelay(usec); 102 } 103 104 void hang(void) 105 { 106 bootstage_error(BOOTSTAGE_ID_NEED_RESET); 107 for (;;) 108 ; 109 } 110 111 /** 112 * memset - Fill a region of memory with the given value 113 * @s: Pointer to the start of the area. 114 * @c: The byte to fill the area with 115 * @count: The size of the area. 116 * 117 * Do not use memset() to access IO space, use memset_io() instead. 118 */ 119 void *memset(void *s, int c, size_t count) 120 { 121 unsigned long *sl = (unsigned long *)s; 122 char *s8; 123 124 #if !CONFIG_IS_ENABLED(TINY_MEMSET) 125 unsigned long cl = 0; 126 int i; 127 128 /* do it one word at a time (32 bits or 64 bits) while possible */ 129 if (((ulong)s & (sizeof(*sl) - 1)) == 0) { 130 for (i = 0; i < sizeof(*sl); i++) { 131 cl <<= 8; 132 cl |= c & 0xff; 133 } 134 while (count >= sizeof(*sl)) { 135 *sl++ = cl; 136 count -= sizeof(*sl); 137 } 138 } 139 #endif /* fill 8 bits at a time */ 140 s8 = (char *)sl; 141 while (count--) 142 *s8++ = c; 143 144 return s; 145 } 146 #endif 147 148 void board_init_f(ulong dummy) 149 { 150 #ifdef CONFIG_SPL_FRAMEWORK 151 int ret; 152 #if !defined(CONFIG_SUPPORT_TPL) 153 struct udevice *dev; 154 #endif 155 #endif 156 157 rockchip_stimer_init(); 158 #define EARLY_UART 159 #if defined(EARLY_UART) && defined(CONFIG_DEBUG_UART) 160 /* 161 * Debug UART can be used from here if required: 162 * 163 * debug_uart_init(); 164 * printch('a'); 165 * printhex8(0x1234); 166 * printascii("string"); 167 */ 168 debug_uart_init(); 169 printascii("U-Boot SPL board init"); 170 #endif 171 172 #ifdef CONFIG_SPL_FRAMEWORK 173 ret = spl_early_init(); 174 if (ret) { 175 printf("spl_early_init() failed: %d\n", ret); 176 hang(); 177 } 178 #if !defined(CONFIG_SUPPORT_TPL) 179 debug("\nspl:init dram\n"); 180 ret = uclass_get_device(UCLASS_RAM, 0, &dev); 181 if (ret) { 182 printf("DRAM init failed: %d\n", ret); 183 return; 184 } 185 #endif 186 preloader_console_init(); 187 #else 188 /* Some SoCs like rk3036 does not use any frame work */ 189 sdram_init(); 190 #endif 191 192 arch_cpu_init(); 193 rk_board_init_f(); 194 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) 195 back_to_bootrom(BROM_BOOT_NEXTSTAGE); 196 #endif 197 198 } 199 200 #ifdef CONFIG_SPL_LOAD_FIT 201 int board_fit_config_name_match(const char *name) 202 { 203 /* Just empty function now - can't decide what to choose */ 204 debug("%s: %s\n", __func__, name); 205 206 return 0; 207 } 208 #endif 209 210 #ifdef CONFIG_SPL_BOARD_INIT 211 __weak int rk_spl_board_init(void) 212 { 213 return 0; 214 } 215 216 static int setup_led(void) 217 { 218 #ifdef CONFIG_SPL_LED 219 struct udevice *dev; 220 char *led_name; 221 int ret; 222 223 led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led"); 224 if (!led_name) 225 return 0; 226 ret = led_get_by_label(led_name, &dev); 227 if (ret) { 228 debug("%s: get=%d\n", __func__, ret); 229 return ret; 230 } 231 ret = led_set_on(dev, 1); 232 if (ret) 233 return ret; 234 #endif 235 236 return 0; 237 } 238 239 void spl_board_init(void) 240 { 241 int ret; 242 243 ret = setup_led(); 244 245 if (ret) { 246 debug("LED ret=%d\n", ret); 247 hang(); 248 } 249 250 rk_spl_board_init(); 251 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) 252 back_to_bootrom(BROM_BOOT_NEXTSTAGE); 253 #endif 254 return; 255 } 256 #endif 257 258 void spl_perform_fixups(struct spl_image_info *spl_image) 259 { 260 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 261 atags_set_bootdev_by_spl_bootdevice(spl_image->boot_device); 262 #endif 263 return; 264 } 265 266 #ifdef CONFIG_SPL_KERNEL_BOOT 267 static int spl_rockchip_dnl_key_pressed(void) 268 { 269 #if defined(CONFIG_SPL_INPUT) 270 return key_read(KEY_VOLUMEUP); 271 #else 272 return 0; 273 #endif 274 } 275 276 void spl_next_stage(struct spl_image_info *spl) 277 { 278 uint32_t reg_boot_mode; 279 280 if (spl_rockchip_dnl_key_pressed()) { 281 spl->next_stage = SPL_NEXT_STAGE_UBOOT; 282 return; 283 } 284 285 reg_boot_mode = readl((void *)CONFIG_ROCKCHIP_BOOT_MODE_REG); 286 switch (reg_boot_mode) { 287 case BOOT_COLD: 288 case BOOT_PANIC: 289 case BOOT_WATCHDOG: 290 case BOOT_NORMAL: 291 spl->next_stage = SPL_NEXT_STAGE_KERNEL; 292 break; 293 default: 294 spl->next_stage = SPL_NEXT_STAGE_UBOOT; 295 } 296 } 297 #endif 298 299 void spl_hang_reset(void) 300 { 301 printf("# Reset the board to bootrom #\n"); 302 #if defined(CONFIG_SPL_SYSRESET) && defined(CONFIG_SPL_DRIVERS_MISC_SUPPORT) 303 writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG); 304 do_reset(NULL, 0, 0, NULL); 305 #endif 306 } 307 308 #ifdef CONFIG_SPL_FIT_ROLLBACK_PROTECT 309 int fit_read_otp_rollback_index(uint32_t fit_index, uint32_t *otp_index) 310 { 311 int ret = 0; 312 313 *otp_index = 0; 314 #if defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP_V2) 315 struct udevice *dev; 316 u32 index, i, otp_version; 317 u32 bit_count; 318 319 dev = misc_otp_get_device(OTP_S); 320 if (!dev) 321 return -ENODEV; 322 323 otp_version = 0; 324 for (i = 0; i < OTP_UBOOT_ROLLBACK_WORDS; i++) { 325 if (misc_otp_read(dev, 4 * 326 (OTP_UBOOT_ROLLBACK_OFFSET + i), 327 &index, 328 4)) { 329 printf("Can't read rollback index\n"); 330 return -EIO; 331 } 332 bit_count = fls(index); 333 otp_version += bit_count; 334 } 335 *otp_index = otp_version; 336 #endif 337 338 return ret; 339 } 340 341 static int fit_write_otp_rollback_index(u32 fit_index) 342 { 343 #if defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP_V2) 344 struct udevice *dev; 345 u32 index, i, otp_index; 346 347 if (!fit_index) 348 return 0; 349 350 if (fit_index > OTP_UBOOT_ROLLBACK_WORDS * 32) 351 return -EINVAL; 352 353 dev = misc_otp_get_device(OTP_S); 354 if (!dev) 355 return -ENODEV; 356 357 if (fit_read_otp_rollback_index(fit_index, &otp_index)) 358 return -EIO; 359 360 if (otp_index < fit_index) { 361 /* Write new SW version to otp */ 362 for (i = 0; i < OTP_UBOOT_ROLLBACK_WORDS; i++) { 363 /* convert to base-1 representation */ 364 index = 0xffffffff >> (OTP_ALL_ONES_NUM_BITS - 365 min(fit_index, (u32)OTP_ALL_ONES_NUM_BITS)); 366 fit_index -= min(fit_index, 367 (u32)OTP_ALL_ONES_NUM_BITS); 368 if (index) { 369 if (misc_otp_write(dev, 4 * 370 (OTP_UBOOT_ROLLBACK_OFFSET + i), 371 &index, 372 4)) { 373 printf("Can't write rollback index\n"); 374 return -EIO; 375 } 376 } 377 } 378 } 379 #endif 380 381 return 0; 382 } 383 #endif 384 385 int spl_board_prepare_for_jump(struct spl_image_info *spl_image) 386 { 387 #ifdef CONFIG_SPL_FIT_ROLLBACK_PROTECT 388 int ret; 389 390 ret = fit_write_otp_rollback_index(gd->rollback_index); 391 if (ret) { 392 panic("Failed to write fit rollback index %d, ret=%d", 393 gd->rollback_index, ret); 394 } 395 #endif 396 return 0; 397 } 398