1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <version.h> 9 #include <boot_rkimg.h> 10 #include <debug_uart.h> 11 #include <dm.h> 12 #include <key.h> 13 #include <led.h> 14 #include <misc.h> 15 #include <ram.h> 16 #include <spl.h> 17 #include <optee_include/OpteeClientInterface.h> 18 #include <power/fuel_gauge.h> 19 #include <asm/arch/bootrom.h> 20 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 21 #include <asm/arch/rk_atags.h> 22 #endif 23 #include <asm/arch/pcie_ep_boot.h> 24 #include <asm/arch/sdram.h> 25 #include <asm/arch/boot_mode.h> 26 #include <asm/arch-rockchip/sys_proto.h> 27 #include <asm/io.h> 28 #include <asm/arch/param.h> 29 #include <asm/arch/rk_hwid.h> 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 void board_return_to_bootrom(void) 34 { 35 back_to_bootrom(BROM_BOOT_NEXTSTAGE); 36 } 37 38 __weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { 39 }; 40 41 const char *board_spl_was_booted_from(void) 42 { 43 u32 bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR); 44 const char *bootdevice_ofpath = NULL; 45 46 if ((bootdevice_brom_id & BROM_DOWNLOAD_MASK) == BROM_DOWNLOAD_MASK) 47 bootdevice_brom_id = BROM_BOOTSOURCE_USB; 48 49 bootdevice_brom_id = bootdevice_brom_id & BROM_BOOTSOURCE_MASK; 50 if (bootdevice_brom_id < ARRAY_SIZE(boot_devices)) 51 bootdevice_ofpath = boot_devices[bootdevice_brom_id]; 52 53 if (bootdevice_ofpath) 54 debug("%s: brom_bootdevice_id %x maps to '%s'\n", 55 __func__, bootdevice_brom_id, bootdevice_ofpath); 56 else 57 debug("%s: failed to resolve brom_bootdevice_id %x\n", 58 __func__, bootdevice_brom_id); 59 60 return bootdevice_ofpath; 61 } 62 63 u32 spl_boot_device(void) 64 { 65 u32 boot_device = BOOT_DEVICE_MMC1; 66 67 #if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \ 68 defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \ 69 defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) 70 return BOOT_DEVICE_SPI; 71 #endif 72 if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)) 73 return BOOT_DEVICE_BOOTROM; 74 75 return boot_device; 76 } 77 78 u32 spl_boot_mode(const u32 boot_device) 79 { 80 return MMCSD_MODE_RAW; 81 } 82 83 __weak void rockchip_stimer_init(void) 84 { 85 /* If Timer already enabled, don't re-init it */ 86 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x10); 87 if ( reg & 0x1 ) 88 return; 89 #ifdef COUNTER_FREQUENCY 90 #ifndef CONFIG_ARM64 91 asm volatile("mcr p15, 0, %0, c14, c0, 0" 92 : : "r"(COUNTER_FREQUENCY)); 93 #endif 94 #endif 95 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + 0x10); 96 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); 97 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); 98 writel(1, CONFIG_ROCKCHIP_STIMER_BASE + 0x10); 99 } 100 101 __weak int arch_cpu_init(void) 102 { 103 return 0; 104 } 105 106 __weak int rk_board_init_f(void) 107 { 108 return 0; 109 } 110 111 #ifndef CONFIG_SPL_LIBGENERIC_SUPPORT 112 void udelay(unsigned long usec) 113 { 114 __udelay(usec); 115 } 116 117 void hang(void) 118 { 119 bootstage_error(BOOTSTAGE_ID_NEED_RESET); 120 for (;;) 121 ; 122 } 123 124 /** 125 * memset - Fill a region of memory with the given value 126 * @s: Pointer to the start of the area. 127 * @c: The byte to fill the area with 128 * @count: The size of the area. 129 * 130 * Do not use memset() to access IO space, use memset_io() instead. 131 */ 132 void *memset(void *s, int c, size_t count) 133 { 134 unsigned long *sl = (unsigned long *)s; 135 char *s8; 136 137 #if !CONFIG_IS_ENABLED(TINY_MEMSET) 138 unsigned long cl = 0; 139 int i; 140 141 /* do it one word at a time (32 bits or 64 bits) while possible */ 142 if (((ulong)s & (sizeof(*sl) - 1)) == 0) { 143 for (i = 0; i < sizeof(*sl); i++) { 144 cl <<= 8; 145 cl |= c & 0xff; 146 } 147 while (count >= sizeof(*sl)) { 148 *sl++ = cl; 149 count -= sizeof(*sl); 150 } 151 } 152 #endif /* fill 8 bits at a time */ 153 s8 = (char *)sl; 154 while (count--) 155 *s8++ = c; 156 157 return s; 158 } 159 #endif 160 161 #ifdef CONFIG_SPL_DM_RESET 162 static void brom_download(void) 163 { 164 if (gd->console_evt == 0x02) { 165 printf("ctrl+b: Bootrom download!\n"); 166 writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG); 167 do_reset(NULL, 0, 0, NULL); 168 } 169 } 170 #endif 171 172 static void spl_hotkey_init(void) 173 { 174 /* If disable console, skip getting uart reg */ 175 if (!gd || gd->flags & GD_FLG_DISABLE_CONSOLE) 176 return; 177 if (!gd->have_console) 178 return; 179 180 /* serial uclass only exists when enable CONFIG_SPL_FRAMEWORK */ 181 #ifdef CONFIG_SPL_FRAMEWORK 182 if (serial_tstc()) { 183 gd->console_evt = serial_getc(); 184 #else 185 if (debug_uart_tstc()) { 186 gd->console_evt = debug_uart_getc(); 187 #endif 188 if (gd->console_evt <= 0x1a) /* 'z' */ 189 printf("SPL Hotkey: ctrl+%c\n", 190 gd->console_evt + 'a' - 1); 191 } 192 193 return; 194 } 195 196 void board_init_f(ulong dummy) 197 { 198 #ifdef CONFIG_SPL_FRAMEWORK 199 int ret; 200 #if !defined(CONFIG_SUPPORT_TPL) 201 struct udevice *dev; 202 #endif 203 #endif 204 gd->flags = dummy; 205 rockchip_stimer_init(); 206 #define EARLY_UART 207 #if defined(EARLY_UART) && defined(CONFIG_DEBUG_UART) 208 /* 209 * Debug UART can be used from here if required: 210 * 211 * debug_uart_init(); 212 * printch('a'); 213 * printhex8(0x1234); 214 * printascii("string"); 215 */ 216 if (!gd->serial.using_pre_serial && 217 !(gd->flags & GD_FLG_DISABLE_CONSOLE)) 218 debug_uart_init(); 219 printascii("U-Boot SPL board init"); 220 #endif 221 gd->sys_start_tick = get_ticks(); 222 #ifdef CONFIG_SPL_PCIE_EP_SUPPORT 223 rockchip_pcie_ep_init(); 224 #endif 225 #ifdef CONFIG_SPL_FRAMEWORK 226 ret = spl_early_init(); 227 if (ret) { 228 printf("spl_early_init() failed: %d\n", ret); 229 hang(); 230 } 231 #if !defined(CONFIG_SUPPORT_TPL) 232 debug("\nspl:init dram\n"); 233 ret = uclass_get_device(UCLASS_RAM, 0, &dev); 234 if (ret) { 235 printf("DRAM init failed: %d\n", ret); 236 return; 237 } 238 #endif 239 preloader_console_init(); 240 #else 241 /* Some SoCs like rk3036 does not use any frame work */ 242 sdram_init(); 243 #endif 244 /* Get hotkey and store in gd */ 245 spl_hotkey_init(); 246 #ifdef CONFIG_SPL_DM_RESET 247 brom_download(); 248 #endif 249 arch_cpu_init(); 250 rk_board_init_f(); 251 #if defined(CONFIG_SPL_RAM_DEVICE) && defined(CONFIG_SPL_PCIE_EP_SUPPORT) 252 rockchip_pcie_ep_get_firmware(); 253 #endif 254 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) 255 back_to_bootrom(BROM_BOOT_NEXTSTAGE); 256 #endif 257 258 } 259 260 #ifdef CONFIG_SPL_LOAD_FIT 261 int board_fit_config_name_match(const char *name) 262 { 263 /* Just empty function now - can't decide what to choose */ 264 debug("%s: %s\n", __func__, name); 265 266 return 0; 267 } 268 #endif 269 270 int board_init_f_boot_flags(void) 271 { 272 int boot_flags = 0; 273 274 #ifdef CONFIG_ARM64 275 asm volatile("mrs %0, cntfrq_el0" : "=r" (gd->arch.timer_rate_hz)); 276 #else 277 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (gd->arch.timer_rate_hz)); 278 #endif 279 280 #if CONFIG_IS_ENABLED(FPGA_ROCKCHIP) 281 arch_fpga_init(); 282 #endif 283 #ifdef CONFIG_PSTORE 284 param_parse_pstore(); 285 #endif 286 /* pre-loader serial */ 287 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) && \ 288 defined(CONFIG_ROCKCHIP_PRELOADER_ATAGS) 289 struct tag *t; 290 291 t = atags_get_tag(ATAG_SERIAL); 292 if (t) { 293 gd->serial.using_pre_serial = 1; 294 gd->serial.enable = t->u.serial.enable; 295 gd->serial.baudrate = t->u.serial.baudrate; 296 gd->serial.addr = t->u.serial.addr; 297 gd->serial.id = t->u.serial.id; 298 gd->baudrate = t->u.serial.baudrate; 299 if (!t->u.serial.enable) 300 boot_flags |= GD_FLG_DISABLE_CONSOLE; 301 debug("preloader: enable=%d, addr=0x%x, baudrate=%d, id=%d\n", 302 t->u.serial.enable, (u32)t->u.serial.addr, 303 t->u.serial.baudrate, t->u.serial.id); 304 } else 305 #endif 306 { 307 gd->baudrate = CONFIG_BAUDRATE; 308 gd->serial.baudrate = CONFIG_BAUDRATE; 309 gd->serial.addr = CONFIG_DEBUG_UART_BASE; 310 } 311 312 /* The highest priority to turn off (override) console */ 313 #if defined(CONFIG_DISABLE_CONSOLE) 314 boot_flags |= GD_FLG_DISABLE_CONSOLE; 315 #endif 316 317 return boot_flags; 318 } 319 320 #ifdef CONFIG_SPL_BOARD_INIT 321 __weak int rk_spl_board_init(void) 322 { 323 return 0; 324 } 325 326 static int setup_led(void) 327 { 328 #ifdef CONFIG_SPL_LED 329 struct udevice *dev; 330 char *led_name; 331 int ret; 332 333 led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led"); 334 if (!led_name) 335 return 0; 336 ret = led_get_by_label(led_name, &dev); 337 if (ret) { 338 debug("%s: get=%d\n", __func__, ret); 339 return ret; 340 } 341 ret = led_set_state(dev, LEDST_ON); 342 if (ret) 343 return ret; 344 #endif 345 346 return 0; 347 } 348 349 void spl_board_init(void) 350 { 351 int ret; 352 353 ret = setup_led(); 354 355 if (ret) { 356 debug("LED ret=%d\n", ret); 357 hang(); 358 } 359 360 rk_spl_board_init(); 361 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) 362 back_to_bootrom(BROM_BOOT_NEXTSTAGE); 363 #endif 364 return; 365 } 366 #endif 367 368 #ifdef CONFIG_SPL_KERNEL_BOOT 369 static int spl_rockchip_dnl_key_pressed(void) 370 { 371 #if defined(CONFIG_SPL_INPUT) 372 return key_read(KEY_VOLUMEUP); 373 #else 374 return 0; 375 #endif 376 } 377 378 #ifdef CONFIG_SPL_DM_FUEL_GAUGE 379 bool spl_is_low_power(void) 380 { 381 struct udevice *dev; 382 int ret, voltage; 383 384 ret = uclass_get_device(UCLASS_FG, 0, &dev); 385 if (ret) { 386 debug("Get charge display failed, ret=%d\n", ret); 387 return false; 388 } 389 390 voltage = fuel_gauge_get_voltage(dev); 391 if (voltage >= CONFIG_SPL_POWER_LOW_VOLTAGE_THRESHOLD) 392 return false; 393 394 return true; 395 } 396 #endif 397 398 void spl_next_stage(struct spl_image_info *spl) 399 { 400 const char *reason[] = { "Recovery key", "Ctrl+c", "LowPwr", "Other" }; 401 uint32_t reg_boot_mode; 402 int i = 0; 403 404 if (spl_rockchip_dnl_key_pressed()) { 405 i = 0; 406 spl->next_stage = SPL_NEXT_STAGE_UBOOT; 407 goto out; 408 } 409 410 if (gd->console_evt == 0x03) { 411 i = 1; 412 spl->next_stage = SPL_NEXT_STAGE_UBOOT; 413 goto out; 414 } 415 416 #ifdef CONFIG_SPL_DM_FUEL_GAUGE 417 if (spl_is_low_power()) { 418 i = 2; 419 spl->next_stage = SPL_NEXT_STAGE_UBOOT; 420 goto out; 421 } 422 #endif 423 424 reg_boot_mode = readl((void *)CONFIG_ROCKCHIP_BOOT_MODE_REG); 425 switch (reg_boot_mode) { 426 case BOOT_LOADER: 427 case BOOT_FASTBOOT: 428 case BOOT_CHARGING: 429 case BOOT_UMS: 430 case BOOT_DFU: 431 i = 3; 432 spl->next_stage = SPL_NEXT_STAGE_UBOOT; 433 break; 434 default: 435 spl->next_stage = SPL_NEXT_STAGE_KERNEL; 436 } 437 438 out: 439 if (spl->next_stage == SPL_NEXT_STAGE_UBOOT) 440 printf("Enter uboot reason: %s\n", reason[i]); 441 442 return; 443 } 444 445 const char *spl_kernel_partition(struct spl_image_info *spl, 446 struct spl_load_info *info) 447 { 448 struct bootloader_message *bmsg = NULL; 449 u32 boot_mode; 450 int ret, cnt; 451 u32 sector = 0; 452 453 #ifdef CONFIG_SPL_LIBDISK_SUPPORT 454 disk_partition_t part_info; 455 456 ret = part_get_info_by_name(info->dev, PART_MISC, &part_info); 457 if (ret >= 0) 458 sector = part_info.start; 459 #else 460 sector = CONFIG_SPL_MISC_SECTOR; 461 #endif 462 if (sector) { 463 cnt = DIV_ROUND_UP(sizeof(*bmsg), info->bl_len); 464 bmsg = memalign(ARCH_DMA_MINALIGN, cnt * info->bl_len); 465 ret = info->read(info, sector + BCB_MESSAGE_BLK_OFFSET, 466 cnt, bmsg); 467 if (ret == cnt && !strcmp(bmsg->command, "boot-recovery")) { 468 free(bmsg); 469 return PART_RECOVERY; 470 } else { 471 free(bmsg); 472 } 473 } 474 475 boot_mode = readl((void *)CONFIG_ROCKCHIP_BOOT_MODE_REG); 476 477 return (boot_mode == BOOT_RECOVERY) ? PART_RECOVERY : PART_BOOT; 478 } 479 480 __weak void spl_fdt_fixup_memory(struct spl_image_info *spl_image) 481 { 482 void *blob = spl_image->fdt_addr; 483 struct tag *t; 484 u64 start[CONFIG_NR_DRAM_BANKS]; 485 u64 size[CONFIG_NR_DRAM_BANKS]; 486 int i, count, err; 487 488 err = fdt_check_header(blob); 489 if (err < 0) { 490 printf("Invalid dtb\n"); 491 return; 492 } 493 494 /* Fixup memory node based on ddr_mem atags */ 495 t = atags_get_tag(ATAG_DDR_MEM); 496 if (t && t->u.ddr_mem.count) { 497 count = t->u.ddr_mem.count; 498 for (i = 0; i < count; i++) { 499 start[i] = t->u.ddr_mem.bank[i]; 500 size[i] = t->u.ddr_mem.bank[i + count]; 501 if (size[i] == 0) 502 continue; 503 debug("Adding bank: 0x%08llx - 0x%08llx (size: 0x%08llx)\n", 504 start[i], start[i] + size[i], size[i]); 505 } 506 507 fdt_increase_size(blob, 512); 508 509 err = fdt_fixup_memory_banks(blob, start, size, count); 510 if (err < 0) { 511 printf("Fixup kernel dtb memory node failed: %s\n", fdt_strerror(err)); 512 return; 513 } 514 } 515 516 return; 517 } 518 519 #if defined(CONFIG_SPL_ROCKCHIP_HWID_DTB) 520 int spl_find_hwid_dtb(const char *fdt_name) 521 { 522 hwid_init_data(); 523 524 return hwid_dtb_is_available(fdt_name); 525 } 526 #endif 527 #endif 528 529 void spl_perform_fixups(struct spl_image_info *spl_image) 530 { 531 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 532 atags_set_bootdev_by_spl_bootdevice(spl_image->boot_device); 533 #ifdef BUILD_SPL_TAG 534 atags_set_shared_fwver(FW_SPL, "spl-"BUILD_SPL_TAG); 535 #endif 536 #endif 537 #if defined(CONFIG_SPL_KERNEL_BOOT) 538 if (spl_image->next_stage == SPL_NEXT_STAGE_KERNEL) 539 spl_fdt_fixup_memory(spl_image); 540 #endif 541 return; 542 } 543 544 void spl_hang_reset(void) 545 { 546 printf("# Reset the board to bootrom #\n"); 547 #if defined(CONFIG_SPL_SYSRESET) && defined(CONFIG_SPL_DRIVERS_MISC_SUPPORT) 548 /* reset is available after dm setup */ 549 if (gd->flags & GD_FLG_SPL_EARLY_INIT) { 550 writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG); 551 do_reset(NULL, 0, 0, NULL); 552 } 553 #endif 554 } 555 556 #ifdef CONFIG_SPL_FIT_ROLLBACK_PROTECT 557 int fit_read_otp_rollback_index(uint32_t fit_index, uint32_t *otp_index) 558 { 559 int ret = 0; 560 561 *otp_index = 0; 562 #if defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP) 563 struct udevice *dev; 564 u32 index, i, otp_version; 565 u32 bit_count; 566 567 dev = misc_otp_get_device(OTP_S); 568 if (!dev) 569 return -ENODEV; 570 571 otp_version = 0; 572 for (i = 0; i < OTP_UBOOT_ROLLBACK_WORDS; i++) { 573 if (misc_otp_read(dev, OTP_UBOOT_ROLLBACK_OFFSET + i * 4, 574 &index, 575 4)) { 576 printf("Can't read rollback index\n"); 577 return -EIO; 578 } 579 580 bit_count = fls(index); 581 otp_version += bit_count; 582 } 583 *otp_index = otp_version; 584 #endif 585 586 return ret; 587 } 588 589 static int fit_write_otp_rollback_index(u32 fit_index) 590 { 591 #if defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP) 592 struct udevice *dev; 593 u32 index, i, otp_index; 594 595 if (!fit_index) 596 return 0; 597 598 if (fit_index > OTP_UBOOT_ROLLBACK_WORDS * 32) 599 return -EINVAL; 600 601 dev = misc_otp_get_device(OTP_S); 602 if (!dev) 603 return -ENODEV; 604 605 if (fit_read_otp_rollback_index(fit_index, &otp_index)) 606 return -EIO; 607 608 if (otp_index < fit_index) { 609 /* Write new SW version to otp */ 610 for (i = 0; i < OTP_UBOOT_ROLLBACK_WORDS; i++) { 611 /* 612 * If fit_index is equal to 0, then execute 0xffffffff >> 32. 613 * But the operand can only be 0 - 31. The "0xffffffff >> 32" is 614 * actually be "0xffffffff >> 0". 615 */ 616 if (!fit_index) 617 break; 618 /* convert to base-1 representation */ 619 index = 0xffffffff >> (OTP_ALL_ONES_NUM_BITS - 620 min(fit_index, (u32)OTP_ALL_ONES_NUM_BITS)); 621 fit_index -= min(fit_index, 622 (u32)OTP_ALL_ONES_NUM_BITS); 623 if (index) { 624 if (misc_otp_write(dev, OTP_UBOOT_ROLLBACK_OFFSET + i * 4, 625 &index, 626 4)) { 627 printf("Can't write rollback index\n"); 628 return -EIO; 629 } 630 } 631 } 632 } 633 #endif 634 635 return 0; 636 } 637 #endif 638 639 int spl_board_prepare_for_jump(struct spl_image_info *spl_image) 640 { 641 #ifdef CONFIG_SPL_FIT_ROLLBACK_PROTECT 642 int ret; 643 644 ret = fit_write_otp_rollback_index(gd->rollback_index); 645 if (ret) { 646 panic("Failed to write fit rollback index %d, ret=%d", 647 gd->rollback_index, ret); 648 } 649 #endif 650 651 #ifdef CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS 652 misc_decompress_cleanup(); 653 #endif 654 return 0; 655 } 656