xref: /rk3399_rockchip-uboot/arch/arm/mach-rockchip/spl.c (revision e66d4537dbd86d2c766c7745e41d41fd88ae2b83) 
1 /*
2  * (C) Copyright 2018 Rockchip Electronics Co., Ltd
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <boot_rkimg.h>
9 #include <debug_uart.h>
10 #include <dm.h>
11 #include <key.h>
12 #include <led.h>
13 #include <misc.h>
14 #include <ram.h>
15 #include <spl.h>
16 #include <optee_include/OpteeClientInterface.h>
17 #include <asm/arch/bootrom.h>
18 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS
19 #include <asm/arch/rk_atags.h>
20 #endif
21 #include <asm/arch/sdram.h>
22 #include <asm/arch/boot_mode.h>
23 #include <asm/arch-rockchip/sys_proto.h>
24 #include <asm/io.h>
25 
26 DECLARE_GLOBAL_DATA_PTR;
27 
28 void board_return_to_bootrom(void)
29 {
30 	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
31 }
32 
33 __weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
34 };
35 
36 const char *board_spl_was_booted_from(void)
37 {
38 	u32  bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR);
39 	const char *bootdevice_ofpath = NULL;
40 
41 	if (bootdevice_brom_id < ARRAY_SIZE(boot_devices))
42 		bootdevice_ofpath = boot_devices[bootdevice_brom_id];
43 
44 	if (bootdevice_ofpath)
45 		debug("%s: brom_bootdevice_id %x maps to '%s'\n",
46 		      __func__, bootdevice_brom_id, bootdevice_ofpath);
47 	else
48 		debug("%s: failed to resolve brom_bootdevice_id %x\n",
49 		      __func__, bootdevice_brom_id);
50 
51 	return bootdevice_ofpath;
52 }
53 
54 u32 spl_boot_device(void)
55 {
56 	u32 boot_device = BOOT_DEVICE_MMC1;
57 
58 #if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
59 		defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
60 		defined(CONFIG_TARGET_CHROMEBOOK_MINNIE)
61 	return BOOT_DEVICE_SPI;
62 #endif
63 	if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM))
64 		return BOOT_DEVICE_BOOTROM;
65 
66 	return boot_device;
67 }
68 
69 u32 spl_boot_mode(const u32 boot_device)
70 {
71 	return MMCSD_MODE_RAW;
72 }
73 
74 __weak void rockchip_stimer_init(void)
75 {
76 	/* If Timer already enabled, don't re-init it */
77 	u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x10);
78 	if ( reg & 0x1 )
79 		return;
80 #ifndef CONFIG_ARM64
81 	asm volatile("mcr p15, 0, %0, c14, c0, 0"
82 		     : : "r"(COUNTER_FREQUENCY));
83 #endif
84 	writel(0, CONFIG_ROCKCHIP_STIMER_BASE + 0x10);
85 	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
86 	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
87 	writel(1, CONFIG_ROCKCHIP_STIMER_BASE + 0x10);
88 }
89 
90 __weak int arch_cpu_init(void)
91 {
92 	return 0;
93 }
94 
95 __weak int rk_board_init_f(void)
96 {
97 	return 0;
98 }
99 
100 #ifndef CONFIG_SPL_LIBGENERIC_SUPPORT
101 void udelay(unsigned long usec)
102 {
103 	__udelay(usec);
104 }
105 
106 void hang(void)
107 {
108 	bootstage_error(BOOTSTAGE_ID_NEED_RESET);
109 	for (;;)
110 		;
111 }
112 
113 /**
114  * memset - Fill a region of memory with the given value
115  * @s: Pointer to the start of the area.
116  * @c: The byte to fill the area with
117  * @count: The size of the area.
118  *
119  * Do not use memset() to access IO space, use memset_io() instead.
120  */
121 void *memset(void *s, int c, size_t count)
122 {
123 	unsigned long *sl = (unsigned long *)s;
124 	char *s8;
125 
126 #if !CONFIG_IS_ENABLED(TINY_MEMSET)
127 	unsigned long cl = 0;
128 	int i;
129 
130 	/* do it one word at a time (32 bits or 64 bits) while possible */
131 	if (((ulong)s & (sizeof(*sl) - 1)) == 0) {
132 		for (i = 0; i < sizeof(*sl); i++) {
133 			cl <<= 8;
134 			cl |= c & 0xff;
135 		}
136 		while (count >= sizeof(*sl)) {
137 			*sl++ = cl;
138 			count -= sizeof(*sl);
139 		}
140 	}
141 #endif /* fill 8 bits at a time */
142 	s8 = (char *)sl;
143 	while (count--)
144 		*s8++ = c;
145 
146 	return s;
147 }
148 #endif
149 
150 void board_init_f(ulong dummy)
151 {
152 #ifdef CONFIG_SPL_FRAMEWORK
153 	int ret;
154 #if !defined(CONFIG_SUPPORT_TPL)
155 	struct udevice *dev;
156 #endif
157 #endif
158 
159 	rockchip_stimer_init();
160 #define EARLY_UART
161 #if defined(EARLY_UART) && defined(CONFIG_DEBUG_UART)
162 	/*
163 	 * Debug UART can be used from here if required:
164 	 *
165 	 * debug_uart_init();
166 	 * printch('a');
167 	 * printhex8(0x1234);
168 	 * printascii("string");
169 	 */
170 	debug_uart_init();
171 	printascii("U-Boot SPL board init");
172 #endif
173 	gd->sys_start_tick = get_ticks();
174 #ifdef CONFIG_SPL_FRAMEWORK
175 	ret = spl_early_init();
176 	if (ret) {
177 		printf("spl_early_init() failed: %d\n", ret);
178 		hang();
179 	}
180 #if !defined(CONFIG_SUPPORT_TPL)
181 	debug("\nspl:init dram\n");
182 	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
183 	if (ret) {
184 		printf("DRAM init failed: %d\n", ret);
185 		return;
186 	}
187 #endif
188 	preloader_console_init();
189 #else
190 	/* Some SoCs like rk3036 does not use any frame work */
191 	sdram_init();
192 #endif
193 
194 	arch_cpu_init();
195 	rk_board_init_f();
196 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
197 	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
198 #endif
199 
200 }
201 
202 #ifdef CONFIG_SPL_LOAD_FIT
203 int board_fit_config_name_match(const char *name)
204 {
205 	/* Just empty function now - can't decide what to choose */
206 	debug("%s: %s\n", __func__, name);
207 
208 	return 0;
209 }
210 #endif
211 
212 int board_init_f_boot_flags(void)
213 {
214 	int boot_flags = 0;
215 
216 	/* pre-loader serial */
217 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) && \
218     defined(CONFIG_ROCKCHIP_PRELOADER_ATAGS)
219 	struct tag *t;
220 
221 
222 	t = atags_get_tag(ATAG_SERIAL);
223 	if (t) {
224 		gd->serial.using_pre_serial = 1;
225 		gd->serial.enable = t->u.serial.enable;
226 		gd->serial.baudrate = t->u.serial.baudrate;
227 		gd->serial.addr = t->u.serial.addr;
228 		gd->serial.id = t->u.serial.id;
229 		gd->baudrate = t->u.serial.baudrate;
230 		if (!t->u.serial.enable)
231 			boot_flags |= GD_FLG_DISABLE_CONSOLE;
232 		debug("preloader: enable=%d, addr=0x%x, baudrate=%d, id=%d\n",
233 		      t->u.serial.enable, (u32)t->u.serial.addr,
234 		      t->u.serial.baudrate, t->u.serial.id);
235 	} else
236 #endif
237 	{
238 		gd->baudrate = CONFIG_BAUDRATE;
239 		gd->serial.baudrate = CONFIG_BAUDRATE;
240 		gd->serial.addr = CONFIG_DEBUG_UART_BASE;
241 	}
242 
243 	/* The highest priority to turn off (override) console */
244 #if defined(CONFIG_DISABLE_CONSOLE)
245 	boot_flags |= GD_FLG_DISABLE_CONSOLE;
246 #endif
247 
248 	return boot_flags;
249 }
250 
251 #ifdef CONFIG_SPL_BOARD_INIT
252 __weak int rk_spl_board_init(void)
253 {
254 	return 0;
255 }
256 
257 static int setup_led(void)
258 {
259 #ifdef CONFIG_SPL_LED
260 	struct udevice *dev;
261 	char *led_name;
262 	int ret;
263 
264 	led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
265 	if (!led_name)
266 		return 0;
267 	ret = led_get_by_label(led_name, &dev);
268 	if (ret) {
269 		debug("%s: get=%d\n", __func__, ret);
270 		return ret;
271 	}
272 	ret = led_set_state(dev, LEDST_ON);
273 	if (ret)
274 		return ret;
275 #endif
276 
277 	return 0;
278 }
279 
280 void spl_board_init(void)
281 {
282 	int ret;
283 
284 	ret = setup_led();
285 
286 	if (ret) {
287 		debug("LED ret=%d\n", ret);
288 		hang();
289 	}
290 
291 	rk_spl_board_init();
292 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
293 	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
294 #endif
295 	return;
296 }
297 #endif
298 
299 void spl_perform_fixups(struct spl_image_info *spl_image)
300 {
301 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS
302 	atags_set_bootdev_by_spl_bootdevice(spl_image->boot_device);
303 #endif
304 	return;
305 }
306 
307 #ifdef CONFIG_SPL_KERNEL_BOOT
308 static int spl_rockchip_dnl_key_pressed(void)
309 {
310 #if defined(CONFIG_SPL_INPUT)
311 	return key_read(KEY_VOLUMEUP);
312 #else
313 	return 0;
314 #endif
315 }
316 
317 void spl_next_stage(struct spl_image_info *spl)
318 {
319 	uint32_t reg_boot_mode;
320 
321 	if (spl_rockchip_dnl_key_pressed()) {
322 		spl->next_stage = SPL_NEXT_STAGE_UBOOT;
323 		return;
324 	}
325 
326 	reg_boot_mode = readl((void *)CONFIG_ROCKCHIP_BOOT_MODE_REG);
327 	switch (reg_boot_mode) {
328 	case BOOT_COLD:
329 	case BOOT_PANIC:
330 	case BOOT_WATCHDOG:
331 	case BOOT_NORMAL:
332 	case BOOT_RECOVERY:
333 		spl->next_stage = SPL_NEXT_STAGE_KERNEL;
334 		break;
335 	default:
336 		spl->next_stage = SPL_NEXT_STAGE_UBOOT;
337 	}
338 }
339 #endif
340 
341 #ifdef CONFIG_SPL_KERNEL_BOOT
342 const char *spl_kernel_partition(struct spl_image_info *spl,
343 				 struct spl_load_info *info)
344 {
345 	struct bootloader_message *bmsg = NULL;
346 	u32 boot_mode;
347 	int ret, cnt;
348 	u32 sector = 0;
349 
350 #ifdef CONFIG_SPL_LIBDISK_SUPPORT
351 	disk_partition_t part_info;
352 
353 	ret = part_get_info_by_name(info->dev, PART_MISC, &part_info);
354 	if (ret >= 0)
355 		sector = part_info.start;
356 #else
357 	sector = CONFIG_SPL_MISC_SECTOR;
358 #endif
359 	if (sector) {
360 		cnt = DIV_ROUND_UP(sizeof(*bmsg), info->bl_len);
361 		bmsg = memalign(ARCH_DMA_MINALIGN, cnt * info->bl_len);
362 		ret = info->read(info, sector + BCB_MESSAGE_BLK_OFFSET,
363 				 cnt, bmsg);
364 		if (ret == cnt && !strcmp(bmsg->command, "boot-recovery")) {
365 			free(bmsg);
366 			return PART_RECOVERY;
367 		} else {
368 			free(bmsg);
369 		}
370 	}
371 
372 	boot_mode = readl((void *)CONFIG_ROCKCHIP_BOOT_MODE_REG);
373 
374 	return (boot_mode == BOOT_RECOVERY) ? PART_RECOVERY : PART_BOOT;
375 }
376 #endif
377 
378 void spl_hang_reset(void)
379 {
380 	printf("# Reset the board to bootrom #\n");
381 #if defined(CONFIG_SPL_SYSRESET) && defined(CONFIG_SPL_DRIVERS_MISC_SUPPORT)
382 	writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG);
383 	do_reset(NULL, 0, 0, NULL);
384 #endif
385 }
386 
387 #ifdef CONFIG_SPL_FIT_ROLLBACK_PROTECT
388 int fit_read_otp_rollback_index(uint32_t fit_index, uint32_t *otp_index)
389 {
390 	int ret = 0;
391 
392 	*otp_index = 0;
393 #if defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP_V2)
394 	struct udevice *dev;
395 	u32 index, i, otp_version;
396 	u32 bit_count;
397 
398 	dev = misc_otp_get_device(OTP_S);
399 	if (!dev)
400 		return -ENODEV;
401 
402 	otp_version = 0;
403 	for (i = 0; i < OTP_UBOOT_ROLLBACK_WORDS; i++) {
404 		if (misc_otp_read(dev, 4 *
405 		    (OTP_UBOOT_ROLLBACK_OFFSET + i),
406 		    &index,
407 		    4)) {
408 			printf("Can't read rollback index\n");
409 			return -EIO;
410 		}
411 		bit_count = fls(index);
412 		otp_version += bit_count;
413 	}
414 	*otp_index = otp_version;
415 #endif
416 
417 	return ret;
418 }
419 
420 static int fit_write_otp_rollback_index(u32 fit_index)
421 {
422 #if defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP_V2)
423 	struct udevice *dev;
424 	u32 index, i, otp_index;
425 
426 	if (!fit_index)
427 		return 0;
428 
429 	if (fit_index > OTP_UBOOT_ROLLBACK_WORDS * 32)
430 		return -EINVAL;
431 
432 	dev = misc_otp_get_device(OTP_S);
433 	if (!dev)
434 		return -ENODEV;
435 
436 	if (fit_read_otp_rollback_index(fit_index, &otp_index))
437 		return -EIO;
438 
439 	if (otp_index < fit_index) {
440 		/* Write new SW version to otp */
441 		for (i = 0; i < OTP_UBOOT_ROLLBACK_WORDS; i++) {
442 			/* convert to base-1 representation */
443 			index = 0xffffffff >> (OTP_ALL_ONES_NUM_BITS -
444 				min(fit_index, (u32)OTP_ALL_ONES_NUM_BITS));
445 			fit_index -= min(fit_index,
446 					  (u32)OTP_ALL_ONES_NUM_BITS);
447 			if (index) {
448 				if (misc_otp_write(dev, 4 *
449 				    (OTP_UBOOT_ROLLBACK_OFFSET + i),
450 				    &index,
451 				    4)) {
452 					printf("Can't write rollback index\n");
453 					return -EIO;
454 				}
455 			}
456 		}
457 	}
458 #endif
459 
460 	return 0;
461 }
462 #endif
463 
464 int spl_board_prepare_for_jump(struct spl_image_info *spl_image)
465 {
466 #ifdef CONFIG_SPL_FIT_ROLLBACK_PROTECT
467 	int ret;
468 
469 	ret = fit_write_otp_rollback_index(gd->rollback_index);
470 	if (ret) {
471 		panic("Failed to write fit rollback index %d, ret=%d",
472 		      gd->rollback_index, ret);
473 	}
474 #endif
475 
476 #ifdef CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS
477 	misc_decompress_cleanup();
478 #endif
479 	return 0;
480 }
481