1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <version.h> 9 #include <boot_rkimg.h> 10 #include <debug_uart.h> 11 #include <dm.h> 12 #include <key.h> 13 #include <led.h> 14 #include <misc.h> 15 #include <ram.h> 16 #include <spl.h> 17 #include <optee_include/OpteeClientInterface.h> 18 #include <power/fuel_gauge.h> 19 #include <asm/arch/bootrom.h> 20 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 21 #include <asm/arch/rk_atags.h> 22 #endif 23 #include <asm/arch/pcie_ep_boot.h> 24 #include <asm/arch/sdram.h> 25 #include <asm/arch/boot_mode.h> 26 #include <asm/arch-rockchip/sys_proto.h> 27 #include <asm/io.h> 28 #include <asm/arch/param.h> 29 30 DECLARE_GLOBAL_DATA_PTR; 31 32 void board_return_to_bootrom(void) 33 { 34 back_to_bootrom(BROM_BOOT_NEXTSTAGE); 35 } 36 37 __weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { 38 }; 39 40 const char *board_spl_was_booted_from(void) 41 { 42 u32 bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR); 43 const char *bootdevice_ofpath = NULL; 44 45 if ((bootdevice_brom_id & BROM_DOWNLOAD_MASK) == BROM_DOWNLOAD_MASK) 46 bootdevice_brom_id = BROM_BOOTSOURCE_USB; 47 48 bootdevice_brom_id = bootdevice_brom_id & BROM_BOOTSOURCE_MASK; 49 if (bootdevice_brom_id < ARRAY_SIZE(boot_devices)) 50 bootdevice_ofpath = boot_devices[bootdevice_brom_id]; 51 52 if (bootdevice_ofpath) 53 debug("%s: brom_bootdevice_id %x maps to '%s'\n", 54 __func__, bootdevice_brom_id, bootdevice_ofpath); 55 else 56 debug("%s: failed to resolve brom_bootdevice_id %x\n", 57 __func__, bootdevice_brom_id); 58 59 return bootdevice_ofpath; 60 } 61 62 u32 spl_boot_device(void) 63 { 64 u32 boot_device = BOOT_DEVICE_MMC1; 65 66 #if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \ 67 defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \ 68 defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) 69 return BOOT_DEVICE_SPI; 70 #endif 71 if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)) 72 return BOOT_DEVICE_BOOTROM; 73 74 return boot_device; 75 } 76 77 u32 spl_boot_mode(const u32 boot_device) 78 { 79 return MMCSD_MODE_RAW; 80 } 81 82 __weak void rockchip_stimer_init(void) 83 { 84 /* If Timer already enabled, don't re-init it */ 85 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x10); 86 if ( reg & 0x1 ) 87 return; 88 #ifndef CONFIG_ARM64 89 asm volatile("mcr p15, 0, %0, c14, c0, 0" 90 : : "r"(COUNTER_FREQUENCY)); 91 #endif 92 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + 0x10); 93 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); 94 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); 95 writel(1, CONFIG_ROCKCHIP_STIMER_BASE + 0x10); 96 } 97 98 __weak int arch_cpu_init(void) 99 { 100 return 0; 101 } 102 103 __weak int rk_board_init_f(void) 104 { 105 return 0; 106 } 107 108 #ifndef CONFIG_SPL_LIBGENERIC_SUPPORT 109 void udelay(unsigned long usec) 110 { 111 __udelay(usec); 112 } 113 114 void hang(void) 115 { 116 bootstage_error(BOOTSTAGE_ID_NEED_RESET); 117 for (;;) 118 ; 119 } 120 121 /** 122 * memset - Fill a region of memory with the given value 123 * @s: Pointer to the start of the area. 124 * @c: The byte to fill the area with 125 * @count: The size of the area. 126 * 127 * Do not use memset() to access IO space, use memset_io() instead. 128 */ 129 void *memset(void *s, int c, size_t count) 130 { 131 unsigned long *sl = (unsigned long *)s; 132 char *s8; 133 134 #if !CONFIG_IS_ENABLED(TINY_MEMSET) 135 unsigned long cl = 0; 136 int i; 137 138 /* do it one word at a time (32 bits or 64 bits) while possible */ 139 if (((ulong)s & (sizeof(*sl) - 1)) == 0) { 140 for (i = 0; i < sizeof(*sl); i++) { 141 cl <<= 8; 142 cl |= c & 0xff; 143 } 144 while (count >= sizeof(*sl)) { 145 *sl++ = cl; 146 count -= sizeof(*sl); 147 } 148 } 149 #endif /* fill 8 bits at a time */ 150 s8 = (char *)sl; 151 while (count--) 152 *s8++ = c; 153 154 return s; 155 } 156 #endif 157 158 #ifdef CONFIG_SPL_DM_RESET 159 static void brom_download(void) 160 { 161 if (gd->console_evt == 0x02) { 162 printf("ctrl+b: Bootrom download!\n"); 163 writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG); 164 do_reset(NULL, 0, 0, NULL); 165 } 166 } 167 #endif 168 169 static void spl_hotkey_init(void) 170 { 171 /* If disable console, skip getting uart reg */ 172 if (!gd || gd->flags & GD_FLG_DISABLE_CONSOLE) 173 return; 174 if (!gd->have_console) 175 return; 176 177 /* serial uclass only exists when enable CONFIG_SPL_FRAMEWORK */ 178 #ifdef CONFIG_SPL_FRAMEWORK 179 if (serial_tstc()) { 180 gd->console_evt = serial_getc(); 181 #else 182 if (debug_uart_tstc()) { 183 gd->console_evt = debug_uart_getc(); 184 #endif 185 if (gd->console_evt <= 0x1a) /* 'z' */ 186 printf("SPL Hotkey: ctrl+%c\n", 187 gd->console_evt + 'a' - 1); 188 } 189 190 return; 191 } 192 193 void board_init_f(ulong dummy) 194 { 195 #ifdef CONFIG_SPL_FRAMEWORK 196 int ret; 197 #if !defined(CONFIG_SUPPORT_TPL) 198 struct udevice *dev; 199 #endif 200 #endif 201 gd->flags = dummy; 202 rockchip_stimer_init(); 203 #define EARLY_UART 204 #if defined(EARLY_UART) && defined(CONFIG_DEBUG_UART) 205 /* 206 * Debug UART can be used from here if required: 207 * 208 * debug_uart_init(); 209 * printch('a'); 210 * printhex8(0x1234); 211 * printascii("string"); 212 */ 213 if (!gd->serial.using_pre_serial && 214 !(gd->flags & GD_FLG_DISABLE_CONSOLE)) 215 debug_uart_init(); 216 printascii("U-Boot SPL board init"); 217 #endif 218 gd->sys_start_tick = get_ticks(); 219 #ifdef CONFIG_SPL_PCIE_EP_SUPPORT 220 rockchip_pcie_ep_init(); 221 #endif 222 #ifdef CONFIG_SPL_FRAMEWORK 223 ret = spl_early_init(); 224 if (ret) { 225 printf("spl_early_init() failed: %d\n", ret); 226 hang(); 227 } 228 #if !defined(CONFIG_SUPPORT_TPL) 229 debug("\nspl:init dram\n"); 230 ret = uclass_get_device(UCLASS_RAM, 0, &dev); 231 if (ret) { 232 printf("DRAM init failed: %d\n", ret); 233 return; 234 } 235 #endif 236 preloader_console_init(); 237 #else 238 /* Some SoCs like rk3036 does not use any frame work */ 239 sdram_init(); 240 #endif 241 /* Get hotkey and store in gd */ 242 spl_hotkey_init(); 243 #ifdef CONFIG_SPL_DM_RESET 244 brom_download(); 245 #endif 246 arch_cpu_init(); 247 rk_board_init_f(); 248 #if defined(CONFIG_SPL_RAM_DEVICE) && defined(CONFIG_SPL_PCIE_EP_SUPPORT) 249 rockchip_pcie_ep_get_firmware(); 250 #endif 251 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) 252 back_to_bootrom(BROM_BOOT_NEXTSTAGE); 253 #endif 254 255 } 256 257 #ifdef CONFIG_SPL_LOAD_FIT 258 int board_fit_config_name_match(const char *name) 259 { 260 /* Just empty function now - can't decide what to choose */ 261 debug("%s: %s\n", __func__, name); 262 263 return 0; 264 } 265 #endif 266 267 int board_init_f_boot_flags(void) 268 { 269 int boot_flags = 0; 270 271 #if CONFIG_IS_ENABLED(FPGA_ROCKCHIP) 272 arch_fpga_init(); 273 #endif 274 #ifdef CONFIG_PSTORE 275 param_parse_pstore(); 276 #endif 277 /* pre-loader serial */ 278 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) && \ 279 defined(CONFIG_ROCKCHIP_PRELOADER_ATAGS) 280 struct tag *t; 281 282 t = atags_get_tag(ATAG_SERIAL); 283 if (t) { 284 gd->serial.using_pre_serial = 1; 285 gd->serial.enable = t->u.serial.enable; 286 gd->serial.baudrate = t->u.serial.baudrate; 287 gd->serial.addr = t->u.serial.addr; 288 gd->serial.id = t->u.serial.id; 289 gd->baudrate = t->u.serial.baudrate; 290 if (!t->u.serial.enable) 291 boot_flags |= GD_FLG_DISABLE_CONSOLE; 292 debug("preloader: enable=%d, addr=0x%x, baudrate=%d, id=%d\n", 293 t->u.serial.enable, (u32)t->u.serial.addr, 294 t->u.serial.baudrate, t->u.serial.id); 295 } else 296 #endif 297 { 298 gd->baudrate = CONFIG_BAUDRATE; 299 gd->serial.baudrate = CONFIG_BAUDRATE; 300 gd->serial.addr = CONFIG_DEBUG_UART_BASE; 301 } 302 303 /* The highest priority to turn off (override) console */ 304 #if defined(CONFIG_DISABLE_CONSOLE) 305 boot_flags |= GD_FLG_DISABLE_CONSOLE; 306 #endif 307 308 return boot_flags; 309 } 310 311 #ifdef CONFIG_SPL_BOARD_INIT 312 __weak int rk_spl_board_init(void) 313 { 314 return 0; 315 } 316 317 static int setup_led(void) 318 { 319 #ifdef CONFIG_SPL_LED 320 struct udevice *dev; 321 char *led_name; 322 int ret; 323 324 led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led"); 325 if (!led_name) 326 return 0; 327 ret = led_get_by_label(led_name, &dev); 328 if (ret) { 329 debug("%s: get=%d\n", __func__, ret); 330 return ret; 331 } 332 ret = led_set_state(dev, LEDST_ON); 333 if (ret) 334 return ret; 335 #endif 336 337 return 0; 338 } 339 340 void spl_board_init(void) 341 { 342 int ret; 343 344 ret = setup_led(); 345 346 if (ret) { 347 debug("LED ret=%d\n", ret); 348 hang(); 349 } 350 351 rk_spl_board_init(); 352 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) 353 back_to_bootrom(BROM_BOOT_NEXTSTAGE); 354 #endif 355 return; 356 } 357 #endif 358 359 #ifdef CONFIG_SPL_KERNEL_BOOT 360 static int spl_rockchip_dnl_key_pressed(void) 361 { 362 #if defined(CONFIG_SPL_INPUT) 363 return key_read(KEY_VOLUMEUP); 364 #else 365 return 0; 366 #endif 367 } 368 369 #ifdef CONFIG_SPL_DM_FUEL_GAUGE 370 bool spl_is_low_power(void) 371 { 372 struct udevice *dev; 373 int ret, voltage; 374 375 ret = uclass_get_device(UCLASS_FG, 0, &dev); 376 if (ret) { 377 debug("Get charge display failed, ret=%d\n", ret); 378 return false; 379 } 380 381 voltage = fuel_gauge_get_voltage(dev); 382 if (voltage >= CONFIG_SPL_POWER_LOW_VOLTAGE_THRESHOLD) 383 return false; 384 385 return true; 386 } 387 #endif 388 389 void spl_next_stage(struct spl_image_info *spl) 390 { 391 const char *reason[] = { "Recovery key", "Ctrl+c", "LowPwr", "Other" }; 392 uint32_t reg_boot_mode; 393 int i = 0; 394 395 if (spl_rockchip_dnl_key_pressed()) { 396 i = 0; 397 spl->next_stage = SPL_NEXT_STAGE_UBOOT; 398 goto out; 399 } 400 401 if (gd->console_evt == 0x03) { 402 i = 1; 403 spl->next_stage = SPL_NEXT_STAGE_UBOOT; 404 goto out; 405 } 406 407 #ifdef CONFIG_SPL_DM_FUEL_GAUGE 408 if (spl_is_low_power()) { 409 i = 2; 410 spl->next_stage = SPL_NEXT_STAGE_UBOOT; 411 goto out; 412 } 413 #endif 414 415 reg_boot_mode = readl((void *)CONFIG_ROCKCHIP_BOOT_MODE_REG); 416 switch (reg_boot_mode) { 417 case BOOT_LOADER: 418 case BOOT_FASTBOOT: 419 case BOOT_CHARGING: 420 case BOOT_UMS: 421 case BOOT_DFU: 422 i = 3; 423 spl->next_stage = SPL_NEXT_STAGE_UBOOT; 424 break; 425 default: 426 spl->next_stage = SPL_NEXT_STAGE_KERNEL; 427 } 428 429 out: 430 if (spl->next_stage == SPL_NEXT_STAGE_UBOOT) 431 printf("Enter uboot reason: %s\n", reason[i]); 432 433 return; 434 } 435 #endif 436 437 #ifdef CONFIG_SPL_KERNEL_BOOT 438 const char *spl_kernel_partition(struct spl_image_info *spl, 439 struct spl_load_info *info) 440 { 441 struct bootloader_message *bmsg = NULL; 442 u32 boot_mode; 443 int ret, cnt; 444 u32 sector = 0; 445 446 #ifdef CONFIG_SPL_LIBDISK_SUPPORT 447 disk_partition_t part_info; 448 449 ret = part_get_info_by_name(info->dev, PART_MISC, &part_info); 450 if (ret >= 0) 451 sector = part_info.start; 452 #else 453 sector = CONFIG_SPL_MISC_SECTOR; 454 #endif 455 if (sector) { 456 cnt = DIV_ROUND_UP(sizeof(*bmsg), info->bl_len); 457 bmsg = memalign(ARCH_DMA_MINALIGN, cnt * info->bl_len); 458 ret = info->read(info, sector + BCB_MESSAGE_BLK_OFFSET, 459 cnt, bmsg); 460 if (ret == cnt && !strcmp(bmsg->command, "boot-recovery")) { 461 free(bmsg); 462 return PART_RECOVERY; 463 } else { 464 free(bmsg); 465 } 466 } 467 468 boot_mode = readl((void *)CONFIG_ROCKCHIP_BOOT_MODE_REG); 469 470 return (boot_mode == BOOT_RECOVERY) ? PART_RECOVERY : PART_BOOT; 471 } 472 473 static void spl_fdt_fixup_memory(struct spl_image_info *spl_image) 474 { 475 void *blob = spl_image->fdt_addr; 476 struct tag *t; 477 u64 start[CONFIG_NR_DRAM_BANKS]; 478 u64 size[CONFIG_NR_DRAM_BANKS]; 479 int i, count, err; 480 481 err = fdt_check_header(blob); 482 if (err < 0) { 483 printf("Invalid dtb\n"); 484 return; 485 } 486 487 /* Fixup memory node based on ddr_mem atags */ 488 t = atags_get_tag(ATAG_DDR_MEM); 489 if (t && t->u.ddr_mem.count) { 490 count = t->u.ddr_mem.count; 491 for (i = 0; i < count; i++) { 492 start[i] = t->u.ddr_mem.bank[i]; 493 size[i] = t->u.ddr_mem.bank[i + count]; 494 if (size[i] == 0) 495 continue; 496 debug("Adding bank: 0x%08llx - 0x%08llx (size: 0x%08llx)\n", 497 start[i], start[i] + size[i], size[i]); 498 } 499 err = fdt_fixup_memory_banks(blob, start, size, count); 500 if (err < 0) { 501 printf("Fixup kernel dtb memory node failed: %s\n", fdt_strerror(err)); 502 return; 503 } 504 } 505 506 return; 507 } 508 #endif 509 510 void spl_perform_fixups(struct spl_image_info *spl_image) 511 { 512 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 513 atags_set_bootdev_by_spl_bootdevice(spl_image->boot_device); 514 #ifdef BUILD_SPL_TAG 515 atags_set_shared_fwver(FW_SPL, "spl-"BUILD_SPL_TAG); 516 #endif 517 #endif 518 #if defined(CONFIG_SPL_KERNEL_BOOT) 519 if (spl_image->next_stage == SPL_NEXT_STAGE_KERNEL) 520 spl_fdt_fixup_memory(spl_image); 521 #endif 522 return; 523 } 524 525 void spl_hang_reset(void) 526 { 527 printf("# Reset the board to bootrom #\n"); 528 #if defined(CONFIG_SPL_SYSRESET) && defined(CONFIG_SPL_DRIVERS_MISC_SUPPORT) 529 /* reset is available after dm setup */ 530 if (gd->flags & GD_FLG_SPL_EARLY_INIT) { 531 writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG); 532 do_reset(NULL, 0, 0, NULL); 533 } 534 #endif 535 } 536 537 #ifdef CONFIG_SPL_FIT_ROLLBACK_PROTECT 538 int fit_read_otp_rollback_index(uint32_t fit_index, uint32_t *otp_index) 539 { 540 int ret = 0; 541 542 *otp_index = 0; 543 #if defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP) 544 struct udevice *dev; 545 u32 index, i, otp_version; 546 u32 bit_count; 547 548 dev = misc_otp_get_device(OTP_S); 549 if (!dev) 550 return -ENODEV; 551 552 otp_version = 0; 553 for (i = 0; i < OTP_UBOOT_ROLLBACK_WORDS; i++) { 554 if (misc_otp_read(dev, OTP_UBOOT_ROLLBACK_OFFSET + i * 4, 555 &index, 556 4)) { 557 printf("Can't read rollback index\n"); 558 return -EIO; 559 } 560 561 bit_count = fls(index); 562 otp_version += bit_count; 563 } 564 *otp_index = otp_version; 565 #endif 566 567 return ret; 568 } 569 570 static int fit_write_otp_rollback_index(u32 fit_index) 571 { 572 #if defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP) 573 struct udevice *dev; 574 u32 index, i, otp_index; 575 576 if (!fit_index) 577 return 0; 578 579 if (fit_index > OTP_UBOOT_ROLLBACK_WORDS * 32) 580 return -EINVAL; 581 582 dev = misc_otp_get_device(OTP_S); 583 if (!dev) 584 return -ENODEV; 585 586 if (fit_read_otp_rollback_index(fit_index, &otp_index)) 587 return -EIO; 588 589 if (otp_index < fit_index) { 590 /* Write new SW version to otp */ 591 for (i = 0; i < OTP_UBOOT_ROLLBACK_WORDS; i++) { 592 /* 593 * If fit_index is equal to 0, then execute 0xffffffff >> 32. 594 * But the operand can only be 0 - 31. The "0xffffffff >> 32" is 595 * actually be "0xffffffff >> 0". 596 */ 597 if (!fit_index) 598 break; 599 /* convert to base-1 representation */ 600 index = 0xffffffff >> (OTP_ALL_ONES_NUM_BITS - 601 min(fit_index, (u32)OTP_ALL_ONES_NUM_BITS)); 602 fit_index -= min(fit_index, 603 (u32)OTP_ALL_ONES_NUM_BITS); 604 if (index) { 605 if (misc_otp_write(dev, OTP_UBOOT_ROLLBACK_OFFSET + i * 4, 606 &index, 607 4)) { 608 printf("Can't write rollback index\n"); 609 return -EIO; 610 } 611 } 612 } 613 } 614 #endif 615 616 return 0; 617 } 618 #endif 619 620 int spl_board_prepare_for_jump(struct spl_image_info *spl_image) 621 { 622 #ifdef CONFIG_SPL_FIT_ROLLBACK_PROTECT 623 int ret; 624 625 ret = fit_write_otp_rollback_index(gd->rollback_index); 626 if (ret) { 627 panic("Failed to write fit rollback index %d, ret=%d", 628 gd->rollback_index, ret); 629 } 630 #endif 631 632 #ifdef CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS 633 misc_decompress_cleanup(); 634 #endif 635 return 0; 636 } 637