1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <version.h> 9 #include <boot_rkimg.h> 10 #include <debug_uart.h> 11 #include <dm.h> 12 #include <key.h> 13 #include <led.h> 14 #include <misc.h> 15 #include <ram.h> 16 #include <spl.h> 17 #include <optee_include/OpteeClientInterface.h> 18 #include <power/fuel_gauge.h> 19 #include <asm/arch/bootrom.h> 20 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 21 #include <asm/arch/rk_atags.h> 22 #endif 23 #include <asm/arch/pcie_ep_boot.h> 24 #include <asm/arch/sdram.h> 25 #include <asm/arch/boot_mode.h> 26 #include <asm/arch-rockchip/sys_proto.h> 27 #include <asm/io.h> 28 #include <asm/arch/param.h> 29 #include <asm/arch/rk_hwid.h> 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 void board_return_to_bootrom(void) 34 { 35 back_to_bootrom(BROM_BOOT_NEXTSTAGE); 36 } 37 38 __weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { 39 }; 40 41 __weak void spl_rk_board_prepare_for_jump(struct spl_image_info *spl_image) 42 { 43 } 44 45 const char *board_spl_was_booted_from(void) 46 { 47 u32 bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR); 48 const char *bootdevice_ofpath = NULL; 49 50 if ((bootdevice_brom_id & BROM_DOWNLOAD_MASK) == BROM_DOWNLOAD_MASK) 51 bootdevice_brom_id = BROM_BOOTSOURCE_USB; 52 53 bootdevice_brom_id = bootdevice_brom_id & BROM_BOOTSOURCE_MASK; 54 if (bootdevice_brom_id < ARRAY_SIZE(boot_devices)) 55 bootdevice_ofpath = boot_devices[bootdevice_brom_id]; 56 57 if (bootdevice_ofpath) 58 debug("%s: brom_bootdevice_id %x maps to '%s'\n", 59 __func__, bootdevice_brom_id, bootdevice_ofpath); 60 else 61 debug("%s: failed to resolve brom_bootdevice_id %x\n", 62 __func__, bootdevice_brom_id); 63 64 return bootdevice_ofpath; 65 } 66 67 u32 spl_boot_device(void) 68 { 69 u32 boot_device = BOOT_DEVICE_MMC1; 70 71 #if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \ 72 defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \ 73 defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) 74 return BOOT_DEVICE_SPI; 75 #endif 76 if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)) 77 return BOOT_DEVICE_BOOTROM; 78 79 return boot_device; 80 } 81 82 u32 spl_boot_mode(const u32 boot_device) 83 { 84 return MMCSD_MODE_RAW; 85 } 86 87 __weak void rockchip_stimer_init(void) 88 { 89 /* If Timer already enabled, don't re-init it */ 90 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x10); 91 if ( reg & 0x1 ) 92 return; 93 #ifdef COUNTER_FREQUENCY 94 #ifndef CONFIG_ARM64 95 asm volatile("mcr p15, 0, %0, c14, c0, 0" 96 : : "r"(COUNTER_FREQUENCY)); 97 #endif 98 #endif 99 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + 0x10); 100 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); 101 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); 102 writel(1, CONFIG_ROCKCHIP_STIMER_BASE + 0x10); 103 } 104 105 __weak int arch_cpu_init(void) 106 { 107 return 0; 108 } 109 110 __weak int rk_board_init_f(void) 111 { 112 return 0; 113 } 114 115 #ifndef CONFIG_SPL_LIBGENERIC_SUPPORT 116 void udelay(unsigned long usec) 117 { 118 __udelay(usec); 119 } 120 121 void hang(void) 122 { 123 bootstage_error(BOOTSTAGE_ID_NEED_RESET); 124 for (;;) 125 ; 126 } 127 128 /** 129 * memset - Fill a region of memory with the given value 130 * @s: Pointer to the start of the area. 131 * @c: The byte to fill the area with 132 * @count: The size of the area. 133 * 134 * Do not use memset() to access IO space, use memset_io() instead. 135 */ 136 void *memset(void *s, int c, size_t count) 137 { 138 unsigned long *sl = (unsigned long *)s; 139 char *s8; 140 141 #if !CONFIG_IS_ENABLED(TINY_MEMSET) 142 unsigned long cl = 0; 143 int i; 144 145 /* do it one word at a time (32 bits or 64 bits) while possible */ 146 if (((ulong)s & (sizeof(*sl) - 1)) == 0) { 147 for (i = 0; i < sizeof(*sl); i++) { 148 cl <<= 8; 149 cl |= c & 0xff; 150 } 151 while (count >= sizeof(*sl)) { 152 *sl++ = cl; 153 count -= sizeof(*sl); 154 } 155 } 156 #endif /* fill 8 bits at a time */ 157 s8 = (char *)sl; 158 while (count--) 159 *s8++ = c; 160 161 return s; 162 } 163 #endif 164 165 #ifdef CONFIG_SPL_DM_RESET 166 static void brom_download(void) 167 { 168 if (gd->console_evt == 0x02) { 169 printf("ctrl+b: Bootrom download!\n"); 170 writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG); 171 do_reset(NULL, 0, 0, NULL); 172 } 173 } 174 #endif 175 176 static void spl_hotkey_init(void) 177 { 178 /* If disable console, skip getting uart reg */ 179 if (!gd || gd->flags & GD_FLG_DISABLE_CONSOLE) 180 return; 181 if (!gd->have_console) 182 return; 183 184 /* serial uclass only exists when enable CONFIG_SPL_FRAMEWORK */ 185 #ifdef CONFIG_SPL_FRAMEWORK 186 if (serial_tstc()) { 187 gd->console_evt = serial_getc(); 188 #else 189 if (debug_uart_tstc()) { 190 gd->console_evt = debug_uart_getc(); 191 #endif 192 if (gd->console_evt <= 0x1a) /* 'z' */ 193 printf("SPL Hotkey: ctrl+%c\n", 194 gd->console_evt + 'a' - 1); 195 } 196 197 return; 198 } 199 200 void board_init_f(ulong dummy) 201 { 202 #ifdef CONFIG_SPL_FRAMEWORK 203 int ret; 204 #if !defined(CONFIG_SUPPORT_TPL) 205 struct udevice *dev; 206 #endif 207 #endif 208 gd->flags = dummy; 209 rockchip_stimer_init(); 210 #define EARLY_UART 211 #if defined(EARLY_UART) && defined(CONFIG_DEBUG_UART) 212 /* 213 * Debug UART can be used from here if required: 214 * 215 * debug_uart_init(); 216 * printch('a'); 217 * printhex8(0x1234); 218 * printascii("string"); 219 */ 220 if (!gd->serial.using_pre_serial && 221 !(gd->flags & GD_FLG_DISABLE_CONSOLE)) 222 debug_uart_init(); 223 printascii("U-Boot SPL board init"); 224 #endif 225 gd->sys_start_tick = get_ticks(); 226 #ifdef CONFIG_SPL_PCIE_EP_SUPPORT 227 rockchip_pcie_ep_init(); 228 #endif 229 #ifdef CONFIG_SPL_FRAMEWORK 230 ret = spl_early_init(); 231 if (ret) { 232 printf("spl_early_init() failed: %d\n", ret); 233 hang(); 234 } 235 #if !defined(CONFIG_SUPPORT_TPL) 236 debug("\nspl:init dram\n"); 237 ret = uclass_get_device(UCLASS_RAM, 0, &dev); 238 if (ret) { 239 printf("DRAM init failed: %d\n", ret); 240 return; 241 } 242 #endif 243 preloader_console_init(); 244 #else 245 /* Some SoCs like rk3036 does not use any frame work */ 246 sdram_init(); 247 #endif 248 /* Get hotkey and store in gd */ 249 spl_hotkey_init(); 250 #ifdef CONFIG_SPL_DM_RESET 251 brom_download(); 252 #endif 253 arch_cpu_init(); 254 rk_board_init_f(); 255 #if defined(CONFIG_SPL_RAM_DEVICE) && defined(CONFIG_SPL_PCIE_EP_SUPPORT) 256 rockchip_pcie_ep_get_firmware(); 257 #endif 258 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) 259 back_to_bootrom(BROM_BOOT_NEXTSTAGE); 260 #endif 261 262 } 263 264 #ifdef CONFIG_SPL_LOAD_FIT 265 int board_fit_config_name_match(const char *name) 266 { 267 /* Just empty function now - can't decide what to choose */ 268 debug("%s: %s\n", __func__, name); 269 270 return 0; 271 } 272 #endif 273 274 int board_init_f_boot_flags(void) 275 { 276 int boot_flags = 0; 277 278 #ifdef CONFIG_ARM64 279 asm volatile("mrs %0, cntfrq_el0" : "=r" (gd->arch.timer_rate_hz)); 280 #else 281 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (gd->arch.timer_rate_hz)); 282 #endif 283 284 #if CONFIG_IS_ENABLED(FPGA_ROCKCHIP) 285 arch_fpga_init(); 286 #endif 287 #ifdef CONFIG_PSTORE 288 param_parse_pstore(); 289 #endif 290 /* pre-loader serial */ 291 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) && \ 292 defined(CONFIG_ROCKCHIP_PRELOADER_ATAGS) 293 struct tag *t; 294 295 t = atags_get_tag(ATAG_SERIAL); 296 if (t) { 297 gd->serial.using_pre_serial = 1; 298 gd->serial.enable = t->u.serial.enable; 299 gd->serial.baudrate = t->u.serial.baudrate; 300 gd->serial.addr = t->u.serial.addr; 301 gd->serial.id = t->u.serial.id; 302 gd->baudrate = t->u.serial.baudrate; 303 if (!t->u.serial.enable) 304 boot_flags |= GD_FLG_DISABLE_CONSOLE; 305 debug("preloader: enable=%d, addr=0x%x, baudrate=%d, id=%d\n", 306 t->u.serial.enable, (u32)t->u.serial.addr, 307 t->u.serial.baudrate, t->u.serial.id); 308 } else 309 #endif 310 { 311 gd->baudrate = CONFIG_BAUDRATE; 312 gd->serial.baudrate = CONFIG_BAUDRATE; 313 gd->serial.addr = CONFIG_DEBUG_UART_BASE; 314 } 315 316 /* The highest priority to turn off (override) console */ 317 #if defined(CONFIG_DISABLE_CONSOLE) 318 boot_flags |= GD_FLG_DISABLE_CONSOLE; 319 #endif 320 321 return boot_flags; 322 } 323 324 #ifdef CONFIG_SPL_BOARD_INIT 325 __weak int rk_spl_board_init(void) 326 { 327 return 0; 328 } 329 330 static int setup_led(void) 331 { 332 #ifdef CONFIG_SPL_LED 333 struct udevice *dev; 334 char *led_name; 335 int ret; 336 337 led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led"); 338 if (!led_name) 339 return 0; 340 ret = led_get_by_label(led_name, &dev); 341 if (ret) { 342 debug("%s: get=%d\n", __func__, ret); 343 return ret; 344 } 345 ret = led_set_state(dev, LEDST_ON); 346 if (ret) 347 return ret; 348 #endif 349 350 return 0; 351 } 352 353 void spl_board_init(void) 354 { 355 int ret; 356 357 ret = setup_led(); 358 359 if (ret) { 360 debug("LED ret=%d\n", ret); 361 hang(); 362 } 363 364 rk_spl_board_init(); 365 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) 366 back_to_bootrom(BROM_BOOT_NEXTSTAGE); 367 #endif 368 return; 369 } 370 #endif 371 372 #ifdef CONFIG_SPL_KERNEL_BOOT 373 static int spl_rockchip_dnl_key_pressed(void) 374 { 375 #if defined(CONFIG_SPL_INPUT) 376 return key_read(KEY_VOLUMEUP); 377 #else 378 return 0; 379 #endif 380 } 381 382 #ifdef CONFIG_SPL_DM_FUEL_GAUGE 383 bool spl_is_low_power(void) 384 { 385 struct udevice *dev; 386 int ret, voltage; 387 388 ret = uclass_get_device(UCLASS_FG, 0, &dev); 389 if (ret) { 390 debug("Get charge display failed, ret=%d\n", ret); 391 return false; 392 } 393 394 voltage = fuel_gauge_get_voltage(dev); 395 if (voltage >= CONFIG_SPL_POWER_LOW_VOLTAGE_THRESHOLD) 396 return false; 397 398 return true; 399 } 400 #endif 401 402 void spl_next_stage(struct spl_image_info *spl) 403 { 404 const char *reason[] = { "Recovery key", "Ctrl+c", "LowPwr", "Other" }; 405 uint32_t reg_boot_mode; 406 int i = 0; 407 408 if (spl_rockchip_dnl_key_pressed()) { 409 i = 0; 410 spl->next_stage = SPL_NEXT_STAGE_UBOOT; 411 goto out; 412 } 413 414 if (gd->console_evt == 0x03) { 415 i = 1; 416 spl->next_stage = SPL_NEXT_STAGE_UBOOT; 417 goto out; 418 } 419 420 #ifdef CONFIG_SPL_DM_FUEL_GAUGE 421 if (spl_is_low_power()) { 422 i = 2; 423 spl->next_stage = SPL_NEXT_STAGE_UBOOT; 424 goto out; 425 } 426 #endif 427 428 reg_boot_mode = readl((void *)CONFIG_ROCKCHIP_BOOT_MODE_REG); 429 switch (reg_boot_mode) { 430 case BOOT_LOADER: 431 case BOOT_FASTBOOT: 432 case BOOT_CHARGING: 433 case BOOT_UMS: 434 case BOOT_DFU: 435 i = 3; 436 spl->next_stage = SPL_NEXT_STAGE_UBOOT; 437 break; 438 default: 439 spl->next_stage = SPL_NEXT_STAGE_KERNEL; 440 } 441 442 out: 443 if (spl->next_stage == SPL_NEXT_STAGE_UBOOT) 444 printf("Enter uboot reason: %s\n", reason[i]); 445 446 return; 447 } 448 449 const char *spl_kernel_partition(struct spl_image_info *spl, 450 struct spl_load_info *info) 451 { 452 struct bootloader_message *bmsg = NULL; 453 u32 boot_mode; 454 int ret, cnt; 455 u32 sector = 0; 456 457 #ifdef CONFIG_SPL_LIBDISK_SUPPORT 458 disk_partition_t part_info; 459 460 ret = part_get_info_by_name(info->dev, PART_MISC, &part_info); 461 if (ret >= 0) 462 sector = part_info.start; 463 #else 464 sector = CONFIG_SPL_MISC_SECTOR; 465 #endif 466 if (sector) { 467 cnt = DIV_ROUND_UP(sizeof(*bmsg), info->bl_len); 468 bmsg = memalign(ARCH_DMA_MINALIGN, cnt * info->bl_len); 469 ret = info->read(info, sector + BCB_MESSAGE_BLK_OFFSET, 470 cnt, bmsg); 471 if (ret == cnt && !strcmp(bmsg->command, "boot-recovery")) { 472 free(bmsg); 473 return PART_RECOVERY; 474 } else { 475 free(bmsg); 476 } 477 } 478 479 boot_mode = readl((void *)CONFIG_ROCKCHIP_BOOT_MODE_REG); 480 481 return (boot_mode == BOOT_RECOVERY) ? PART_RECOVERY : PART_BOOT; 482 } 483 484 __weak void spl_fdt_fixup_memory(struct spl_image_info *spl_image) 485 { 486 void *blob = spl_image->fdt_addr; 487 struct tag *t; 488 u64 start[CONFIG_NR_DRAM_BANKS]; 489 u64 size[CONFIG_NR_DRAM_BANKS]; 490 int i, count, err; 491 492 err = fdt_check_header(blob); 493 if (err < 0) { 494 printf("Invalid dtb\n"); 495 return; 496 } 497 498 /* Fixup memory node based on ddr_mem atags */ 499 t = atags_get_tag(ATAG_DDR_MEM); 500 if (t && t->u.ddr_mem.count) { 501 count = t->u.ddr_mem.count; 502 for (i = 0; i < count; i++) { 503 start[i] = t->u.ddr_mem.bank[i]; 504 size[i] = t->u.ddr_mem.bank[i + count]; 505 if (size[i] == 0) 506 continue; 507 debug("Adding bank: 0x%08llx - 0x%08llx (size: 0x%08llx)\n", 508 start[i], start[i] + size[i], size[i]); 509 } 510 511 fdt_increase_size(blob, 512); 512 513 err = fdt_fixup_memory_banks(blob, start, size, count); 514 if (err < 0) { 515 printf("Fixup kernel dtb memory node failed: %s\n", fdt_strerror(err)); 516 return; 517 } 518 } 519 520 return; 521 } 522 523 #if defined(CONFIG_SPL_ROCKCHIP_HWID_DTB) 524 int spl_find_hwid_dtb(const char *fdt_name) 525 { 526 hwid_init_data(); 527 528 return hwid_dtb_is_available(fdt_name); 529 } 530 #endif 531 #endif 532 533 void spl_perform_fixups(struct spl_image_info *spl_image) 534 { 535 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 536 atags_set_bootdev_by_spl_bootdevice(spl_image->boot_device); 537 #ifdef BUILD_SPL_TAG 538 atags_set_shared_fwver(FW_SPL, "spl-"BUILD_SPL_TAG); 539 #endif 540 #endif 541 #if defined(CONFIG_SPL_KERNEL_BOOT) 542 if (spl_image->next_stage == SPL_NEXT_STAGE_KERNEL) 543 spl_fdt_fixup_memory(spl_image); 544 #endif 545 return; 546 } 547 548 void spl_hang_reset(void) 549 { 550 printf("# Reset the board to bootrom #\n"); 551 #if defined(CONFIG_SPL_SYSRESET) && defined(CONFIG_SPL_DRIVERS_MISC_SUPPORT) 552 /* reset is available after dm setup */ 553 if (gd->flags & GD_FLG_SPL_EARLY_INIT) { 554 writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG); 555 do_reset(NULL, 0, 0, NULL); 556 } 557 #endif 558 } 559 560 #ifdef CONFIG_SPL_FIT_ROLLBACK_PROTECT 561 int fit_read_otp_rollback_index(uint32_t fit_index, uint32_t *otp_index) 562 { 563 int ret = 0; 564 565 *otp_index = 0; 566 #if defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP) 567 struct udevice *dev; 568 u32 index, i, otp_version; 569 u32 bit_count; 570 571 dev = misc_otp_get_device(OTP_S); 572 if (!dev) 573 return -ENODEV; 574 575 otp_version = 0; 576 for (i = 0; i < OTP_UBOOT_ROLLBACK_WORDS; i++) { 577 if (misc_otp_read(dev, OTP_UBOOT_ROLLBACK_OFFSET + i * 4, 578 &index, 579 4)) { 580 printf("Can't read rollback index\n"); 581 return -EIO; 582 } 583 584 bit_count = fls(index); 585 otp_version += bit_count; 586 } 587 *otp_index = otp_version; 588 #endif 589 590 return ret; 591 } 592 593 static int fit_write_otp_rollback_index(u32 fit_index) 594 { 595 #if defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP) 596 struct udevice *dev; 597 u32 index, i, otp_index; 598 599 if (!fit_index) 600 return 0; 601 602 if (fit_index > OTP_UBOOT_ROLLBACK_WORDS * 32) 603 return -EINVAL; 604 605 dev = misc_otp_get_device(OTP_S); 606 if (!dev) 607 return -ENODEV; 608 609 if (fit_read_otp_rollback_index(fit_index, &otp_index)) 610 return -EIO; 611 612 if (otp_index < fit_index) { 613 /* Write new SW version to otp */ 614 for (i = 0; i < OTP_UBOOT_ROLLBACK_WORDS; i++) { 615 /* 616 * If fit_index is equal to 0, then execute 0xffffffff >> 32. 617 * But the operand can only be 0 - 31. The "0xffffffff >> 32" is 618 * actually be "0xffffffff >> 0". 619 */ 620 if (!fit_index) 621 break; 622 /* convert to base-1 representation */ 623 index = 0xffffffff >> (OTP_ALL_ONES_NUM_BITS - 624 min(fit_index, (u32)OTP_ALL_ONES_NUM_BITS)); 625 fit_index -= min(fit_index, 626 (u32)OTP_ALL_ONES_NUM_BITS); 627 if (index) { 628 if (misc_otp_write(dev, OTP_UBOOT_ROLLBACK_OFFSET + i * 4, 629 &index, 630 4)) { 631 printf("Can't write rollback index\n"); 632 return -EIO; 633 } 634 } 635 } 636 } 637 #endif 638 639 return 0; 640 } 641 #endif 642 643 int spl_board_prepare_for_jump(struct spl_image_info *spl_image) 644 { 645 #ifdef CONFIG_SPL_FIT_ROLLBACK_PROTECT 646 int ret; 647 648 ret = fit_write_otp_rollback_index(gd->rollback_index); 649 if (ret) { 650 panic("Failed to write fit rollback index %d, ret=%d", 651 gd->rollback_index, ret); 652 } 653 #endif 654 655 #ifdef CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS 656 misc_decompress_cleanup(); 657 #endif 658 spl_rk_board_prepare_for_jump(spl_image); 659 660 return 0; 661 } 662